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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b21-20020a170902d31500b001d5081be740sm2027519plc.62.2024.01.18.18.35.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 18:35:02 -0800 (PST) From: Kito Cheng To: rep.dot.nop@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org Cc: Kito Cheng Subject: [PATCH] RISC-V: Tweak the wording for the sorry message Date: Fri, 19 Jan 2024 10:34:57 +0800 Message-Id: <20240119023457.1870618-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788484510323611439 X-GMAIL-MSGID: 1788484510323611439 Use "does not" rather than "cannot", because it's implementation issue. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_override_options_internal): Tweak sorry message. --- gcc/config/riscv/riscv.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f1d5129397f..dd6e68a08c2 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts) We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */ if (TARGET_MIN_VLEN_OPTS (opts) > 4096) - sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for " + sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for " "'V' Extension"); /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with big-endian after finishing full coverage testing. */ if (TARGET_VECTOR && TARGET_BIG_ENDIAN) - sorry ("Current RISC-V GCC cannot support RVV in big-endian mode"); + sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); /* Convert -march to a chunks count. */ riscv_vector_chunks = riscv_convert_vector_bits (opts);