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[192.176.117.6]) by smtp.gmail.com with ESMTPSA id p9-20020a056512234900b0050e3615f608sm691367lfu.209.2024.01.18.08.41.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 08:41:04 -0800 (PST) From: Mikael Pettersson To: gcc-patches@gcc.gnu.org Subject: [PATCH] Avoid ICE in single-bit logical RMWs on m68k-uclinux [PR108640] Date: Thu, 18 Jan 2024 17:39:26 +0100 Message-ID: <20240118164052.11548-1-mikpelinux@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788447161354665233 X-GMAIL-MSGID: 1788447161354665233 When generating RMW logical operations on m68k, the backend recognizes single-bit operations and rewrites them as bit instructions on operands adjusted to address the intended byte. When offsetting the addresses the backend keeps the modes as SImode, even though the actual access will be in QImode. The uclinux target defines M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P which adds a check that the adjusted operand is within the bounds of the original object. Since the address has been offset it is not, and the compiler ICEs. The bug is that the modes of the adjusted operands should have been narrowed to QImode, which is that this patch does. Nearby code which narrows to HImode gets that right. Bootstrapped and regression tested on m68k-linux-gnu. Ok for master? (Note: I don't have commit rights.) gcc/ PR target/108640 * config/m68k/m68k.cc (output_andsi3): Use QImode for address adjusted for 1-byte RMW access. (output_iorsi3): Likewise. (output_xorsi3): Likewise. gcc/testsuite/ PR target/108640 * gcc.target/m68k/pr108640.c: New test. --- gcc/config/m68k/m68k.cc | 6 +++--- gcc/testsuite/gcc.target/m68k/pr108640.c | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/m68k/pr108640.c diff --git a/gcc/config/m68k/m68k.cc b/gcc/config/m68k/m68k.cc index e9325686b92..6cd45b53406 100644 --- a/gcc/config/m68k/m68k.cc +++ b/gcc/config/m68k/m68k.cc @@ -5471,7 +5471,7 @@ output_andsi3 (rtx *operands) operands[1] = GEN_INT (logval); else { - operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); + operands[0] = adjust_address (operands[0], QImode, 3 - (logval / 8)); operands[1] = GEN_INT (logval % 8); } return "bclr %1,%0"; @@ -5510,7 +5510,7 @@ output_iorsi3 (rtx *operands) operands[1] = GEN_INT (logval); else { - operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); + operands[0] = adjust_address (operands[0], QImode, 3 - (logval / 8)); operands[1] = GEN_INT (logval % 8); } return "bset %1,%0"; @@ -5548,7 +5548,7 @@ output_xorsi3 (rtx *operands) operands[1] = GEN_INT (logval); else { - operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); + operands[0] = adjust_address (operands[0], QImode, 3 - (logval / 8)); operands[1] = GEN_INT (logval % 8); } return "bchg %1,%0"; diff --git a/gcc/testsuite/gcc.target/m68k/pr108640.c b/gcc/testsuite/gcc.target/m68k/pr108640.c new file mode 100644 index 00000000000..5f3e8b49d42 --- /dev/null +++ b/gcc/testsuite/gcc.target/m68k/pr108640.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { do-options "-O1" } */ + +int x; +void andsi3(void) { x &= ~(1 << 16); } +void iorsi3(void) { x |= (1 << 16); } +void xorsi3(void) { x ^= (1 << 16); }