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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.16 via Frontend Transport; Tue, 16 Jan 2024 11:59:53 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 16 Jan 2024 03:59:40 -0800 Received: from pohsuns-pegasus.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 16 Jan 2024 03:59:38 -0800 From: Pohsun Su To: , , , CC: , , , Pohsun Su Subject: [PATCH 1/2] clocksource/drivers/timer-tegra186: add WDIOC_GETTIMELEFT support Date: Tue, 16 Jan 2024 19:58:37 +0800 Message-ID: <20240116115838.16544-2-pohsuns@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240116115838.16544-1-pohsuns@nvidia.com> References: <20240116115838.16544-1-pohsuns@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|DM6PR12MB4545:EE_ X-MS-Office365-Filtering-Correlation-Id: e1e10531-e990-4da1-310f-08dc168aa699 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2024 11:59:53.4716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1e10531-e990-4da1-310f-08dc168aa699 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4545 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788248303256565543 X-GMAIL-MSGID: 1788248303256565543 This change adds support for WDIOC_GETTIMELEFT so userspace programs can get the number of seconds before system reset by the watchdog timer via ioctl. Signed-off-by: Pohsun Su --- drivers/clocksource/timer-tegra186.c | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index 304537dadf2c..685c6689a2da 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -29,6 +29,7 @@ #define TMRSR 0x004 #define TMRSR_INTR_CLR BIT(30) +#define TMRSR_PCV GENMASK(28, 0) #define TMRCSSR 0x008 #define TMRCSSR_SRC_USEC (0 << 0) @@ -45,6 +46,9 @@ #define WDTCR_TIMER_SOURCE_MASK 0xf #define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) +#define WDTSR 0x004 +#define WDTSR_CURRENT_EXPIRATION_COUNT GENMASK(14, 12) + #define WDTCMDR 0x008 #define WDTCMDR_DISABLE_COUNTER BIT(1) #define WDTCMDR_START_COUNTER BIT(0) @@ -234,12 +238,49 @@ static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, return 0; } +static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + u32 timeleft; + u32 expiration; + + if (!watchdog_active(&wdt->base)) { + /* return zero if the watchdog timer is not activated. */ + return 0; + } + + /* + * System power-on reset occurs on the fifth expiration of the watchdog timer and so + * when the watchdog timer is configured, the actual value programmed into the counter + * is 1/5 of the timeout value. Once the counter reaches 0, expiration count will be + * increased by 1 and the down counter restarts. + * Hence to get the time left before system reset we must combine 2 parts: + * 1. value of the current down counter + * 2. (number of counter expirations remaining) * (timeout/5) + */ + + /* Get the current number of counter expirations. Should be a value between 0 and 4. */ + expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, readl_relaxed(wdt->regs + WDTSR)); + + /* Convert the current counter value to seconds, rounding up to the nearest second. */ + timeleft = FIELD_GET(TMRSR_PCV, readl_relaxed(wdt->tmr->regs + TMRSR)); + timeleft = (timeleft + USEC_PER_SEC / 2) / USEC_PER_SEC; + + /* + * Calculate the time remaining by adding the time for the counter value + * to the time of the counter expirations that remain. + */ + timeleft += wdt->base.timeout * (4 - expiration) / 5; + return timeleft; +} + static const struct watchdog_ops tegra186_wdt_ops = { .owner = THIS_MODULE, .start = tegra186_wdt_start, .stop = tegra186_wdt_stop, .ping = tegra186_wdt_ping, .set_timeout = tegra186_wdt_set_timeout, + .get_timeleft = tegra186_wdt_get_timeleft, }; static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra, From patchwork Tue Jan 16 11:58:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pohsun Su X-Patchwork-Id: 188512 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:42cf:b0:101:a8e8:374 with SMTP id q15csp201416dye; Tue, 16 Jan 2024 04:00:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMlf/EWrxbsfgRes2amHMgpupjr+dTf0EQmXLZOSZDYj9YMUbFX0bWwRxdmBSXs33rPSTo X-Received: by 2002:a05:620a:66b:b0:781:5c66:c71d with SMTP id a11-20020a05620a066b00b007815c66c71dmr8743176qkh.45.1705406450990; Tue, 16 Jan 2024 04:00:50 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705406450; cv=pass; d=google.com; s=arc-20160816; b=WVEx9LYVK3SXFzgA0aV78ASG6v9vYtO1BuQHGu4HvpTrO5osMwZETamNMK91d0yrHo b0eZ/yKL/v6zSAX1y7wAxxZmFmf3kbpFXblsUp8sgfhgkiCUEsX4H1Gz0e1eZKTDUX7Q eCCaMXLZ5Xq9m6lLKjqsuFLU0SDIR/aHZ94dKSQOCMnQY3zzP4BT48ec/1BgQxsLcS1f aiTaI3DX95Y7r6IjHsObxyvoHJ3/bYi/HH8GHIYOD8nvJ/VaDyEAwC04akTLDrf6QXb2 A/gZa1Kth8WuxDni+87jCbZNtrJo8YRU0DpI8ByHohAxlKvCoajACf1SsCI6m1B1Gbpp +vGQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WqAlyeWm5KWLX0BzuSxwsTtHhRJPt37Lq4jARKhl1eA=; fh=s7sY3ttOacxfaxWrUh+8mxXqMZyUZkWTNiekLT7t48k=; b=QeVUeRNGWZ570AQgzE1vTbI7et6xFduZFLYJpFoo6f0jfPr7pa0d5Cbose2nrZPb6i 0aps39d+YO7J8zcxX87oYCuv0wsa0A0xMfwrH4ccGilGp0fbswBa8qhPJUQ7G16XYEPL Wv021/QkdfRXY97Bdfz2wxVVCH8NtVvseTQmKvxoNiKmoHelAOC4ET03s3HzxoaNjiLx Z+ppoZO9nYrwYOF1mvgJeuPFS7ZEWBxuxtU1pkWBFwEa8DNcnk26q5tKfDWcwwjsUD+0 rmolHhy4YvzigCI4Zr/7eT0Mp8BOPctrtAZ+9WiRe+vDehcnHs6PqQ7ZJg8n4kbzgTaH E62A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=diOL8NOo; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel+bounces-27357-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-27357-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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The timer irq handler is triggered due to the 1st expiration, the handler disables and enables watchdog but also implicitly clears the expiration count so the count can only be 0 or 1. Since this watchdog supports opened, configured, or pinged by systemd, We remove this behavior or the watchdog may not bark when systemd crashes since the 5th expiration never comes. Signed-off-by: Pohsun Su --- drivers/clocksource/timer-tegra186.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index 685c6689a2da..963c12c81f4d 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -174,7 +174,8 @@ static void tegra186_wdt_enable(struct tegra186_wdt *wdt) value |= WDTCR_PERIOD(1); /* enable local interrupt for WDT petting */ - value |= WDTCR_LOCAL_INT_ENABLE; + if (0) + value |= WDTCR_LOCAL_INT_ENABLE; /* enable local FIQ and remote interrupt for debug dump */ if (0) @@ -406,18 +407,6 @@ static int tegra186_timer_usec_init(struct tegra186_timer *tegra) return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); } -static irqreturn_t tegra186_timer_irq(int irq, void *data) -{ - struct tegra186_timer *tegra = data; - - if (watchdog_active(&tegra->wdt->base)) { - tegra186_wdt_disable(tegra->wdt); - tegra186_wdt_enable(tegra->wdt); - } - - return IRQ_HANDLED; -} - static int tegra186_timer_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -469,17 +458,8 @@ static int tegra186_timer_probe(struct platform_device *pdev) goto unregister_osc; } - err = devm_request_irq(dev, irq, tegra186_timer_irq, 0, - "tegra186-timer", tegra); - if (err < 0) { - dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err); - goto unregister_usec; - } - return 0; -unregister_usec: - clocksource_unregister(&tegra->usec); unregister_osc: clocksource_unregister(&tegra->osc); unregister_tsc: