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Allow it in bindings. Signed-off-by: Konrad Dybcio --- Changes since v1: - Add minItems Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..82bc696de662 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -159,7 +159,8 @@ properties: through the TCU's programming interface. power-domains: - maxItems: 1 + minItems: 0 + maxItems: 3 nvidia,memory-controller: description: | From patchwork Mon Nov 14 10:42:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19671 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2074813wru; Mon, 14 Nov 2022 02:43:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Je0JiUXfSXoewzF86V4YU2mdSeCw/NesaNqggtHr3ItjVEZNHAFJcOMwkrniNRigqDRHR X-Received: by 2002:aa7:da98:0:b0:463:a83c:d762 with SMTP id q24-20020aa7da98000000b00463a83cd762mr10279606eds.44.1668422604515; Mon, 14 Nov 2022 02:43:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422604; cv=none; d=google.com; s=arc-20160816; b=SyrnHf/hI3RRDOF6eI8ziI6K59YRYJId81/kdvdY+Zmg/yNh/7Y/HVxSlVpJcXMX+0 rbouMEDTt8qea1I/5WVecNuFvjoVmGdTULy/dX8rOYPhniVqjFZifNPjS7v+CbeyD5Cw WiP8J3/kIsYGYiMz8s3hAtvmmmONxGk42NuZ04Ypx0tTFgvXi6RWGXQUen62VMRA6iv5 AKnxumvUwKyJbRg8aygNxylwLn8fJQA6wC1WxE2zCGMr4BDIwbhO5ENNsUwuckIXMLk+ sdVz6aOEZnv5jHy8HoTJ76mEoCBEs1WsC9wOJCsY4CQnFz2qVmvjEyhCDWTcatrsl4l8 cqvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pefehE5o4ZbEpfgRDd+vWut5SWgW8/RYnVz1s2zWHXE=; b=eXLrJZLMFyq6x6DVSGGfkIAOElrCQsrcbg22muBRc+zgK/FAto+2dAPDwSW2799Kw0 YGw/mcftJ/8NPsUKz9XKEjEjtIAzByi+ji95oEJgZrHTvovrsAkepdb3eYCL4rv9e5Dy tVgVFf/qDRPpxZ3ZfOU68oQ68qkH2j0FQxmXqZ0awXXpbi1iUCQLjFNqcgUNvTGtPhdm SmPwo4RPyTFam0PZw2F3CxaZhKCuMTIx/Z5AWKV3zM0dFNllvc6+HSZN+xNhqccbcrk0 USwPHjmh7q4ErwO5BEwmdq1qSLtA8zjX9R7SxTKzzSOWlLjkDfSS7APwTTKtC/xU0Zd9 nrug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uZuLqwtg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- Changes since v1: - take a different approach; patch substituted arch/arm64/boot/dts/qcom/pmk8350.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index a7ec9d11946d..2730d97ab213 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -8,10 +8,15 @@ #include #include +/* (Sadly) this PMIC can be configured to be at different SIDs */ +#ifndef PMK8350_SID + #define PMK8350_SID 0 +#endif + &spmi_bus { - pmk8350: pmic@0 { + pmk8350: pmic@PMK8350_SID { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; + reg = ; #address-cells = <1>; #size-cells = <0>; @@ -21,14 +26,14 @@ pmk8350_pon: pon@1300 { pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; linux,code = ; status = "disabled"; }; pon_resin: resin { compatible = "qcom,pmk8350-resin"; - interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; status = "disabled"; }; }; @@ -38,14 +43,14 @@ pmk8350_vadc: adc@3100 { reg = <0x3100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #io-channel-cells = <1>; }; pmk8350_adc_tm: adc-tm@3400 { compatible = "qcom,adc-tm7"; reg = <0x3400>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -56,7 +61,7 @@ pmk8350_rtc: rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts = ; status = "disabled"; }; From patchwork Mon Nov 14 10:42:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19675 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2075065wru; Mon, 14 Nov 2022 02:44:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf4XS8wMs0jZ4W0u9NFCjn6f8YXo083DcDXPtv8Vgf8IpPUNXcqQZw/53ST98Yedbdcktxgr X-Received: by 2002:a17:906:6a28:b0:7ad:8608:a0a1 with SMTP id qw40-20020a1709066a2800b007ad8608a0a1mr9650973ejc.110.1668422665264; Mon, 14 Nov 2022 02:44:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422665; cv=none; d=google.com; s=arc-20160816; b=MZ2wcCzaboiNvVUEIsSbpGIKopjaWTinmfqOBDYbRIg20Ga4yQLh0pEnajo29VY+JZ YkjLjnFcHXbXIuDC0OT2vBIVRDUCFKj4cHEzWTlqbhNsdN9SbkDAHrKSfc6Mo0jO/NcC pZpC73Xe19cJm9SrLQh7ZLFHkUdBB1Fx7mcZ0ZxPGv3amgeXKTVVHEL4xTYMJD3hBs3Z 5iNsfln6N1H7qsl/YYUUzD3GDPz78lSXLugwXrRHBsUqAQz5zLSvkaVhKt/t6a8+gXe1 JkYXIz0eibpLZkFRK7BI/lNHVhAeb3fIsZ7RArqtlxxDPzfGxLzomRf3Oyw6F05NN2nu OLhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y9OMoKQnRn0IQNyaI5drIYf1dFeHggeskHv0qAn+c0c=; b=LMGrCuhDlQc2bdVDnoZ5g97nMD4dQY7/egHjEj62SCKrf+kEFSriLuJqiKTbR1i9EH FJfmJQDMGadKxSZGEFyPZaj/69ZEF7bUsFPIf5FwLT5joWpcXYosC1xGUMtaQ3x2ZZzu 2Qvd1HaRLsBmVqyd1aowEWxarV6ZaWfJtk9uROyYOa8oKACYh8EXd47c17MknQsU4Ag4 TZF0r9aovoZLBsIy6DFJgz909/mjE9o6626s/3K9U138O2/HhodlwXRgG6xxrDJz4DxK UIeTw2k0eLXZJJGGJdoMZnuyNJX6yhOvQu8WcliGazki3lm84AqH5iQrXZg4dWsaFjxh oIEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gcH1G3kI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- No changes since v1. arch/arm64/boot/dts/qcom/sm6375.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 9b1a497e5ca7..62a64dd731a0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -567,6 +567,46 @@ rpm_msg_ram: sram@45f0000 { reg = <0 0x045f0000 0 0x7000>; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x16 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04c00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xd6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Mon Nov 14 10:42:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19672 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2074826wru; Mon, 14 Nov 2022 02:43:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Lod36+4wOkgnujx8Z725/JCHAst3pQ7wyAWXYHAGiayyX8Iu9Z3JQWb6QX1me99TXuwyd X-Received: by 2002:a17:906:1805:b0:78d:36d7:ed29 with SMTP id v5-20020a170906180500b0078d36d7ed29mr10100870eje.655.1668422611539; Mon, 14 Nov 2022 02:43:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422611; cv=none; d=google.com; s=arc-20160816; b=KhfNdlyaBysTi051NfbkhFxw4ulbpR07/og/uebPMt664nIK12C1omYRNc6O1PMphY FrjcyVf7ib6ctl3C+Mgh85yPGc+M3bgsqDsG7GBFE8/WKWlj6tzzCUziuJIrd91738th s8DA0yqKk+YLlyq5UmmqWQLkzwvnGI7N8WGg2HnRNLc46kFbpO9rr/mD9yqunJ76qYjP KSBpu/RhiDIOwC5Hf6J4srdc87ym4d0b4enHZAa5nUYA/W4lk/TwkGBuwdfjY72te/Ui u7nbk8Spq8F6FZG9O83D1huB9zH45lf9Blu48wk0L1BUQJg8yKJqxQ1BaWvvbnRRKibg gzWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=unS8DAja8HA/dIZlSwbV4MAOjYuJmP970JokwE9EcjQ=; b=U3/vwyKOTzi4kDxpwRie5XctetqdE4cvJfYTjHUIam77Pkyf0uT5/yoBihudYsZoGG F2pnv4/PPuDfjlXchLUkduyrk5Sh+ZT3rmUnojDVOiurSMcGDrlvqi6EUpwamFHrvdCi MyQ+mS8lWWKiR+RF4SlC7AdowLdzloYEyv9gHIQOnhCjctkaxWwwmPNfGOQeFUrgBTFe AMt5lHZ+mBWDYWHwvF7EBWO9djSgPCpFNA+V+oVs8uiuMc69fjGEvfrVTwyiYgbRa5eP a8uTnc1Wl6TgDocIPqnQHbRBYqS1SNp6D1o9PiJg4tk+G7duauJqCjhJWND1DASpmpZX bqsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UNJQwlLN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Changes since v1: - pick up a-b arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 62a64dd731a0..952156891476 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -519,6 +519,49 @@ tlmm: pinctrl@500000 { gpio-controller; #interrupt-cells = <2>; #gpio-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio61", "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio19", "gpio20"; + /* TLMM, GCC and vendor DT all have different indices.. */ + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio4", "gpio5"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { From patchwork Mon Nov 14 10:42:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19673 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2074835wru; Mon, 14 Nov 2022 02:43:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf7SQcEmmFhzv7U1cr/EHV1IqqSs2M5HUVkCPYdokrnsu/5y4juYorjDFNCgffX0FgOsW/Aa X-Received: by 2002:a17:906:fb81:b0:7ae:9187:eb70 with SMTP id lr1-20020a170906fb8100b007ae9187eb70mr9176527ejb.533.1668422612680; Mon, 14 Nov 2022 02:43:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422612; cv=none; d=google.com; s=arc-20160816; b=zAuvQ8JEmaBq0LsaEYDZK5LqheH2T8OcXcyUVZPqUjyfPhdeNoRizt7UlqDOxoe8/Q RolmKNbZybdAYWWHuB4n1NYXXs3cLyJxTq1DULw4E9rzTkbcC5NmZEfr7Fl1GrLzi2lc H4AGbSpr6DFpMK6toP1dXyOkX6a9Z1dpGWjeVfRhSnmnTuJ9ysqrCP2anOBKU17afEvu x8VsnjbMqffHdSFrj4gxrrBfdozj++11b3EhbXbv5234Vbnzkawq6V68I1TrVGPrZA8b hQGVlsC0GWoyd2QAsTgCTCNxUG/mOVYt5AT6KjJf+ByoiKYlZXBOGtM1cU02TYehrqaX KAlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EhVzOmWLQ0AfDjFCb5OflGVxRe6o8eIbACNlgcPHwsE=; b=RflPzRvGkktkUspZCtWmhG67NMLIbCKbB/xrvWdKN037RlDT2iA2dhdCMAO2uOVVi8 u0mJ7OqL/AY3e1b9GtzXMNkhdOJHYI3y3oO+dJBudm5bQbVoIhD7RF19N1J876sW+IIP dJi9KC/BgGOAYL67nt03N7ENVlN6CCtswRlfAnKBxLm0LTQnPuUFAgPpxkdwLKomO5OY GXxV1ic6/znKELYTdo9Hf5deE+whQbj2+31jsVW+w06A/akbOu0ukU/0C+5zBslBwwbr dJF+sArSKjw0W78Q2CSsn5Xns4ROdFv3iG5uQdDw8j8GDPAWD13GAFCYryLZ6zrQMJtA ZgMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bs5yjaBM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio --- No changes since v1. arch/arm64/boot/dts/qcom/sm6375.dtsi | 306 +++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 952156891476..6adffd927a8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -317,6 +318,25 @@ CLUSTER_PD: cpu-cluster0 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -630,6 +650,125 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. + * There is a comment in the included DTSI of another SoC saying that they + * are not "bolled out" (probably meaning not routed to solder balls) + * TLMM driver however, suggests there are as many as 15 QUPs in total! + * Most of which don't even have pin configurations for.. Sad stuff! + */ + }; + gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x04c00000 0 0x60000>; @@ -650,6 +789,173 @@ gpi_dma1: dma-controller@4c00000 { status = "disabled"; }; + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04cc0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c6: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Mon Nov 14 10:42:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19674 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2074906wru; Mon, 14 Nov 2022 02:43:47 -0800 (PST) X-Google-Smtp-Source: AA0mqf5pzR87/TvM3zhAL2kH15aMoHtxsMyGWmlcx0mKxIIX8F4opiidpquD8BoqM2LbC2I/QXCy X-Received: by 2002:aa7:cf08:0:b0:461:a09b:aaf2 with SMTP id a8-20020aa7cf08000000b00461a09baaf2mr10388712edy.328.1668422627444; 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Signed-off-by: Konrad Dybcio --- No changes since v1. .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 450d4a557df1..6a0f4c0bf7ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -65,6 +65,22 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Mon Nov 14 10:42:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19676 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2075086wru; Mon, 14 Nov 2022 02:44:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf4uq1sG08wRYMhzNhfDz87H/Ur8ZJwVJPtJrFD/lYlN7O8e3VIHysSsqhvfRbaMd9Romqbd X-Received: by 2002:a17:90a:a887:b0:216:bda1:cdca with SMTP id h7-20020a17090aa88700b00216bda1cdcamr12976448pjq.201.1668422669476; Mon, 14 Nov 2022 02:44:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422669; cv=none; d=google.com; s=arc-20160816; b=SSTVrJr+uyDvtvVWuxc0fsMvrizODvQDF+1XgM6ZDErKJhMsdDrORF7SQGEAKv4o0/ 6iRwJs7SfsRLuCNaV9foHZIXUVxNUUf8nlZCkQCpHHtmIrJjMlzXMMQh0upq47NjxwcB IkG7TBvFZiezHtOYo6uSrYOeMCH+gNCJa7ASVyqcLEvcyNUMivJEXIcHCGFJj7tZ1Or8 Zwx7jcyqorI0xrAVPgnMRhE35C5AJWqC/0WMhIST+rlu2Njon4i1wRlPZwZTK8gW34z4 YBli2Fbf5jrDaG/+XxxbMhCTtOOyFiTE9Ip/L+zIuIH4M6roC2Sbzoy5WV4B42fl6bw7 yrrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NIxBbSjNtdNlSWQ1P+SfGBLDhzhPep7hpCHZEsAxTUk=; b=NNAjzzJPwBEcEI30u9S1ubw//Snn8l+L7fIwVtKBYuJyqcmKecC/u1NHaTiuFMgXKS HFq2TuncHyij6HlnJimdUvNhY3kJVxLCwo21tyIAimeFv3GDTWiJdKzFPADS6CC+Ts0c cRPswPwfkWVADDCeWwbf3ofM+JNpDXiaNb/OWmmP1UfzCQx3PZBnlg2Ij4F14RTxVK4d L+sqhWRpqcM8qqmoSR4P+5rYcbvzA3RmVMidRXMqvjIch1JPoetqk204LOvz9Qp0ow91 z+0uc4ISUHslloah6jbZkIMAXrwN0PtXtMvXmsUkOEECHNan8XS9jEAVFj8iWBSwkPRy 9P9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cZew1Zo/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- Changes since v1: - configure PMK8350 SID .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 6a0f4c0bf7ad..c830124cb483 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -5,10 +5,18 @@ /dts-v1/; +/* PMK8350 is configured to use SID6 instead of 0 */ +#define PMK8350_SID 6 + #include #include "sm6375.dtsi" +#include "pm6125.dtsi" +#include "pmk8350.dtsi" #include "pmr735a.dtsi" +/* PM6125 PON is used and we can't have duplicate labels */ +/delete-node/ &pmk8350_pon; + / { model = "Sony Xperia 10 IV"; compatible = "sony,pdx225", "qcom,sm6375"; @@ -73,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Mon Nov 14 10:42:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19677 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2075344wru; Mon, 14 Nov 2022 02:45:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf5ROvO0+kQsio+fF/oN9CjiOBZgLo6c4ELKE1JL0gqB258iBzuTpzwnH3Wqr/qrQFX42lpa X-Received: by 2002:a17:906:6592:b0:7ae:9677:d8dd with SMTP id x18-20020a170906659200b007ae9677d8ddmr9765429ejn.71.1668422717305; Mon, 14 Nov 2022 02:45:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422717; cv=none; d=google.com; s=arc-20160816; b=ll6wuceRqGDNHHEDCFeEr1nMQAGf5u5199Mi3CsCbaKmddXwDackeO+N8PAdORirk0 LX4395/Tov5c7FG/zDUBouwTeuy3iYY1vxblg9fEZXDAXDAtBtQJmbPyF9JRoRBxC2ea g4tsmhBRLHWUQNDJRHMVoAop175P18PNnLgGRIhG8vBHmf/T98MvmEUtDMaJFb95bluJ EBsIpaI/j9JGLyjahjqpCXerq/wgXsVBGbIJr57GczJmiRgJn4d8jrXsRP4nRlOPmnoV YV4cUNFR76Nk4n/xD2jrI5ljD/uA/UqgHsGBaAJy2TAcDLnLzLl8usVctyD1C/OBvB+5 ZkAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P8ClIYh0V6nqYf4lc4Knu97ZlNglR4NFcQeCr/Q4wUQ=; b=vyPvGhu9zXOm11PwEiENnJUSGSwp6299drJnr/L0omUc2iV+lzVqYWcjVLW1nv13GZ Er/1uCKWj0+PmJlxMzQwM5KLfrJZk50vHhlL3zybuJ7Kk4KT8l0Dh/AIk0iBIszmFvwz wHHbT3Id0i81WPxSXXHl8qi2JQzjZiTknWdJcsVos2epa4fQ1G8f8MyDMbHOeZqWaf3N YjmxoB6xJaqy1WoX4z/plQNFtCwiFe4a0/55a6Jb4h9akLFS/WoZYhuy4ihZv9t1BsLT nLNNZcbjz5YaZD+k91FXh4/7SRe+mIBMsidLGrEerhmKpGK3URoaqZnxPJxadZ9qLXiw b36Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yb1Qo1yb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- Changes since v1: - sort the node properly (alphabet is hard, I know..) .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index c830124cb483..0f1ddfa28c89 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -106,6 +106,188 @@ &qupv3_id_1 { status = "okay"; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s5: s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + }; + + pm6125_s6: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1374000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + /* + * S8 is VDD_GFX + * L1 is VDD_LPI_CX + */ + + pm6125_l2: l2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + /* L17 is VDD_LPI_MX */ + + pm6125_l18: l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmr735a-regulators"; + + /* + * S1 is VDD_MX + * S2 is VDD_CX + */ + + pmr735a_l1: l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pmr735a_l2: l2 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; + }; + + pmr735a_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pmr735a_l5: l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + pmr735a_l6: l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + pmr735a_l7: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Mon Nov 14 10:42:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 19678 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2075417wru; Mon, 14 Nov 2022 02:45:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf4cd2IvL3lJhR1iXK4QalNQ7AkBuxc8c4ajdej3qdALw8G+XQyffCS1QW7rJ9cKPVeC1fif X-Received: by 2002:a17:906:eb59:b0:7ae:c1b2:d928 with SMTP id mc25-20020a170906eb5900b007aec1b2d928mr9646580ejb.296.1668422731758; Mon, 14 Nov 2022 02:45:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668422731; cv=none; d=google.com; s=arc-20160816; b=QuV8237LnA+xCnl6iukocahiEql8i9zZjKSHHEqzWiS/WIfZWipTlmujsWf65s7VBl DF5P7VS2A10NiUMcto5I27LCmrbPZK2QmL/AC+RpbVg8wzGJlZUoTk0uKZFd9XHkWlvD rgrpYjcLPrrIOxmLahZiT/Za8L70HUBe7pCW1zBzQyY8FiDmDnhDzy1ZwwbWHZ7XLSjP Mw/8ER1fKQRJZTg4E+n1Qr1rJeN903bQ5nCzw3DRtiDU/e3WLwPL8BU0uPuyBpSfUOJW 1ItHtjHSYreCJpVkYo/A5ZXdVJ9BBhNAuuOO8KNydifL1A8JvjNiNravotqxN0psNcOf 3NXw== ARC-Message-Signature: i=1; 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The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio --- No changes since v1. .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 0f1ddfa28c89..d18167bcb41f 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -81,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + vdd-supply = <&pm6125_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_avdd_default>; + }; +}; + &pmk8350_adc_tm { status = "okay"; }; @@ -290,6 +307,20 @@ pmr735a_l7: l7 { &tlmm { gpio-reserved-ranges = <13 4>; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_avdd_default: ts-avdd-default-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <8>; + output-high; + }; }; &usb_1 {