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KG Automatenbau Herrieden" (https://sielaff.de). Signed-off-by: Frieder Schrempf Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 309b94c328c84..8825a9f60ac5a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1233,6 +1233,8 @@ patternProperties: description: Si-En Technology Ltd. "^si-linux,.*": description: Silicon Linux Corporation + "^sielaff,.*": + description: Sielaff GmbH & Co. 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[2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id o26-20020a05620a229a00b007833cd0673dsi9208748qkh.630.2024.01.16.02.54.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 02:54:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-27277-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=cGWnULrm; spf=pass (google.com: domain of linux-kernel+bounces-27277-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-27277-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 847A71C23196 for ; Tue, 16 Jan 2024 10:54:13 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1AE8C19BA8; Tue, 16 Jan 2024 10:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="cGWnULrm" Received: from mail.fris.de (unknown [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81E671946E; Tue, 16 Jan 2024 10:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 273F4C0393; Tue, 16 Jan 2024 11:53:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1705402426; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=KGsp2ET18R7VVq0Ua70B7k4zn/i7OqgsUzQBbBtgh2A=; b=cGWnULrmy/jcmgGRtsLEqmY8NxUQfdEgDEeNzyqWMHme28CNc+aObZCRDuF1XbRVDlVTx4 1u0tbtjlZ6+8R+LZioRk2Z42D5GEsQLCCXUj35tBOkWhRWdOu2Uune8OlKmm1Mbng87eRv ypAja2lPavc3OYWV0THCib83USfe4lM7y3dq26AbdN/bSZP5aA9GC4lmrN0itvOf+ZT/80 agNkcTyib94h5q1xv+MYh7Sb1eq/XXgoQyMOp+cNxP0C8DAS3U5tvmO/K12r6PY3HXkMan NlGg9DCVSNOcBQtlfX9dW9cti+hAcsEwdJ5PVeCj8VqfsZ1QXup51ex8QP6hAw== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Li Yang , Rob Herring , Shawn Guo Cc: Frieder Schrempf , Bjorn Helgaas , Christoph Niedermaier , Conor Dooley , Gregor Herburger , Josua Mayer , Krzysztof Kozlowski , Marcel Ziswiler , Marco Felsch , Marek Vasut , Markus Niebel , Stefan Wahren , Tim Harvey , Yannic Moog Subject: [PATCH 2/3] dt-bindings: arm: fsl: Add Sielaff i.MX6 Solo board Date: Tue, 16 Jan 2024 11:51:56 +0100 Message-ID: <20240116105317.267525-3-frieder@fris.de> In-Reply-To: <20240116105317.267525-1-frieder@fris.de> References: <20240116105317.267525-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788244083485302797 X-GMAIL-MSGID: 1788244083485302797 From: Frieder Schrempf Add compatible for the Sielaff i.MX6 Solo board. Signed-off-by: Frieder Schrempf Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 32b195852a75c..f6cdf4a8e51a2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -469,6 +469,7 @@ properties: - prt,prtvt7 # Protonic VT7 board - rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board - riot,imx6s-riotboard # RIoTboard i.MX6S + - sielaff,imx6dl-board # Sielaff i.MX6 Solo Board - skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2 - skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6 - solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite From patchwork Tue Jan 16 10:51:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 188488 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:42cf:b0:101:a8e8:374 with SMTP id q15csp172545dye; Tue, 16 Jan 2024 02:54:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IGWa9BCNIdvFfQH6jd76dYe9/iYqFHWf8Jir3o8TH6qsXqJin6RYleNFbP89fJk7Jt0L4iS X-Received: by 2002:a17:906:a03:b0:a2e:71fa:554d with SMTP id w3-20020a1709060a0300b00a2e71fa554dmr408595ejf.102.1705402483445; Tue, 16 Jan 2024 02:54:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705402483; cv=none; d=google.com; s=arc-20160816; b=G2cIFYMkc5qEj5UyJ35PC+GLx5xBg7n3szDDECmQy1W0gPzErcfIkRsvAZhIciYE1+ Xfp8wj/KIKbUUSABG4ZU0/DSSroR/qg4aK6qmaSiI2PQAlTdQetrVTCvpeWNhqpEcyxF 99djffkIFqbCuL3b7H8TycCsqvfNEuzpZkPodDMlYSa6LuF2eWm/8xh7BkgyJxC/o5Ut lIVDHmr/Qby+TJnVr9xJjfrCoj4GLwJ/c1Iv6A0GkTHZ76hGctutBiQWtrYVbZetMPgu a6tYRYmn6FVPVG1Z6Bv+m/zOCdZ3l0Zht2203d/KtNyX0g21PKlIwRl7ESmWo8UOtkGE 1WOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hyBPsf8SOH7XtOMXQJ6clHFg2/D5B/kPD6ppS0YwXdQ=; fh=6aS5pMBMnjUgI0/pCMwomvRDs08+nwe7YQjjB4qhemk=; b=0Qy3cAV1L+E5S5FSD9MdKHb/NwLphMN4DubKCRPjJxmQojw4+MX08rIGIZP2o5oEaR bNUEMnPKB9R03nBZiIOh6SMI5PLDUkGk7XilxR+AhHZOlMgO5VwPWahMKKZPFQK+gMEw SiA+y50o0mAmrjaEc3o2Cb/g3bVIISo8s+irbRn9tNhlpsQW/AQEM1wXu3HGiTXTUtRq 8LnGheKHny1Z70clNhXaZcTp9IYqpL0FhAgGDGQSUY9SPg0FIzT0Uzpnf/VYj9jers6M 0XEYDM5b61zUk6Dm8g2y/tkeBhNvYHOsT9o+2WIYeGhg5Sl43dRFtOEoy42UY1qM244b YkFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=oacMjNZf; spf=pass (google.com: domain of linux-kernel+bounces-27278-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-27278-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id d17-20020a170906c21100b00a2b0afda56fsi4596681ejz.1044.2024.01.16.02.54.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 02:54:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-27278-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=oacMjNZf; spf=pass (google.com: domain of linux-kernel+bounces-27278-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-27278-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id E0E361F23189 for ; Tue, 16 Jan 2024 10:54:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BA74F19BAA; Tue, 16 Jan 2024 10:54:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="oacMjNZf" Received: from mail.fris.de (unknown [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AED319440; Tue, 16 Jan 2024 10:54:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B2A6FC02D5; Tue, 16 Jan 2024 11:54:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1705402447; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=hyBPsf8SOH7XtOMXQJ6clHFg2/D5B/kPD6ppS0YwXdQ=; b=oacMjNZf5VsNUgFyTAf6DnGpOkklJYw9qTDS3G+AO2LYLhvGXA/uapmKs+jWJWO/1JCT7I GnhWtt8pHMP7cThLzPVacazq+lQZcu4xB43VfUHzAm3+UpNa5Yxl+R/br2ZfzKag7lb9xA 0X5YjlKnf8Kl11wrVp5J+FdSzoLkgFjhgT+vvlj1LpwfCwqtzU8NJp03m7KQHkoDK3S000 KFG7r507vTKln5FtAvgoG4TPUP8HBGuRebeW1d5s3g3HvYiWNyX8Hd3lmBxA2iLjvo7UC9 i7DjemigMzV7nHyVR+7gPqoFI9t7D0aCn/f/Gjyklno7RkkFsRRr4mqhPQqOwQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Andre Przywara , Dmitry Baryshkov , Fabio Estevam , Gregory CLEMENT , James Hilliard , Kunihiko Hayashi , NXP Linux Team , Pengutronix Kernel Team , Rob Herring Subject: [PATCH 3/3] ARM: dts: imx6dl: Add support for Sielaff i.MX6 Solo board Date: Tue, 16 Jan 2024 11:51:57 +0100 Message-ID: <20240116105317.267525-4-frieder@fris.de> In-Reply-To: <20240116105317.267525-1-frieder@fris.de> References: <20240116105317.267525-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788244114617665357 X-GMAIL-MSGID: 1788244114617665357 From: Frieder Schrempf The Sielaff i.MX6 Solo board is used as controller and user interface in vending machines. It is based on the i.MX6 Solo SoC and features the following peripherals and interfaces: * 512 MB DDR3 RAM * 512 MB NAND Flash * 1 MB NOR Flash * SD card * Debug LED * Debug UART * Key Inputs * RTC * RS232 * 100 MBit Ethernet * USB Hub * USB OTG * HDMI * 7" LVDS IPS panel * PWM Backlight * Optional Extension Board with USB Ethernet NIC Signed-off-by: Frieder Schrempf --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts | 533 +++++++++++++++++++ 2 files changed, 534 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index a724d1a7a9a07..c32e004e7610c 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -118,6 +118,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ imx6dl-savageboard.dtb \ + imx6dl-sielaff.dtb \ imx6dl-skov-revc-lt2.dtb \ imx6dl-skov-revc-lt6.dtb \ imx6dl-solidsense.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts new file mode 100644 index 0000000000000..9340fbcdd0265 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include +#include +#include + +/ { + model = "Sielaff i.MX6 Solo"; + compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm3 0 50000 0>; + brightness-levels = <0 0 64 88 112 136 184 232 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + power-supply = <®_backlight>; + }; + + cec { + compatible = "cec-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + hdmi-phandle = <&hdmi>; + }; + + enet_ref: clock-enet-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet-ref"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-0 { + gpios = <&gpio2 16 0>; + debounce-interval = <10>; + linux,code = <1>; + }; + + key-1 { + gpios = <&gpio3 27 0>; + debounce-interval = <10>; + linux,code = <2>; + }; + + key-2 { + gpios = <&gpio5 4 0>; + debounce-interval = <10>; + linux,code = <3>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-debug { + label = "debug-led"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; + + osc_eth_phy: clock-osc-eth-phy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc-eth-phy"; + }; + + panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_backlight>; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + regulator-name = "backlight"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + /* + * Set PTP clock to external instead of internal reference, as the + * REF_CLK from the PHY is fed back into the i.MX6 and the GPR + * register needs to be set accordingly (see mach-imx6q.c). + */ + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&enet_ref>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + clocks = <&osc_eth_phy>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + reset-assert-us = <500>; + reset-deassert-us = <100>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "key-out", "key-in", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "lan9500a-rst", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c4>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + st1633@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio5>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + gt911@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + usb1@1 { + compatible = "usb4b4,6570"; + reg = <1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <12000000 0>; + }; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "host"; + over-current-active-low; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_backlight: regbacklightgrp { + fsl,pins = < + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +};