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[147.75.80.249]) by mx.google.com with ESMTPS id ot26-20020a170906ccda00b00a2accc5f96esi3674971ejb.581.2024.01.15.04.58.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 04:58:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-25983-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wtUjWDCL; spf=pass (google.com: domain of linux-kernel+bounces-25983-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25983-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 72C941F21F38 for ; Mon, 15 Jan 2024 12:58:51 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4824E1758B; Mon, 15 Jan 2024 12:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wtUjWDCL" Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4461117555; Mon, 15 Jan 2024 12:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvJZb110754; Mon, 15 Jan 2024 06:57:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705323439; bh=nVIik13VEQb/k+Y/rs8n0/H7l0pIsFj55OzrRKWZwcU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wtUjWDCLxK+FclaPXHB4PPXzzGbZD0gR0OqEYRi2Xrocsl+M7TNvfa7K3kstFKuBb QVH9YEK2FcGlWOSe8V4bCZBnxHRRucnDdz5k1jy3KhwVOfy+HeMZ6/l0w5eqpfzjWr kml8Q+i2hvxSZE7tSRdO/mr0G2qM7knaR6KEspPY= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40FCvJB0019839 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jan 2024 06:57:19 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jan 2024 06:57:18 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jan 2024 06:57:18 -0600 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvIIQ128467; Mon, 15 Jan 2024 06:57:18 -0600 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Date: Mon, 15 Jan 2024 18:27:15 +0530 Message-ID: <20240115125716.560363-2-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115125716.560363-1-devarsht@ti.com> References: <20240115125716.560363-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788161328135421196 X-GMAIL-MSGID: 1788161328135421196 TI keystone display subsystem present in AM65 and other SoCs such as AM62 support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1]. The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region. This adds binding for "common1" register region too as supported by the hardware. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) Signed-off-by: Devarsh Thakkar Acked-by: Conor Dooley --- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index b6767ef0d24d..55e3e490d0e6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items: @@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items: @@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>, From patchwork Mon Jan 15 12:57:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devarsh Thakkar X-Patchwork-Id: 188134 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp1682628dyc; Mon, 15 Jan 2024 04:58:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbHB1p1fKSh1icz2TL5sHqzvedxWxQgVa1GjInSTRwOFAibx+Ivm+GEw/epLJGtJwD+unc X-Received: by 2002:a05:6a21:3391:b0:19a:5b89:9d63 with SMTP id yy17-20020a056a21339100b0019a5b899d63mr5565895pzb.12.1705323499847; Mon, 15 Jan 2024 04:58:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705323499; cv=none; d=google.com; s=arc-20160816; b=dnlj6W3ZJ7EV4qAryv86Ay4VvssmM4MldvzNntln+jNHPOaJc2C66Rn6WvIt8yqpqP 5/7BqCm4Ffg1WxvRRf8668JoA7kvo4NidQvP8ByOqwMdr1gz8Qg5Yoqs6d09YmhIyz0m Ftw20Id+trKfRHnM/QiP1tM5IYmXcizirz9AycYDdriKD+4c5h4Jg1fUEbZeNjf7UxLJ OBYrLh2FXKafdZs2DJsFgoq+vatIS4hI9DbEV5/Mj+a/CO8FWD4OWl5ny0WYTTseoF0G /5VJfDYrNhsDMq2w6tkBl4bJ/ItwUpqhyd4vgJqe6phte85cg4yNOzMuaHsnPwj0T77N lP3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3Osuk5K0i7HWxwinhFXlIBGatS8OzdMtUhxrEy62/3M=; fh=EXWdQIUZd8ztTXuq9rgJTiik/YpFs+RnkZnK7SZSjB4=; b=POdxayyuHz8vDj6ItjnuIvGGB4/gH4yyiokEXFyohgQix1wrnAXwHGZVJ+Y5N96u49 1M/XVNoLNW1lTku8PChaLinDNqb5bYttoPcHLS5gTAqHZJ0yeV3PeMqRvi+PmLQI6gcI vC/la2hNF26slRPpqcU3pO7ZmJ4SDeDYJU/76IZaAzaFc/UoGU2SZf0MzF/reyQA+UPc cLrraLPoGEpaUKNf+SwMbIKxOZ/dDleJqZ2eo86bHzNDUTFZG4el2vAbA5VAu68tJynM q1KY09hwP0/ToO6nShcKYCaSXnGZXv1/NJS8Oe56L+uMwto2sKKoLLDcEQJYmHmcQa/0 gQhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rq8SDkeN; spf=pass (google.com: domain of linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [147.75.48.161]) by mx.google.com with ESMTPS id h22-20020a635316000000b005cda5e4a862si8943572pgb.258.2024.01.15.04.58.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 04:58:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rq8SDkeN; spf=pass (google.com: domain of linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id CF7CBB2139C for ; Mon, 15 Jan 2024 12:58:18 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 253221754E; Mon, 15 Jan 2024 12:57:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rq8SDkeN" Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAEAB171D8; Mon, 15 Jan 2024 12:57:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvLMd112244; Mon, 15 Jan 2024 06:57:21 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705323441; bh=3Osuk5K0i7HWxwinhFXlIBGatS8OzdMtUhxrEy62/3M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rq8SDkeNaTsb/gYCbLlLCaoNrxadGaZlmeBI6rPjWF4+Te+xCGyA/FdmYfoLHvao1 tvlfVug4KLtDvn4Bo7M2I8dKj8ORoKR51vbYa0fCeeoaqtlxTlMJ2T1+Umk+qO+ihV 7aLagIQMPsxfXbqfsbmMcIQc4rd1q6kSwI7FoP4s= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40FCvLYI123671 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jan 2024 06:57:21 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jan 2024 06:57:20 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jan 2024 06:57:20 -0600 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvJpS128487; Mon, 15 Jan 2024 06:57:20 -0600 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , Subject: [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs Date: Mon, 15 Jan 2024 18:27:16 +0530 Message-ID: <20240115125716.560363-3-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115125716.560363-1-devarsht@ti.com> References: <20240115125716.560363-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788161294104388626 X-GMAIL-MSGID: 1788161294104388626 This adds common1 register space for AM62x and AM65x SoC's which are using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. This region is documented in respective Technical Reference Manuals [1]. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) Signed-off-by: Devarsh Thakkar --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 464b7565d085..298bf8d5de8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -779,9 +779,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index fcea54465636..5b2d4365b911 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;