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([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n2-20020aca2402000000b00354948e04e4sm3432939oic.2.2022.11.14.01.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 01:06:06 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v6 1/3] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Date: Mon, 14 Nov 2022 14:35:34 +0530 Message-Id: <20221114090536.1662624-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221114090536.1662624-1-apatel@ventanamicro.com> References: <20221114090536.1662624-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749464037133646501?= X-GMAIL-MSGID: =?utf-8?q?1749464037133646501?= Currently, the memremap() called with MEMREMAP_WB maps memory using the generic ioremap() function which breaks on system with Svpbmt because memory mapped using _PAGE_IOREMAP page attributes is treated as strongly-ordered non-cacheable IO memory. To address this, we implement RISC-V specific arch_memremap_wb() which maps memory using _PAGE_KERNEL page attributes resulting in write-back cacheable mapping on systems with Svpbmt. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/include/asm/io.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 92080a227937..42497d487a17 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #include +#ifdef CONFIG_MMU +#define arch_memremap_wb(addr, size) \ + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL)) +#endif + #endif /* _ASM_RISCV_IO_H */ From patchwork Mon Nov 14 09:05:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 19621 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2048111wru; Mon, 14 Nov 2022 01:19:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf5DnPC4oF5zzYZHvluEwr1Y4xyUEte9C8kV7BSDOKtX9slPekTAAd4SRaDu8a8E4qAkY0jS X-Received: by 2002:a17:902:a38d:b0:186:f256:91d1 with SMTP id x13-20020a170902a38d00b00186f25691d1mr12962996pla.151.1668417591735; Mon, 14 Nov 2022 01:19:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668417591; cv=none; d=google.com; s=arc-20160816; b=oNEz+560Ef6go3NUx+xEb5KLrj8qWJM8pc0Uy9K8aTgzUpirVuNXAAGWR3+/yr8Tjl 3sH4LYwOCRyXnojaHgrR1WZITuHCfPZhldN1YbupWMdvKHB4R87J7YdkyrCmyN7xCTKo fC0sfzNRvbTo7mtuQEFx8k47mC/sfznCUdaH4c4d8+wqYxNkb39cYN3iIQVRO1GKbCSQ UP0ehT2gjgjifnIfpN05CjA4uKnZQnsxpR0gEczORNZlofXdpk0z7utG7W9IZmrRS6fU uUWvWF7Iw4CwoJJHaCKJJirKNUuMkBdlwlOTYQjTFdiKaU9lDKrZQiMDSLUa3358ebom 6rqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qoWw75G040ie7NtRU1t+qmFKMYccQlQoZxH65ktuUwc=; b=iz3trn5iMAJWjeqMCKcgMFfQCp2/mXWW+BRQVLNvNgNFjDHw3a4PzNwwquinIdg/l7 kX23rkISQNQYWYy4Nz1YdVxLyYtnK51MyhmZkiEJYinjn7zkwkiVQgV4QivJUEAqBgvD TsPJKEsTS/r1iHzubcKvrtazKIWl3FK5D1Q+3d8fv1W9TRTQnA7zLlcEwm/QM5PVUTSD C7ya3cdeLl05JKr7jniBP2JxnYzwBWag1/naUWQDx58NIS2MBF6QLoln6aGfktovbT+X +c4AI1MrweDTH64dxv3DftWO2kdtF3BQ9L2toqGxkmTvtOm8a8GrUHwc1lUSibHjJ4G2 Fqzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=iw9Zn5wy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n2-20020aca2402000000b00354948e04e4sm3432939oic.2.2022.11.14.01.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 01:06:11 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v6 2/3] RISC-V: Implement arch specific PMEM APIs Date: Mon, 14 Nov 2022 14:35:35 +0530 Message-Id: <20221114090536.1662624-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221114090536.1662624-1-apatel@ventanamicro.com> References: <20221114090536.1662624-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749462644614557181?= X-GMAIL-MSGID: =?utf-8?q?1749462644614557181?= The NVDIMM PMEM driver expects arch specific APIs for cache maintenance and if arch does not provide these APIs then NVDIMM PMEM driver will always use MEMREMAP_WT to map persistent memory which in-turn maps as UC memory type defined by the RISC-V Svpbmt specification. Now that the Svpbmt and Zicbom support is available in RISC-V kernel, we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM PMEM driver can use MEMREMAP_WB to map persistent memory. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/pmem.c | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/mm/pmem.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa78595a6089..c0e22648bd16 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,6 +25,7 @@ config RISCV select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV select ARCH_HAS_MMIOWB + select ARCH_HAS_PMEM_API select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index d76aabf4b94d..b4f35da889bf 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -13,6 +13,7 @@ obj-y += extable.o obj-$(CONFIG_MMU) += fault.o pageattr.o obj-y += cacheflush.o obj-y += context.o +obj-y += pmem.o ifeq ($(CONFIG_MMU),y) obj-$(CONFIG_SMP) += tlbflush.o diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c new file mode 100644 index 000000000000..089df92ae876 --- /dev/null +++ b/arch/riscv/mm/pmem.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include + +#include + +void arch_wb_cache_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); + +void arch_invalidate_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_invalidate_pmem); From patchwork Mon Nov 14 09:05:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 19622 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2048630wru; Mon, 14 Nov 2022 01:21:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf5e9XE8u3u3d98zABQYz+GixxVvsm3QoL8QLMahJMZkzuoFVi3tH21Td+jmQght5meiJZEa X-Received: by 2002:a63:1348:0:b0:456:f713:c3d1 with SMTP id 8-20020a631348000000b00456f713c3d1mr11006294pgt.303.1668417694474; Mon, 14 Nov 2022 01:21:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668417694; cv=none; d=google.com; s=arc-20160816; b=MsI20Sfo1OR88ffhdkoCbQiFHxSh+E87nPVkISr9MpUTAo7xJFuSYu+QYB9x0/D0Iw jbM81XZTYtuycZ0L1xw/lOgdZoVZyNkaGiWW14khERFGTb3Li79dvOJhNGi9cI0m8464 POVddZfcc6glxWedZ6IJgxOFPnI5s3WCYRJbFgCDxT+G+ASNCEMV43gLNRvhdZflYWTj m1aOngIr9TXXEnv92rHm+LwazHzPyj9f6ElD8AFL+Ksj2IFE1lLmrWvPemx76JOc1UOH jAHxfvSGJKt7K9xIUNfsnY6JG1DAE1lBEl8PTn319cayQhjv9q+7Ajby8RwBr273gUEl EWtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5TnLW0RVC/l/l6ZpSJGiQ9RS55Sh7Bww2u/zF6eZ2bY=; b=FusP3n7So0wYo23mm/qJwm8JJh1UlckBxi58sxf5+0PVVn4loYaOy62gZZ/kvY9axE UeILFO8ZUaeIxB65Gzj7RdmSwVENP8FNf08Z5lQNyBe4YGhWOTYlmTIBS+JiOcKN4UGy q/KjRpTKO7/+uNY/eHm5CUotEFjnG0l+9J0+b5hHa5sC06eOHfO0CPUDBBPIZ1a2Cxfn yhFErcHLTsnAH42BeTJjplvKDkcTXT5X1jQDZnlwzZNU0nuaMngCMpM7WvCm/5WOLyto cqJOA+7ia0SW7gxSCAZdxVc3SOebAXzj8qR5BiD8s7FMYxwfQTekdX3HD6kDGE3ckVw4 LW7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NcRntpJU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n2-20020aca2402000000b00354948e04e4sm3432939oic.2.2022.11.14.01.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 01:06:15 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 3/3] RISC-V: Enable PMEM drivers Date: Mon, 14 Nov 2022 14:35:36 +0530 Message-Id: <20221114090536.1662624-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221114090536.1662624-1-apatel@ventanamicro.com> References: <20221114090536.1662624-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749462752253378134?= X-GMAIL-MSGID: =?utf-8?q?1749462752253378134?= We now have PMEM arch support available in RISC-V kernel so let us enable relevant drivers in defconfig. Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..462da9f7410d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_VIRTIO=y +CONFIG_LIBNVDIMM=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y