From patchwork Mon Jan 15 06:57:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 188037 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp1538587dyc; Sun, 14 Jan 2024 22:58:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IHNqMmnbyFOPl4Xmy/m1h6GhGrbh7nCxub0Und9D9xGvdiTZrl7K9lN2c0PWt44ZldE8I89 X-Received: by 2002:a05:620a:1a88:b0:783:5797:a7d1 with SMTP id bl8-20020a05620a1a8800b007835797a7d1mr3014854qkb.41.1705301917461; Sun, 14 Jan 2024 22:58:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705301917; cv=pass; d=google.com; s=arc-20160816; b=HOYYJfYPrZNvZJzoCeyj0zjMXqprgiQtmbC1aSc0vYQ/Hta+MhL+NE0rrJyV102i/I 3exnVdLQLgG27hRo4DmGx2mLy+LDJ2KQunB0qgXDUhpIXLujzvjFzIPlHF80rUFcZ5tk P1mF1OpOxyTODSfbKEAuJWqXbp/94iK99hHaoDLrFH1Yi0aO4TZ4E+HWDSSBlN4PG7Ac BKkryZ2GXKZNbKYGCwQaro7rIgBw90e3NvQ8lO1RmPe7ThF4ThEucOAeuNocGq+xCVrh ySusD3xpcewX7MUL0r/qYpWaYJEeG2lzCW8LaopGbe+TQzf81Ia3py1EeKc133MxNztx B9Ew== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:arc-filter:dmarc-filter:delivered-to; bh=23CxmQNiMz6pmMWUMu+rXNfeGYjdilYTAhw2kWHIV94=; fh=idvV5TQ1gmHAoU8u1GUGfjilVySOK+BR5TeZLoSouN8=; b=UIajRIrXcaOKv0Kor+99JfDUWTy/EElBA/DA3ah3exChKo80u/84myUlcvLL4pTmcY tcCffhSrEi52hvZj50NesJxPoTkRHim3MaqhKhe0kbiWWdG8erZMQu+OfplQOQgSDxQS 5luWbgXcw6Yn5cfVYXoDYs+8ezJSJ91F3HnoWGd7DSakbza0y/4AhB2ImzKdmZoB5mQw RZldf9tpaluuHkyX/FjPvkVHtW06htM9g+PYW+kcYhTIyOVP7q3yyN4HjOLrtAKQUJYQ 1tom42h3vyIMbifivn+7vhkOgjO1n8uKvXHCji5ZS/H+xZ9w8UyY5V4f/uLGzcqZx/Mt quOw== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o13-20020a05620a0d4d00b0078138f20c65si7205879qkl.534.2024.01.14.22.58.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jan 2024 22:58:37 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2C8C03858C3A for ; Mon, 15 Jan 2024 06:58:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 669513858D1E for ; Mon, 15 Jan 2024 06:57:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 669513858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 669513858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.59.177.22 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705301875; cv=none; b=FcoRMcA1og5Vj87x3vEh4KtIV7BPOJpxt33wshtKKmPdip8xcMiojqTkRDoKOt9vAe1Dt9DQtLWBIFvZuRRHGVbWRZNSUrQ5Onpv7Q+VYKOxeQgVes1qm/1aIFyjybFCOjC1qDEgfS1zXRAy2Fe4rchgmNcq9CfhfOybKYN1CP4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705301875; c=relaxed/simple; bh=lmRJOeWV3II+nf8KQDligZmicg/ZFboXx08xoCaKlZk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=SviczCQdTvKMbU8P4OswABw9bPaskPcfDOphyaNn2MZp02cWkgyzyJhZ2pibf3I1KG/OX4eSuP8txHSZlg4HNiXpr1PHG2AQ9llUxfbbLaSCdOdltfLmEOlccl55G6EPlbMRBFJVXODqZQq6vhkxx8qoXlH1GxP5pIUEq+VRu9Y= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp86t1705301860txhjjdo2 X-QQ-Originating-IP: kWsQpJMmOrUHFE3TZy7Y+pmNOQEiasusMHEXE4ffrfQ= Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 15 Jan 2024 14:57:39 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBfnQIUIHWF8VH/FtEzm0nZ6tJHGRJNdvqTViGQrxXAVCgZiVCOpdN 9VFMvi7EPy55hqOIg40t6/7RnRNns+tML00QGm3wLQ9BiUq3bZ5So2D72HeOTXPpT/O2kZq c5xvdeEOIaT0K4oNoGJRNqNUAEhtchujdUSDjRd1W8lFn7xGzcDasOSLYL0s7BV+zgxGuOw C3Ar6BHjvz6gtce2VyteNOY8D87Vb5FyiYHKjIpjRk8fOo+i/zBRh6I72PkxbM7GF+PF05p T/n8RKtU0papBjjwvkwg5LisEqisDVojG+lHpkodY2s/2ju8kRkTetm3ECV2JetcmUGeCT3 SI4JsDO99Q9SB1FOUJuIpK+Zfotwzf8l9l/nvprTxYbVmrvLNrPlxYdeXBX8B4mA/lIE/lW y2CZqRcaVQQOj98maKuUR5iDO7BbOGSS X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5780228604058136314 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Fix attributes bug configuration of ternary instructions Date: Mon, 15 Jan 2024 14:57:38 +0800 Message-Id: <20240115065738.869086-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788138663218656808 X-GMAIL-MSGID: 1788138663218656808 This patch fixes the following FAILs: Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax FAIL: gcc.c-torture/execute/pr68532.c -O0 execution test FAIL: gcc.c-torture/execute/pr68532.c -O1 execution test FAIL: gcc.c-torture/execute/pr68532.c -O2 execution test FAIL: gcc.c-torture/execute/pr68532.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test FAIL: gcc.c-torture/execute/pr68532.c -O3 -g execution test FAIL: gcc.c-torture/execute/pr68532.c -Os execution test FAIL: gcc.c-torture/execute/pr68532.c -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax FAIL: gcc.dg/vect/pr60196-1.c execution test FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax FAIL: gcc.dg/vect/pr60196-1.c execution test FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test Running target riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax FAIL: gcc.dg/vect/pr60196-1.c execution test FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test The root cause is attributes of ternary intructions are incorrect which cause AVL prop PASS and VSETVL PASS behave incorrectly. Tested no regression and committed. PR target/113393 gcc/ChangeLog: * config/riscv/vector.md: Fix ternary attributes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr113393-1.c: New test. * gcc.target/riscv/rvv/autovec/pr113393-2.c: New test. * gcc.target/riscv/rvv/autovec/pr113393-3.c: New test. --- gcc/config/riscv/vector.md | 42 +++++++++---------- .../gcc.target/riscv/rvv/autovec/pr113393-1.c | 24 +++++++++++ .../gcc.target/riscv/rvv/autovec/pr113393-2.c | 29 +++++++++++++ .../gcc.target/riscv/rvv/autovec/pr113393-3.c | 5 +++ 4 files changed, 79 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index c1a282a27b3..ee4ee059a50 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -715,7 +715,7 @@ (const_int 1) (eq_attr "type" "vimuladd,vfmuladd") - (const_int 5)] + (const_int 2)] (const_int INVALID_ATTRIBUTE))) ;; The index of operand[] represents the machine mode of the instruction. @@ -5308,7 +5308,7 @@ vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "2") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5339,7 +5339,7 @@ vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5392,7 +5392,7 @@ vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "3") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5424,7 +5424,7 @@ vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5492,7 +5492,7 @@ vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "3") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5525,7 +5525,7 @@ vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5606,7 +5606,7 @@ vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "2") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5637,7 +5637,7 @@ vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5690,7 +5690,7 @@ vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "3") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5722,7 +5722,7 @@ vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5790,7 +5790,7 @@ vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "3") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -5823,7 +5823,7 @@ vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6516,7 +6516,7 @@ vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "2") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6551,7 +6551,7 @@ vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6610,7 +6610,7 @@ vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "3") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6646,7 +6646,7 @@ vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6740,7 +6740,7 @@ vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "2") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6776,7 +6776,7 @@ vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6837,7 +6837,7 @@ vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "4") + (set_attr "merge_op_idx" "3") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) @@ -6874,7 +6874,7 @@ vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") - (set_attr "merge_op_idx" "2") + (set_attr "merge_op_idx" "4") (set_attr "vl_op_idx" "5") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c new file mode 100644 index 00000000000..57c5cff637b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-require-effective-target riscv_v } */ + +#define SIZE 128 +unsigned short _Alignas (16) in[SIZE]; + +__attribute__ ((noinline)) int +test (unsigned short sum, unsigned short *in, int x) +{ + for (int j = 0; j < SIZE; j += 8) + sum += in[j] * x; + return sum; +} + +int +main () +{ + for (int i = 0; i < SIZE; i++) + in[i] = i; + if (test (0, in, 1) != 960) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c new file mode 100644 index 00000000000..c36a16d91ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */ +/* { dg-require-effective-target riscv_v } */ + +__attribute__((noinline, noclone)) static int +bar (const short *a, int len) +{ + int x; + int x1 = 0; + + for (x = 0; x < len; x++) + x1 += x * a[x]; + return x1; +} + +__attribute__((noinline, noclone)) void +foo (void) +{ + short stuff[9] = {1, 1, 1, 1, 1, 1, 1, 1, 1 }; + if (bar (stuff, 9) != 36) + __builtin_abort (); +} + +int +main () +{ + foo (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c new file mode 100644 index 00000000000..063cf854329 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-require-effective-target riscv_v } */ + +#include "pr113393-2.c"