From patchwork Fri Jan 12 23:56:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 187843 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp508370dyc; Fri, 12 Jan 2024 15:57:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IE4aLYnJNqNm/GoORxEf905sHTT4FExADwBK106+WI8bmP/dEN16vQhGH4V7U3TqxA17kmO X-Received: by 2002:a17:907:918f:b0:a1e:3a14:e84b with SMTP id bp15-20020a170907918f00b00a1e3a14e84bmr1701152ejb.44.1705103835215; Fri, 12 Jan 2024 15:57:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705103835; cv=none; d=google.com; s=arc-20160816; b=wkYFqcyY7ToJkJ4+37HWcXp/PLxXkTJ6qXoa6B8lSjMId3HJnfQc2Ejl3TU2hAFRPv oO8nigOnst3aeQzBnoi59xMAZbo0uljjQrHRC9xr6N4Y/lzk7wf0fFvCwdxn0nkt7O4H yFq0Bq4bxi0tsUcYAitIdhoHSE6PASzPryg7dLSEg1769/vUjkbzCYxDDWwVLTkrQkyS F4VmVkg5o1C0rYSNCBgBzbcvh7qJp8sEGuQUKxOLjKvuqO7iL5r0z6CKOwJB2KLMTsxB h2ovxbUpz+yr8sYVSKCJdgMLClz3ppuABNp4YYi/7LmUt3odsWLrKH6fbc9PyXptBYqM s5WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=8ZPrT6/9y7GTRJXEMx1tnKXDzgpl8nPp7oBDsTEm8Wc=; fh=qPogcCrLsCYBo/9TCOpP+gmFKVDqSFHDtiwHbevqSF8=; b=07ndakw3mIWVAm4qqru0IXdVnhjogKPIOa1RdwPS8ij8m7/li+Ck2HNEPFJeFLpuBE GWJseb8OUzBARICo2yDBMICQi9vDDcMZN9jsjiHgMccUTWdmMz0cAlEbReGQiZRXIDi8 au3t/1Zz0O1j9C5ZwV6JakHLDs7XWB3LTNielRmwPSyWUi5AGCzvx7t8WY4IUD8cy8Bu JfjbbYKhCSZih8hLZIbcXDqlrkmHOuUDeeZolSj9/JBXsiGHexmK2tWGOElEm7BaY/ED PssYgM7uvWIBUHnmTM8DvTv7AWu4NcvDtiLduXZYnbt+Y/ywSXGnAwDYK4emZ2KcD58T wpNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=SFOqFyIp; spf=pass (google.com: domain of linux-kernel+bounces-25120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25120-ouuuleilei=gmail.com@vger.kernel.org" Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id g9-20020a170906394900b00a2afed17e93si1767141eje.191.2024.01.12.15.57.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jan 2024 15:57:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-25120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=SFOqFyIp; spf=pass (google.com: domain of linux-kernel+bounces-25120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25120-ouuuleilei=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id A71321F21CA6 for ; Fri, 12 Jan 2024 23:57:14 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3EFFF1BDC4; Fri, 12 Jan 2024 23:56:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="SFOqFyIp" Received: from mail-il1-f172.google.com (mail-il1-f172.google.com [209.85.166.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B23B81A5AC for ; Fri, 12 Jan 2024 23:56:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-il1-f172.google.com with SMTP id e9e14a558f8ab-3606e69ec67so45007155ab.2 for ; Fri, 12 Jan 2024 15:56:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1705103784; x=1705708584; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8ZPrT6/9y7GTRJXEMx1tnKXDzgpl8nPp7oBDsTEm8Wc=; b=SFOqFyIpJc08sirFK1gwy7/Qe5fHvOHapnEwh26GPZoHY9pTBUkdZGElXgw7Qo8CLv 99fB+FdfT9F1Fq03XTM63Go/l6oLCEsAxh/nTdkui92FNfpLM/DEzLrQoMs4TiUnvKpS ikPIGqIjzgVaBo4tWuaMWvBGNDKn8EbWCfqmogUygAQ/5U9zSZRREwuVsZn5m4SpMMsa QCFMKaicgENFKDXENDiZgJLxUxH+ukDFDQx4u+7WIHWFhbEk+SWRf09P9ItAK5wGqU8+ Lonk63IH0tPRBWqarLUWGmw6JPLMhgjUuyNpxC3BYo8vUtKjvW4PfRQsJLPFM9XoGQo+ Fy1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705103784; x=1705708584; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8ZPrT6/9y7GTRJXEMx1tnKXDzgpl8nPp7oBDsTEm8Wc=; b=YMWfgHS6GZ9D1LYMiCAsUQ5vihbCuAA8IjZfkuJBdPG3c5ifa/GsG60/aeA8mE7dS7 Z+iOZH2AU/N6fxG2Z9FVrCCv8z8yB1RllPpZ+ON8mM4s2SGny/vMP6N3OlbGB5VwxabS kDyDWARcbj3bP+Auxs8lwnA8+ufvM/dt6boPIMoSBCZtTvYz3iRtBkpUpIKgo+jR2NOi DLWOyI2uWv0COt8rMU4R8QN44ckBUsDHGfOs5J1sBYy7zd86fPRU2mm2FajBv5QbLEPv RvD2PgOwr4pcFxclw2TbVQElNC0n53CfPJ+iZ+90VhsIh38pVTfcTq++lw30H3UDrV+/ R3vw== X-Gm-Message-State: AOJu0YyDP1ppcr0dKsD3DZam+37P+baSWqSPPCLqgozFc7BKu/LBYzrw ZRhEo8R18jbPVFRwEoZl4VHiU9Y7bqXG/g== X-Received: by 2002:a92:d642:0:b0:35f:aba9:1031 with SMTP id x2-20020a92d642000000b0035faba91031mr2026091ilp.126.1705103783744; Fri, 12 Jan 2024 15:56:23 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id jc14-20020a17090325ce00b001d3b3ac2d7bsm3725537plb.245.2024.01.12.15.56.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jan 2024 15:56:23 -0800 (PST) From: Charlie Jenkins Date: Fri, 12 Jan 2024 15:56:20 -0800 Subject: [PATCH v7 1/2] riscv: Include riscv_set_icache_flush_ctx prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240112-fencei-v7-1-78f0614e1db0@rivosinc.com> References: <20240112-fencei-v7-0-78f0614e1db0@rivosinc.com> In-Reply-To: <20240112-fencei-v7-0-78f0614e1db0@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705103781; l=7834; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=IdbTkc3Q5t6sA8vLkrqSjebg3h+Stp0xkerv0GwEwco=; b=DFljA3ELwjm7M3ykiqZxlt6bGcQv8rzhZHSg/zi0qtVve1L7ETJZfuIxnYwlcJfFB4Uq9IHgt PFfuzrwL+8sDzjWUUZPkqIiowj+kAlIg28wSiK9URyZ6p/IrZR2H/en X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787930959317652694 X-GMAIL-MSGID: 1787930959317652694 Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable optimization of cross modifying code. This prctl enables userspace code to use icache flushing instructions such as fence.i with the guarantee that the icache will continue to be clean after thread migration. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra --- arch/riscv/include/asm/mmu.h | 2 ++ arch/riscv/include/asm/processor.h | 6 ++++ arch/riscv/mm/cacheflush.c | 67 ++++++++++++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 8 +++-- include/uapi/linux/prctl.h | 6 ++++ kernel/sys.c | 6 ++++ 6 files changed, 92 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..60be458e94da 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -19,6 +19,8 @@ typedef struct { #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; + /* Force local icache flush on all migrations. */ + bool force_icache_flush; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index f19f861cda54..7eda6c75e0f2 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -84,6 +84,9 @@ struct thread_struct { unsigned long vstate_ctrl; struct __riscv_v_ext_state vstate; unsigned long align_ctl; +#ifdef CONFIG_SMP + bool force_icache_flush; +#endif }; /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -145,6 +148,9 @@ extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(arg1, arg2) +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 55a34f2020a8..ff545f19f07a 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -152,3 +153,69 @@ void __init riscv_init_cbo_blocksizes(void) if (cboz_block_size) riscv_cboz_block_size = cboz_block_size; } + +/** + * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructions in + * userspace. + * @ctx: Set the type of icache flushing instructions permitted/prohibited in + * userspace. Supported values described below. + * + * Supported values for ctx: + * + * * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in userspace. + * + * * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in userspace. When ``scope == + * PR_RISCV_SCOPE_PER_PROCESS``, this will effect all threads in a process. + * Therefore, caution must be taken -- only use this flag when you can + * guarantee that no thread in the process will emit fence.i from this point + * onward. + * + * @scope: Set scope of where icache flushing instructions are allowed to be + * emitted. Supported values described below. + * + * Supported values for scope: + * + * * PR_RISCV_SCOPE_PER_PROCESS: Ensure the icache of any thread in this process + * is coherent with instruction storage upon + * migration. + * + * * PR_RISCV_SCOPE_PER_THREAD: Ensure the icache of the current thread is + * coherent with instruction storage upon + * migration. + * + * When ``scope == PR_RISCV_SCOPE_PER_PROCESS``, all threads in the process are + * permitted to emit icache flushing instructions. Whenever any thread in the + * process is migrated, the corresponding hart's icache will be guaranteed to be + * consistent with instruction storage. Note this does not enforce any + * guarantees outside of migration. If a thread modifies an instruction that + * another thread may attempt to execute, the other thread must still emit an + * icache flushing instruction before attempting to execute the potentially + * modified instruction. This must be performed by the userspace program. + * + * In per-thread context (eg. ``scope == PR_RISCV_SCOPE_PER_THREAD``), only the + * thread calling this function is permitted to emit icache flushing + * instructions. When the thread is migrated, the corresponding hart's icache + * will be guaranteed to be consistent with instruction storage. + * + * On kernels configured without SMP, this function is a nop as migrations + * across harts will not occur. + */ +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope) +{ +#ifdef CONFIG_SMP + switch (ctx) { + case PR_RISCV_CTX_SW_FENCEI_ON: + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + current->mm->context.force_icache_flush = true; + break; + case PR_RISCV_SCOPE_PER_THREAD: + current->thread.force_icache_flush = true; + break; + default: + return -EINVAL; + } + } +#endif + return 0; +} diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..0146c61be0ab 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -297,12 +297,14 @@ static inline void set_mm(struct mm_struct *prev, * * The "cpu" argument must be the current local CPU number. */ -static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu) +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu, + struct task_struct *task) { #ifdef CONFIG_SMP cpumask_t *mask = &mm->context.icache_stale_mask; - if (cpumask_test_cpu(cpu, mask)) { + if (cpumask_test_cpu(cpu, mask) || mm->context.force_icache_flush || + (task && task->thread.force_icache_flush)) { cpumask_clear_cpu(cpu, mask); /* * Ensure the remote hart's writes are visible to this hart. @@ -332,5 +334,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, set_mm(prev, next, cpu); - flush_icache_deferred(next, cpu); + flush_icache_deferred(next, cpu, task); } diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..524d546d697b 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,10 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 +# define PR_RISCV_CTX_SW_FENCEI_ON 0 +# define PR_RISCV_CTX_SW_FENCEI_OFF 1 +# define PR_RISCV_SCOPE_PER_PROCESS 0 +# define PR_RISCV_SCOPE_PER_THREAD 1 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 420d9cb9cc8e..e806a8a67c36 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,9 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef RISCV_SET_ICACHE_FLUSH_CTX +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) +#endif /* * this is where the system-wide overflow UID and GID are defined, for @@ -2739,6 +2742,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error = RISCV_V_GET_CONTROL(); break; + case PR_RISCV_SET_ICACHE_FLUSH_CTX: + error = RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); + break; default: error = -EINVAL; break; From patchwork Fri Jan 12 23:56:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 187844 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp508405dyc; Fri, 12 Jan 2024 15:57:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IGRzY6rrwKXGsFpLzVOrIF09vDHRLor2O8GQor4U3SjMmohC+CvLuUhUu58fmjEw56w6PAS X-Received: by 2002:a92:cdac:0:b0:360:5840:64be with SMTP id g12-20020a92cdac000000b00360584064bemr2262441ild.38.1705103840465; Fri, 12 Jan 2024 15:57:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705103840; cv=none; d=google.com; s=arc-20160816; b=TPMxxp1Sz4LaUwQobWKL4XvIpoPeQJjJBTQJJEMned4S0OZBz4863+tdmzBZmG26DU Lh34ki2aESe895aXi7xPS9gzN6brn1R2PYEw4b5QdrzTDrib8AQOB6XsUIojSgKd3rpT rYtckrMfDE0sxfV7JBJc1xjglyufv5tXIFE0V8PinsBgCyZ/6YttiQiSnXL7ENoNReDw MjUJux+uzDcjx3mWd4tOW3CcDyUqQQczATgj8peJkwDPoHvOeq+AzbmbX0FD1l50gh9j bzQwCrbQeRQAwdoKHf4fKr+LWprE7CE525b1n10h6x+Vq5b3jPiBlxPzoWRVrYmQ7d87 HJjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=rEBcVc42XhLbclEOiOTeHrqKkg/yMaKrCrHZS6upbrE=; fh=qPogcCrLsCYBo/9TCOpP+gmFKVDqSFHDtiwHbevqSF8=; b=vaX3xo96N8VWr3TA088X49rxDrELldjvQdpsZli8ZuPP8hmNOoMqTCPtlx0De7M9Eu bWTuDKxos6xV56mht/CQUE0qL5ejzTfKM8ZGmkbm+H4W+AvMX9HIMHp5uP71mCGn9an4 DuQXB5MQm9vJfRA7np08bvDJSbf8SOWvItyQmvwlf2fMX7Knfn7BxOf8uG6gls+MlnD2 adepzfyzIOpMk1WufLMF2FyBm1TSeI7jdq6xB6ILKRB5fL6Z1vxOgpKwYVQMoVXt1Ce6 qYocvx2P986Sqcqw7HjnMnN+/9XPjl2x43UzUSF+JkJreXSGc3k+IiSx+YnXG/AR1m2I 01UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=PuOQUF4A; spf=pass (google.com: domain of linux-kernel+bounces-25121-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25121-ouuuleilei=gmail.com@vger.kernel.org" Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id d18-20020a170903209200b001d4a8f240f4si3975883plc.425.2024.01.12.15.57.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jan 2024 15:57:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-25121-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=PuOQUF4A; spf=pass (google.com: domain of linux-kernel+bounces-25121-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25121-ouuuleilei=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 5B50CB2256D for ; Fri, 12 Jan 2024 23:57:15 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5F65D1BDC5; Fri, 12 Jan 2024 23:56:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="PuOQUF4A" Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC1A61A5BF for ; Fri, 12 Jan 2024 23:56:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1d3e05abcaeso50804195ad.1 for ; Fri, 12 Jan 2024 15:56:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1705103785; x=1705708585; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rEBcVc42XhLbclEOiOTeHrqKkg/yMaKrCrHZS6upbrE=; b=PuOQUF4AJD7+KafeAsSxhpKUyYK7t6UWeME/pXneBCX6ojv/HZ+cmWWu0F50Yd3s7c K8cVdhoSFFw8bmRUwp4d872XWunUUNy5KDtrVnBz808YJ0nxIaScampqMavlhPYBlbAl yRORTgj9R4dFY408jqf1N3oyGTBrFYtF0kASRvdzkZgtVsXo7hdQRscc8F+NvSJnF5Te mo277vhfUQIQuQwRZe+Dsu67gKy7cM1PXuFsTv2VuKZPyLA9zJSSYloznQBwiztZJVIX tVxgJMIZzfv6A2NcE3FIs3I7YMHHHCmWV1tvIuR5HKvAV2zTdQpQvnSucb+RSTqNrNX4 sKIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705103785; x=1705708585; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rEBcVc42XhLbclEOiOTeHrqKkg/yMaKrCrHZS6upbrE=; b=LySVNbWFtjBz9hUTdlFYFlma3c83bY850mCGsZOP6gN5DJWEz9vRUEl5HZulWVDAkD rGr6JBIEAdJXTARrD7zMlz4RrwIDt/3LXjpuJFBGYKCAeC8oFt0jd/rCMkptoQh4v/Ip rdLilCWfpn6x0dijXarDESYsVRYPIN2my8SqIQlmvv3/7rjxzYxrTYdyht9HFNgBuqwE u4fbkLN6HPmXuHxav6O1vlt8zNMcmgVLGSrZeEBFDz7h/y3DBgrWtPXnMf41H8VSzg8T tAzt7TffOj7D5NLpTZ6I1gUbKjRMANNQWWhKW9/79qGOVJQLSG47ICPQZJ321n8Z5Vqz BtlQ== X-Gm-Message-State: AOJu0YywRbFfwjoi4iXqvUrgMPoZ2grf9Lu0DCLgssRba0mJD6oc5lLx pb2+8DqjkVL4dqFaBHN5brEr/rKMlX2meg== X-Received: by 2002:a17:90a:39ce:b0:28c:b190:7f85 with SMTP id k14-20020a17090a39ce00b0028cb1907f85mr1693150pjf.13.1705103785134; Fri, 12 Jan 2024 15:56:25 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id jc14-20020a17090325ce00b001d3b3ac2d7bsm3725537plb.245.2024.01.12.15.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jan 2024 15:56:24 -0800 (PST) From: Charlie Jenkins Date: Fri, 12 Jan 2024 15:56:21 -0800 Subject: [PATCH v7 2/2] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240112-fencei-v7-2-78f0614e1db0@rivosinc.com> References: <20240112-fencei-v7-0-78f0614e1db0@rivosinc.com> In-Reply-To: <20240112-fencei-v7-0-78f0614e1db0@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705103781; l=3833; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=K6GU1jCnXJT3SY9+VUk3ZVtE1kDzv2SIhv7zwH/+BBM=; b=IIwtYnkypsYDf9+vi3bTkqQxfW18T9+8GE7LkRi/XsBDie8HMeanSj33rnURU6I++o2xxUcr+ RMM+6s5z2kOCPBLVFCEEsc9wRzO3ABlP9+RAZmyIWBEBaj1qTOBw6p7 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787930964763546029 X-GMAIL-MSGID: 1787930964763546029 Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra --- Documentation/arch/riscv/cmodx.rst | 88 ++++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 89 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst new file mode 100644 index 000000000000..7ae8ababa039 --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,88 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================================================== +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux +============================================================================== + +CMODX is a programming technique where a program executes instructions that were +modified by the program itself. Instruction storage and the instruction cache +(icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the +program must enforce its own synchronization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new hart. If +migration occurs after the userspace synchronized the icache and instruction +storage with fence.i, the icache will no longer be clean. This is due to the +behavior of fence.i only affecting the hart that it is called on. Thus, the hart +that the task has been migrated to may not have synchronized instruction storage +and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() syscall, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in +userspace. The syscall performs a one-off icache flushing operation. The prctl +changes the Linux ABI to allow userspace to emit icache flushing operations. + +prctl() Interface +--------------------- + +Call prctl() with ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` as the first argument. The +remaining arguments will be delegated to the riscv_set_icache_flush_ctx +function detailed below. + +.. kernel-doc:: arch/riscv/mm/cacheflush.c + :identifiers: riscv_set_icache_flush_ctx + +Example usage: + +The following files are meant to be compiled and linked with each other. The +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value = get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_ON, PR_RISCV_CTX_SW_FENCEI, PR_RISCV_SCOPE_PER_PROCESS); + modify_instruction(); + + value = get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx features