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Signed-off-by: Krishna chaitanya chundru Acked-by: Rob Herring Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index eadba38171e1..bc28669f6fa0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -777,6 +777,8 @@ allOf: - qcom,pcie-sa8540p - qcom,pcie-sa8775p - qcom,pcie-sc8280xp + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 then: required: - interconnects From patchwork Fri Jan 12 14:22:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 187751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp206772dyc; Fri, 12 Jan 2024 06:24:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IEQIZ05J+5X8K/J5tdJiNHWkN8Uj7mEKb+57366FCUOdSHoQvN9YcKuQiE+4ZKJP2Ky+0EI X-Received: by 2002:a05:622a:1012:b0:429:d3ea:ab1f with SMTP id d18-20020a05622a101200b00429d3eaab1fmr445053qte.31.1705069455565; Fri, 12 Jan 2024 06:24:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705069455; cv=none; d=google.com; s=arc-20160816; b=rIKD0S/ZSuqPH28tv7QmaqYtEwLdSbjIXpK1HTuec9lEL6hDdvNr/k2MLNL0B/soZZ 8zIEo3aGyRlamcycFYfLzSfS3YxBJYIkf5oEuE8KmTfhezJ96wNbHaeD+lRLqm1xqUhE ktZKq7o2dZtzXIIY0+b63ZknCG3xUACPdv3YiZ6xe2wOt8z1yGPYNy7KteI2N6vI1/cD eYsJ+2Q7KjKnabTKHUNKtoWzJ5j/Mqs92VdzK9CajbpmYGQfEnT+DQ6RQzLxjtPizSK7 cCcuxZCPPTduvskxENUXBTIrApjT3KHoodnfNCFSnTyrMS0AZ/fn2FZrNOHvKxJxq9X3 O2aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=gLfw8AIaJEv4HEZ0m3fuRz1wRBUGrrfxBc/+bWKiP/4=; fh=qy+4K2Our8FgIwRPsvePEWc9yS5HV+GOlB0H/jQK3pI=; b=lt62YfVp/tXhS7wJBQxTrTeaKeB+714MHCGcaB4uaQ3NujLNon9To6ZhnIfmXTtD4L 3s/2U1ewK0Y+S2ETd/o9BP1XFgssvdBN1yOHwlftaM+ucBBobQah7/e0SyLmlbUZM+4h Ff/gYuGBn4SL2fo6ph9Ry75gdBvm+oiF9nxfD08x2BIms4TZXqLEDH54LL3fUwO8fMoe Et+kRhAdTBpLP8BE4/k4/1lXnbJppu4IIQLYX5Vc8x/feT1lLkCxo5B/7lhkDiagyxkF pQBBb806aKQx4XgudM6JsfP1zPqc34Df+QhzhNMhyMfNkwp7OZnGm6dAS4xKVwT/JIco TZ/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Cpyw1YOR; spf=pass (google.com: domain of linux-kernel+bounces-24735-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-24735-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..6b1d2e0d9d14 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1781,6 +1781,10 @@ pcie0: pcie@1c00000 { <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1890,6 +1894,10 @@ pcie1: pcie@1c08000 { <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, From patchwork Fri Jan 12 14:22:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 187753 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp207039dyc; Fri, 12 Jan 2024 06:24:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IGJBaQ9H0o6HccBQOC67KIfCn+sXQcuJX+6Kr51zVG1MqgfcgeE3Gg8CEKK1myTiiDDzyoM X-Received: by 2002:a05:6402:b52:b0:558:e027:c460 with SMTP id bx18-20020a0564020b5200b00558e027c460mr733814edb.12.1705069479779; Fri, 12 Jan 2024 06:24:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705069479; cv=none; d=google.com; s=arc-20160816; b=DrqSxlBma1dXLgWRVNmtLK3EHM7IpaR1O2SubtepOxJjjCPTWiiWbJOhMInM0oefeb R4KDoYSUcSMc+aEUDoBi32JXOOJd9lUB3kzbiajNmy144uiqLFLcpJaILXiydXFzSvIv R7WOqS9/eapX2kbyOHGYudex+vDd3jtxDEDV8jXjlHt4iuKYHT5wJPtONfVcg5DA+DnZ +DxcBp/EN2nJJD0KMdOc0w5jFvf7XOoOAZ7PYycekQ3wNTswWrzXGNWze618udCb/ybU Wa/f78QZ98GxA0WW0/sLRjMS9OHClZP6x+CHkRfYGCNx+o0Jdi3k8G9cGhqs7LQcuThb qJSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=EQEeixSS21OvGRSeYUgmkjCTDJPNCEH8blpRpvwWulo=; fh=t3TklgoSlm2/4MZbuogAzhiaZ561HR3kFygAeMtFlAM=; b=ZEWXyoOtcAwdi/51gkeMZ6aCNYLHw1y3bWVaMkjhT6+lKC7xJjcVjLJQBjAG3tkfmz xV94o2FeS0tocT2arbU8GM77zfGuCWpIOzZILn1dBtxNbSmjrutGACyiBlyiT23xPpA1 qGVlPPKYDUjRcgzgVtKgmnbso5jYEBuzlR1FjuCBHSLV1sgsjoruNq3dOxx4hop5Yg/z tBJVNkGUOvtAFiIALblY+rIOZWMRTwlooLX+fjNlWuE5zTPu24AwQWDOj32g1g4L4qWL i17t4aO9arhzYhRBai1jXt4tGMsp+GodS0MxDUftdqpU+fd8BefCWP2JjwusT2TNDfHv wYYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=E9MySg8r; spf=pass (google.com: domain of linux-kernel+bounces-24737-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-24737-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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As there is less access on this path compared to pcie to mem path add minimum vote i.e GEN1x1 bandwidth always. In suspend remove the cpu vote after register space access is done. Fixes: c4860af88d0c ("PCI: qcom: Add basic interconnect support") cc: stable@vger.kernel.org Signed-off-by: Krishna chaitanya chundru Reviewed-by: Bryan O'Donoghue --- drivers/pci/controller/dwc/pcie-qcom.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 11c80555d975..035953f0b6d8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -240,6 +240,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; + struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; @@ -1372,6 +1373,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) if (IS_ERR(pcie->icc_mem)) return PTR_ERR(pcie->icc_mem); + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); + if (IS_ERR(pcie->icc_cpu)) + return PTR_ERR(pcie->icc_cpu); /* * Some Qualcomm platforms require interconnect bandwidth constraints * to be set before enabling interconnect clocks. @@ -1381,7 +1385,18 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) */ ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "failed to set interconnect bandwidth for pcie-mem: %d\n", + ret); + return ret; + } + + /* + * The config space, BAR space and registers goes through cpu-pcie path. + * Set peak bandwidth to single-lane Gen1 for this path all the time. + */ + ret = icc_set_bw(pcie->icc_cpu, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth for cpu-pcie: %d\n", ret); return ret; } @@ -1573,7 +1588,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) */ ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); if (ret) { - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); + dev_err(dev, "Failed to set interconnect bandwidth for pcie-mem: %d\n", ret); return ret; } @@ -1597,6 +1612,12 @@ static int qcom_pcie_suspend_noirq(struct device *dev) pcie->suspended = true; } + /* Remove cpu path vote after all the register access is done */ + ret = icc_set_bw(pcie->icc_cpu, 0, 0); + if (ret) { + dev_err(dev, "failed to set interconnect bandwidth for cpu-pcie: %d\n", ret); + return ret; + } return 0; } @@ -1605,6 +1626,12 @@ static int qcom_pcie_resume_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); int ret; + ret = icc_set_bw(pcie->icc_cpu, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); + if (ret) { + dev_err(dev, "failed to set interconnect bandwidth for cpu-pcie: %d\n", ret); + return ret; + } + if (pcie->suspended) { ret = qcom_pcie_host_init(&pcie->pci->pp); if (ret) From patchwork Fri Jan 12 14:22:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 187754 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp207217dyc; Fri, 12 Jan 2024 06:24:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IEi8fTKO29tMMNbetxZxFczXBg/9gz4LLzbb/6eIeNFMMuZ39nuTCA0PdQTvwSOvlszzc9x X-Received: by 2002:a67:f709:0:b0:468:1008:141d with SMTP id m9-20020a67f709000000b004681008141dmr1034075vso.40.1705069496151; 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Adding the Operating Performance Points table allows to adjust power domain performance state and icc peak bw, depending on the PCIe gen speed and width. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index bc28669f6fa0..a37b2ef7dbfc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -122,6 +122,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg From patchwork Fri Jan 12 14:22:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 187755 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp207456dyc; Fri, 12 Jan 2024 06:25:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IFunHjHpnwlQ1NAQePWXI2gNjLGbWEUVtBp4lqfizglC9wZ25CMJLhNjTYYaYYDVez19QeO X-Received: by 2002:a67:fe88:0:b0:468:112b:3c95 with SMTP id b8-20020a67fe88000000b00468112b3c95mr1911013vsr.20.1705069514839; Fri, 12 Jan 2024 06:25:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705069514; cv=none; d=google.com; s=arc-20160816; b=NRalJLYdrCjvmdMleQ0wSJVVr51SflUcEh+DBvNOwK8rz2qJP6MzcTyV/6Cs6tgXqN mga32K17UWXf/KgzY96vD2v1cHZPvevL1rbB/cfUevMSbFftWeQhLffbp28r7OBpWKg2 6oYph+LctnAeQzyEjORlmBvqJWvEvZaiHHs8Aoz1l3qPkN3xQElW2ATICfh3Itny0yje xBXjiyxvC+EQrzEA8AnjkotdP8A+UkfHIGUMKS1zTB+4vPeDEzzz+uWaLgeI5Qf7KSK6 Ir0j93pKzmaoYFm7BQ8UCWXwXmkN5aVOc2WUpYAQZXZLgyRncdNen29ZW+nSeU+3jWTV vrMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=j4G+WA6H+z2u1MOFTfSX+TMcgfWW0vSaHHxynkn1f6A=; fh=qy+4K2Our8FgIwRPsvePEWc9yS5HV+GOlB0H/jQK3pI=; b=YnuyeeZaV5MKf00m8RFpBuCs+eSZR1ESJR1QNJs4tKS/wlq7M53SF1WsV8CblnOjxm Cb1pqVvrbcnNL5Z+KgMFzVVgyDVDiUOZc85MjCtTlSygZhScOJUjfvlLw4eTs+WSEfJu oFnCK7YK1doT7oEGQKSFwlT4nDU9aUAYomm3baNRKxmSqkzUrJXi7kHyQZJHyRcHNfs0 v7IzTkxF/T2/aLASFdXdjWF8rquq6BwhJCNtskGCBeWOeY64vzLl5Dx5UUdjz1mjvoQ4 tfkBsjISO2OOsFMWbquXyXgphBvaJKLLg8gvKB9lFYL6W/gyqC1gGuA9EJpOK0r15aDN Raiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Z3omn30K; spf=pass (google.com: domain of linux-kernel+bounces-24739-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-24739-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Add the OPP table support to specify RPMH performance states and interconnect peak bandwidth. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6b1d2e0d9d14..eab85ecaeff0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1827,7 +1827,32 @@ pcie0: pcie@1c00000 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 250000>; + }; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 250000>; + }; + + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 250000>; + }; + }; + }; pcie0_phy: phy@1c06000 { @@ -1938,7 +1963,56 @@ pcie1: pcie@1c08000 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 250000>; + }; + + /* GEN 1x2 GEN 2x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 250000>; + }; + + /* GEN 2x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 250000>; + }; + + /* GEN 3x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 250000>; + }; + + /* GEN 3x2 GEN 4x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 250000>; + }; + + /* GEN 4x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 250000>; + }; + }; + }; pcie1_phy: phy@1c0e000 { From patchwork Fri Jan 12 14:22:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 187756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp207679dyc; Fri, 12 Jan 2024 06:25:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IECKkwTZ1v0P4cAnBAq21eOhENm8m+1jeA/B85MgKtUsBPuCuxs4I5XhtwcaB066peBkDyv X-Received: by 2002:a05:6a00:4503:b0:6da:6c33:f269 with SMTP id cw3-20020a056a00450300b006da6c33f269mr868215pfb.25.1705069535048; Fri, 12 Jan 2024 06:25:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705069535; cv=none; d=google.com; s=arc-20160816; b=GPINqpQPoCr03v9YWP0+950OEgWk4exluwhaKLXJEGbt1+RoyCR6UozQNZQhbkJQIv w3xaJFBfPhchZE2CDvUkgDUCMVVWqDY7CVhTl2GH+i91ebqe/KrtLqZL6MX0r3W+2I0v 6zLe46aKTvFQ14/11BBNUtxRRjF7QlPUnkHKLkAeGP3j1R52Gwx6bOc+4nnObChZ7guV 4+ytGUzBrS00Zb7Csxyh86SglhvItqOv8JhIrt1jlpttWvmwVrvttzZI2ENpSV9ErIyc NukzBw6CZRtZY/ZUJYNH9j7qr0ynEH5ApoEYAZlNfNQs6T9Lh9z0LvKkDH/SkwYVHRC3 h3FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=7A77C1bSS37WpSitpH9pPkRNIJBrqGXzPtEVUEKvxU0=; fh=qy+4K2Our8FgIwRPsvePEWc9yS5HV+GOlB0H/jQK3pI=; b=v4VZy0GlOgTONgKIevzs5f2c2M/VMoES/mll/TfrlFn7OG413ydXG82d+ZLXysGhbk LUHA/RXGSsQeUkiQRV6dSH69QwGZeucu3SLRRXSm9Q6kTfD4hkqpqx33CNUvAWqwuydT 0uMYqUTiC9yrNMZa5nIE4HN61kx13t/68q1mOAS8ZNi/7RALS+VE5ExnUOFrQtRVtOh/ EILboP290JaoYccg2Mk5vFTqUkIlHBUwchB2qoWvkRXAbRMwsxYcfJcBDxt4+D5Q55Uf R4yQsKQ2lXqfPzm76p6Ibqqn+C6Zm7VidlLxIJECPBVn45g0BDHelFJuN532E9cdqHrH XjaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="Hg/wdzzR"; spf=pass (google.com: domain of linux-kernel+bounces-24740-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-24740-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Fri, 12 Jan 2024 14:22:57 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 12 Jan 2024 06:22:51 -0800 From: Krishna chaitanya chundru Date: Fri, 12 Jan 2024 19:52:05 +0530 Subject: [PATCH v6 6/6] PCI: qcom: Add OPP support to scale performance state of power domain Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240112-opp_support-v6-6-77bbf7d0cc37@quicinc.com> References: <20240112-opp_support-v6-0-77bbf7d0cc37@quicinc.com> In-Reply-To: <20240112-opp_support-v6-0-77bbf7d0cc37@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , "Lorenzo Pieralisi" , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Rob Herring , Johan Hovold , Brian Masney , Georgi Djakov CC: , , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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PCIe controller can operate on different RPMh performance state of power domain based up on the speed of the link. And this performance state varies from target to target. It is manadate to scale the performance state based up on the PCIe speed link operates so that SoC can run under optimum power conditions. Add Operating Performance Points(OPP) support to vote for RPMh state based upon GEN speed link is operating. OPP can handle ICC bw voting also, so move icc bw voting through opp framework if opp entries are present. In PCIe certain gen speeds like GEN1x2 & GEN2X1 or GEN3x2 & GEN4x1 use same icc bw and has frequency, so use frequency based search to reduce number of entries in the opp table. Don't initialize icc if opp is supported. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 83 ++++++++++++++++++++++++++++------ 1 file changed, 70 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 035953f0b6d8..31512dc9d6ff 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -244,6 +245,7 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; + bool opp_supported; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -1404,16 +1406,14 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) return 0; } -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u32 offset, status; + u32 offset, status, freq; + struct dev_pm_opp *opp; int speed, width; int ret; - if (!pcie->icc_mem) - return; - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); @@ -1424,11 +1424,42 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); - if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); + if (pcie->opp_supported) { + switch (speed) { + case 1: + freq = 2500000; + break; + case 2: + freq = 5000000; + break; + case 3: + freq = 8000000; + break; + default: + WARN_ON_ONCE(1); + fallthrough; + case 4: + freq = 16000000; + break; + } + + opp = dev_pm_opp_find_freq_exact(pci->dev, freq * width, true); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set opp: freq %ld ret %d\n", + dev_pm_opp_get_freq(opp), ret); + dev_pm_opp_put(opp); + } + } else { + ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth for pcie-mem: %d\n", + ret); + } } + + return; } static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) @@ -1471,8 +1502,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; + unsigned long max_freq = INT_MAX; struct device *dev = &pdev->dev; struct qcom_pcie *pcie; + struct dev_pm_opp *opp; struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; @@ -1539,9 +1572,33 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = qcom_pcie_icc_init(pcie); - if (ret) + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) { + dev_err_probe(dev, ret, "Failed to add OPP table\n"); goto err_pm_runtime_put; + } + + /* vote for max freq in the opp table if opp table is present */ + if (ret != -ENODEV) { + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(dev, opp); + if (ret) + dev_err_probe(pci->dev, ret, + "Failed to set opp: freq %ld\n", + dev_pm_opp_get_freq(opp)); + dev_pm_opp_put(opp); + } + pcie->opp_supported = true; + } + + /* Skip icc init if opp is supported as icc bw vote is handled by opp framework */ + if (!pcie->opp_supported) { + ret = qcom_pcie_icc_init(pcie); + if (ret) + goto err_pm_runtime_put; + } ret = pcie->cfg->ops->get_resources(pcie); if (ret) @@ -1561,7 +1618,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) qcom_pcie_init_debugfs(pcie); @@ -1640,7 +1697,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) pcie->suspended = false; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); return 0; }