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([106.51.188.200]) by smtp.gmail.com with ESMTPSA id jd2-20020a170903260200b001d4a7cf0673sm730566plb.117.2024.01.11.01.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 01:31:11 -0800 (PST) From: Sunil V L To: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org Cc: "Rafael J . Wysocki" , Len Brown , Anup Patel , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Andrew Jones , Atish Kumar Patra , Sunil V L Subject: [PATCH -next 1/2] ACPI: Enable ACPI_PROCESSOR for RISC-V Date: Thu, 11 Jan 2024 15:00:57 +0530 Message-Id: <20240111093058.121838-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111093058.121838-1-sunilvl@ventanamicro.com> References: <20240111093058.121838-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787786011792693138 X-GMAIL-MSGID: 1787786011792693138 The ACPI processor driver is not currently enabled for RISC-V. This is required to enable CPU related functionalities like LPI and CPPC. Hence, enable ACPI_PROCESSOR for RISC-V. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- drivers/acpi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index f819e760ff19..9a920752171c 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -282,7 +282,7 @@ config ACPI_CPPC_LIB config ACPI_PROCESSOR tristate "Processor" - depends on X86 || ARM64 || LOONGARCH + depends on X86 || ARM64 || LOONGARCH || RISCV select ACPI_PROCESSOR_IDLE select ACPI_CPU_FREQ_PSS if X86 || LOONGARCH select THERMAL From patchwork Thu Jan 11 09:30:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 187267 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp1329627dyi; Thu, 11 Jan 2024 01:32:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IGpLKkidhbciwBht42lD6uPfOOHmo0uUVuFjlqk3ybzi7/9goSZuTm3Jzipc7Sc/nYEm9RU X-Received: by 2002:a17:906:f8cd:b0:a2b:1e4a:e2e6 with SMTP id lh13-20020a170906f8cd00b00a2b1e4ae2e6mr493322ejb.11.1704965569104; Thu, 11 Jan 2024 01:32:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704965569; cv=none; d=google.com; s=arc-20160816; b=eCty1TF9buGVuOFFizb4ayZU6zGQlX02/dRbDNtxo/zJFO5BGsK197hMPeZlob71vs XTxdf6tzbhlsn1nRwfS9fkk+bUXSHz6jyuz9NiaoV8T81CI4mclYiVtHWlGqCPzAPxCk O8xIoGeJgErTNF4/87jqW5oojbaNbzdxhFJ7V51vcnoD1me3q0z03AAk/Fl5DKvL3kHI Bxz5Wvb7mYQw1BGXnJ8uCOOIhz1bppjZ2RJ940PFQFlwvA34kA85XpMbP0LSs9aG2aF2 1hiIDX2TOSw4OclPpQsg8U9HWMuGrUiILbTaMI8eCjjqBtcMqB3RrH9QeJd6F5R3Tqn8 4cJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=cUtZ/fl35OGrV0n4xrT7BhxLu5Q7HTfNcZ5vLHqEvsY=; fh=Ht2C34ikojivmsjwXjSqFBDmzjHdD6yX68Xa6Pv6fTI=; b=C4AcFHDk6WlMzk7ihPrX3wNzHmQ2RRBGbNuPkBiSB6hD7pkwJ6BnhP6w2mzGuusUzy /NhbP3cIcsZv1j4lepq+XFCDDd94sC1rIMCwNf+pDQW1jA+pZ76ZEKnlOLKJQYQ7S77T q8ZHqLRtVjNVccftO+bMmqbOb2wgFFgpioNDdGQ3FNa6XvgCKvuKQiX8lhjlyJGldha2 8scyBgzufGl7S+yBkFArXm/n6nUasowsvp+LE7BVA26uG26o3TUzGetGl4K1gXqn5j4F ag/h953ewXDn+K7sET1zThcUqCUMluvWE9p5tCP+3tZIws8XiwAycTopvr4M7nEqFvCT Z1MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aAhgOOjr; spf=pass (google.com: domain of linux-kernel+bounces-23319-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-23319-ouuuleilei=gmail.com@vger.kernel.org" Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([106.51.188.200]) by smtp.gmail.com with ESMTPSA id jd2-20020a170903260200b001d4a7cf0673sm730566plb.117.2024.01.11.01.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 01:31:16 -0800 (PST) From: Sunil V L To: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org Cc: "Rafael J . Wysocki" , Len Brown , Anup Patel , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Andrew Jones , Atish Kumar Patra , Sunil V L Subject: [PATCH -next 2/2] cpuidle: RISC-V: Add ACPI LPI support Date: Thu, 11 Jan 2024 15:00:58 +0530 Message-Id: <20240111093058.121838-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111093058.121838-1-sunilvl@ventanamicro.com> References: <20240111093058.121838-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787785976965695407 X-GMAIL-MSGID: 1787785976965695407 Add required callbacks to support Low Power Idle (LPI) on ACPI based RISC-V platforms. Signed-off-by: Sunil V L --- drivers/cpuidle/cpuidle-riscv-sbi.c | 78 +++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/cpuidle/cpuidle-riscv-sbi.c b/drivers/cpuidle/cpuidle-riscv-sbi.c index e8094fc92491..cea67a54ab39 100644 --- a/drivers/cpuidle/cpuidle-riscv-sbi.c +++ b/drivers/cpuidle/cpuidle-riscv-sbi.c @@ -632,3 +632,81 @@ static int __init sbi_cpuidle_init(void) return 0; } device_initcall(sbi_cpuidle_init); + +#ifdef CONFIG_ACPI_PROCESSOR_IDLE + +#include +#include + +#define RISCV_FFH_LPI_TYPE_MASK 0x1000000000000000ULL +#define RISCV_FFH_LPI_RSVD_MASK 0x0FFFFFFF00000000ULL + +static int acpi_cpu_init_idle(unsigned int cpu) +{ + int i; + struct acpi_lpi_state *lpi; + struct acpi_processor *pr = per_cpu(processors, cpu); + + if (unlikely(!pr || !pr->flags.has_lpi)) + return -EINVAL; + + /* + * The SBI HSM suspend function is only available when: + * 1) SBI version is 0.3 or higher + * 2) SBI HSM extension is available + */ + if (sbi_spec_version < sbi_mk_version(0, 3) || + !sbi_probe_extension(SBI_EXT_HSM)) { + pr_warn("HSM suspend not available\n"); + return -EINVAL; + } + + if (pr->power.count <= 1) + return -ENODEV; + + for (i = 1; i < pr->power.count; i++) { + u32 state; + + lpi = &pr->power.lpi_states[i]; + + /* Validate Entry Method as per FFH spec. + * bits[63:60] should be 0x1 + * bits[59:32] should be 0x0 + * bits[31:0] represent a SBI power_state + */ + if (!(lpi->address & RISCV_FFH_LPI_TYPE_MASK) || + (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) { + pr_warn("Invalid LPI entry method %#llx\n", lpi->address); + return -EINVAL; + } + + state = lpi->address; + if (!sbi_suspend_state_is_valid(state)) { + pr_warn("Invalid SBI power state %#x\n", state); + return -EINVAL; + } + } + + return 0; +} + +int acpi_processor_ffh_lpi_probe(unsigned int cpu) +{ + return acpi_cpu_init_idle(cpu); +} + +int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) +{ + u32 state = lpi->address; + + if (state & SBI_HSM_SUSP_NON_RET_BIT) + return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, + lpi->index, + state); + else + return CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM(sbi_suspend, + lpi->index, + state); +} + +#endif