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[147.75.80.249]) by mx.google.com with ESMTPS id t4-20020a056402524400b00553d87f48c7si1841471edd.571.2024.01.10.07.15.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:15:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-22404-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@fairphone.com header.s=fair header.b=ASB0evTS; spf=pass (google.com: domain of linux-kernel+bounces-22404-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22404-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=fairphone.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id AB2CE1F23230 for ; Wed, 10 Jan 2024 15:15:08 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3E3D4C3DB; Wed, 10 Jan 2024 15:14:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="ASB0evTS" Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 404CD4BAAC for ; Wed, 10 Jan 2024 15:14:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Received: by mail-wm1-f66.google.com with SMTP id 5b1f17b1804b1-40e43e489e4so47907175e9.1 for ; Wed, 10 Jan 2024 07:14:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1704899657; x=1705504457; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5Sy3lixVdO+ssOCBS2YWjdDhiY4KhMhsBIz9dLLKsi4=; b=ASB0evTSIyJ8rkwyCgCQB8gDS1MCsjrs8/UyM1tuBnDUmNTEioQH826cFFsRzEQ22f EAo6E4bvBxQRW2elm9IoRYviJCmaPSXWYwfkwdBuxFKf7bTyHZJfPju2QOCr5uhCfI5W AA3FpKt1LVeru6hveBIIsKi37ts+ygrHk1A+ugBDNcmDf1x/0do+Jf7QWM5gRGLkCK/e g503dt0Hcz1WyA4QBK1e7hemkiW+n7UKFzlXtnNAKDv7rxlb/riZUPfUm7E8/3fYDYR5 Y9YYDRMrOBzEeP0ttaFQE9DBru0FB0ezPko7GURpB+Y7r15OfyarrWN8gqxRX8X2LUxO 37zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704899657; x=1705504457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Sy3lixVdO+ssOCBS2YWjdDhiY4KhMhsBIz9dLLKsi4=; b=H29SYyU7H/PDJqTxqblXTKPxAqqpz0HiTQepjdImz53G+l/58bQgobdOA6JXTBmllF HeFAZ8qIcB62XR9j4owEkC5EvZ+m6/nnhMsFGmutrvxE7FVtzuQ+V93uNpEDZsaW7RYI snVH1r2AOBH/guZF7gxdmTjI9VWccC+cMDMvgh2FKoj6XcFORlzHW6qbueommNaIJ7dX +/4+ayQBLz/NOIZQC2qPMfSI6xNrR/gXLtqQy6UwCRvMJKTH76UbHn5U6dddvDX0nDCy tiWyzTz6CL5DqUU/hvaY1IyN8n0H6NivzuF1i8KB6NsP1Sg6DpBODJAhfoXOjOjsTEJh L8OQ== X-Gm-Message-State: AOJu0YxMdcNzdyCAvff7PpxLfCWCBfgumDip2f0XRQxXQJ71XR+tHCRB 7ixQ7GVV1NxqaAP4kRl+tqF2mCeD6ZxfMw== X-Received: by 2002:a05:600c:310f:b0:40e:3ab9:102d with SMTP id g15-20020a05600c310f00b0040e3ab9102dmr661174wmo.181.1704899657574; Wed, 10 Jan 2024 07:14:17 -0800 (PST) Received: from otso.luca.vpn.lucaweiss.eu (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:17 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:08 +0100 Subject: [PATCH v2 1/4] dt-bindings: display: panel: Add Himax HX83112A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240110-fp4-panel-v2-1-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787716917337500588 X-GMAIL-MSGID: 1787716917337500588 Himax HX83112A is a display driver IC used to drive LCD DSI panels. Describe it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss --- .../bindings/display/panel/himax,hx83112a.yaml | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83112a.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83112a.yaml new file mode 100644 index 000000000000..22f58f1da9fd --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83112a.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX83112A-based DSI display panels + +maintainers: + - Luca Weiss + +description: + The Himax HX83112A is a generic DSI Panel IC used to control + LCD panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: fairphone,fp4-hx83112a-djn + - const: himax,hx83112a + + vdd1-supply: + description: Digital voltage rail + + vsn-supply: + description: Positive source voltage rail + + vsp-supply: + description: Negative source voltage rail + + reg: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd1-supply + - vsn-supply + - vsp-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "fairphone,fp4-hx83112a-djn", "himax,hx83112a"; + reg = <0>; + + backlight = <&pm6150l_wled>; + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply = <&vreg_l1e>; + vsn-supply = <&pm6150l_lcdb_ncp>; + vsp-supply = <&pm6150l_lcdb_ldo>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + +... 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:17 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:09 +0100 Subject: [PATCH v2 2/4] drm/panel: Add driver for DJN HX83112A LCD panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240110-fp4-panel-v2-2-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787716978300999465 X-GMAIL-MSGID: 1787716978300999465 Add support for the 2340x1080 LCD DJN panel bundled with a HX83112A driver IC, as found on the Fairphone 4 smartphone. Signed-off-by: Luca Weiss --- drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-himax-hx83112a.c | 352 +++++++++++++++++++++++++++ 3 files changed, 363 insertions(+) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 99e14dc212ec..3379b13df4b8 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -162,6 +162,16 @@ config DRM_PANEL_FEIYANG_FY07024DI26A30D Say Y if you want to enable support for panels based on the Feiyang FY07024DI26A30-D MIPI-DSI interface. +config DRM_PANEL_HIMAX_HX83112A + tristate "Himax HX83112A-based DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select DRM_KMS_HELPER + help + Say Y here if you want to enable support for Himax HX83112A-based + display panels, such as the one found in the Fairphone 4 smartphone. + config DRM_PANEL_HIMAX_HX8394 tristate "HIMAX HX8394 MIPI-DSI LCD panels" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index d10c3de51c6d..c2fc4c8c8340 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o +obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o diff --git a/drivers/gpu/drm/panel/panel-himax-hx83112a.c b/drivers/gpu/drm/panel/panel-himax-hx83112a.c new file mode 100644 index 000000000000..cccc6075fd8e --- /dev/null +++ b/drivers/gpu/drm/panel/panel-himax-hx83112a.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree. + * Copyright (c) 2024 Luca Weiss + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct hx83112a_panel { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct regulator_bulk_data supplies[3]; + struct gpio_desc *reset_gpio; +}; + +static inline struct hx83112a_panel *to_hx83112a_panel(struct drm_panel *panel) +{ + return container_of(panel, struct hx83112a_panel, panel); +} + +static void hx83112a_reset(struct hx83112a_panel *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(20); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + msleep(20); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(50); +} + +static int hx83112a_on(struct hx83112a_panel *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x83, 0x11, 0x2a); + mipi_dsi_dcs_write_seq(dsi, 0xb1, + 0x08, 0x28, 0x28, 0x83, 0x83, 0x4c, 0x4f, 0x33); + mipi_dsi_dcs_write_seq(dsi, 0xb2, + 0x00, 0x02, 0x00, 0x90, 0x24, 0x00, 0x08, 0x19, + 0xea, 0x11, 0x11, 0x00, 0x11, 0xa3); + mipi_dsi_dcs_write_seq(dsi, 0xb4, + 0x58, 0x68, 0x58, 0x68, 0x0f, 0xef, 0x0b, 0xc0, + 0x0b, 0xc0, 0x0b, 0xc0, 0x00, 0xff, 0x00, 0xff, + 0x00, 0x00, 0x14, 0x15, 0x00, 0x29, 0x11, 0x07, + 0x12, 0x00, 0x29); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xb4, + 0x00, 0x12, 0x12, 0x11, 0x88, 0x12, 0x12, 0x00, + 0x53); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x03); + mipi_dsi_dcs_write_seq(dsi, 0xc1, + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, + 0x40); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xc1, + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, + 0x40); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xc1, + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, + 0x40); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xc7, 0x70, 0x00, 0x04, 0xe0, 0x33, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x08); + mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x2b, 0x2b); + mipi_dsi_dcs_write_seq(dsi, 0xd3, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, + 0x08, 0x03, 0x03, 0x22, 0x18, 0x07, 0x07, 0x07, + 0x07, 0x32, 0x10, 0x06, 0x00, 0x06, 0x32, 0x10, + 0x07, 0x00, 0x07, 0x32, 0x19, 0x31, 0x09, 0x31, + 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x09, 0x30, 0x00, 0x00, 0x00, 0x06, 0x0d, 0x00, + 0x0f); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xd3, + 0x00, 0x00, 0x19, 0x10, 0x00, 0x0a, 0x00, 0x81); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xd5, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0xc0, 0xc0, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, + 0x28, 0x28, 0x24, 0x24, 0x02, 0x03, 0x02, 0x03, + 0x00, 0x01, 0x00, 0x01, 0x31, 0x31, 0x31, 0x31, + 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); + mipi_dsi_dcs_write_seq(dsi, 0xd6, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, + 0x24, 0x24, 0x28, 0x28, 0x01, 0x00, 0x01, 0x00, + 0x03, 0x02, 0x03, 0x02, 0x31, 0x31, 0x31, 0x31, + 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, + 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, 0xaa, 0xaa); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0x2e, 0x28, 0x00, 0x00, 0x00, 0xaa, 0x2e, + 0x28, 0x00, 0x00, 0x00, 0xaa, 0xee, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xee, 0xaa, 0xaa, 0xaa, 0xaa); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xff, + 0xff, 0xff, 0xff, 0xff); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x03); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xe7, + 0x0e, 0x0e, 0x1e, 0x65, 0x1c, 0x65, 0x00, 0x50, + 0x20, 0x20, 0x00, 0x00, 0x02, 0x02, 0x02, 0x05, + 0x14, 0x14, 0x32, 0xb9, 0x23, 0xb9, 0x08); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xe7, + 0x02, 0x00, 0xa8, 0x01, 0xa8, 0x0d, 0xa4, 0x0e); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xe7, + 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0xc3); + mipi_dsi_dcs_write_seq(dsi, 0xcb, 0xd1, 0xd6); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0x3f); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0xc6); + mipi_dsi_dcs_write_seq(dsi, 0xbf, 0x37); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0x3f); + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + msleep(150); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display on: %d\n", ret); + return ret; + } + msleep(50); + + return 0; +} + +static int hx83112a_disable(struct drm_panel *panel) +{ + struct hx83112a_panel *ctx = to_hx83112a_panel(panel); + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display off: %d\n", ret); + return ret; + } + msleep(20); + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + return 0; +} + +static int hx83112a_prepare(struct drm_panel *panel) +{ + struct hx83112a_panel *ctx = to_hx83112a_panel(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + + hx83112a_reset(ctx); + + ret = hx83112a_on(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + return ret; + } + + return 0; +} + +static int hx83112a_unprepare(struct drm_panel *panel) +{ + struct hx83112a_panel *ctx = to_hx83112a_panel(panel); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + + return 0; +} + +static const struct drm_display_mode hx83112a_mode = { + .clock = (1080 + 28 + 8 + 8) * (2340 + 27 + 5 + 5) * 60 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 28, + .hsync_end = 1080 + 28 + 8, + .htotal = 1080 + 28 + 8 + 8, + .vdisplay = 2340, + .vsync_start = 2340 + 27, + .vsync_end = 2340 + 27 + 5, + .vtotal = 2340 + 27 + 5 + 5, + .width_mm = 67, + .height_mm = 145, + .type = DRM_MODE_TYPE_DRIVER, +}; + +static int hx83112a_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + return drm_connector_helper_get_modes_fixed(connector, &hx83112a_mode); +} + +static const struct drm_panel_funcs hx83112a_panel_funcs = { + .prepare = hx83112a_prepare, + .unprepare = hx83112a_unprepare, + .disable = hx83112a_disable, + .get_modes = hx83112a_get_modes, +}; + +static int hx83112a_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct hx83112a_panel *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->supplies[0].supply = "vdd1"; + ctx->supplies[1].supply = "vsn"; + ctx->supplies[2].supply = "vsp"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HSE | + MIPI_DSI_CLOCK_NON_CONTINUOUS; + + drm_panel_init(&ctx->panel, dev, &hx83112a_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first = true; + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void hx83112a_remove(struct mipi_dsi_device *dsi) +{ + struct hx83112a_panel *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id hx83112a_of_match[] = { + { .compatible = "fairphone,fp4-hx83112a-djn" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, hx83112a_of_match); + +static struct mipi_dsi_driver hx83112a_driver = { + .probe = hx83112a_probe, + .remove = hx83112a_remove, + .driver = { + .name = "panel-himax-hx83112a", + .of_match_table = hx83112a_of_match, + }, +}; +module_mipi_dsi_driver(hx83112a_driver); + +MODULE_DESCRIPTION("DRM driver for hx83112a-equipped DSI panels"); +MODULE_LICENSE("GPL"); From patchwork Wed Jan 10 15:14:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 186929 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp857807dyi; Wed, 10 Jan 2024 07:15:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IE55M+BJpY0GjtkUBWIX4y4gh/H0vUR7W+vPFOTX9d2NlqEAckSbICL7CaUvH5jZmAQpFT6 X-Received: by 2002:a05:620a:1473:b0:781:565c:3d8 with SMTP id j19-20020a05620a147300b00781565c03d8mr1064891qkl.90.1704899744094; Wed, 10 Jan 2024 07:15:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704899744; cv=none; d=google.com; s=arc-20160816; b=ifP+Qbpt46ERf33yxttp1fAzlZPNScISAMC9SoaBp7WMZ73+ipQJ9h0rEz0Q4xG2v1 ykj5c0ogI/uvw1eErqNM5OFTAjinrz5YZqmJNEvc59msp1SUGYQ0wjsDlumq8AfDWwAh oB6IBFMTw81l8Q7QzyD6YOtZjut1LZ42d2WlRUw7B4vOf9iGM7/+wHJTY30nbJzvTwfC 3NStCjWTElDRASlZf5fkXrTrsadjRG3p1cIO5fbQpGpuMeEp6sJZqq3S0DC0Gj0eV862 LFDvjKBFv39MFltC6/KTpXs7KwJfVXpTPz+CnJz1+pfeFUNL151qjeWWyRQd4dJkyOph 53LQ== ARC-Message-Signature: i=1; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:19 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:10 +0100 Subject: [PATCH v2 3/4] arm64: dts: qcom: sm6350: Remove "disabled" state of GMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240110-fp4-panel-v2-3-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787716954053808044 X-GMAIL-MSGID: 1787716954053808044 The GMU won't probe without GPU being enabled, so we can remove the disabled status so we don't have to explicitly enable the GMU in all the devices that enable GPU. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8fd6f4d03490..29008e155d62 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1449,8 +1449,6 @@ gmu: gmu@3d6a000 { operating-points-v2 = <&gmu_opp_table>; - status = "disabled"; - gmu_opp_table: opp-table { compatible = "operating-points-v2"; From patchwork Wed Jan 10 15:14:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 186930 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp857832dyi; Wed, 10 Jan 2024 07:15:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdKWokRsEycu2RUflIC5Y/aGp04huZ/Fez6ljazFYm4g8i3Khu51110KjPzr71CeE06VyB X-Received: by 2002:a17:906:5:b0:a2c:148b:4951 with SMTP id 5-20020a170906000500b00a2c148b4951mr171399eja.70.1704899746651; Wed, 10 Jan 2024 07:15:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704899746; cv=none; d=google.com; s=arc-20160816; b=Ux/GBFB5TSQOJ8WTUKnXj+rn4gubwcfQCbDKAT5tqoDCn9XWZGD7Vmb0mxhCCLtGCs +wB5S1WhetzFTtQAOBs/1ATg50AnlKOgqf53UWIWgDekBmcfUxfLm/Ec9z++yIvox2Kf EklvsuNXWKOjWk7TI5l4ql3uXGayOB2nOevv6NOANuxkgxpLJNM4NFi+VTInsh1vJ5Nc Pv/bEQT0utMCNsWyzcQaRH8oK0Z2YEwUWpTEw9r2Jf0iI1SPcnLiSzRqd5yD6cefBWii 87TT5tGpGJcWsGWB6kwdMsC/hjw4ev4zT67zKn1yD9CZbWb5r3dDRgbg+u7TcTwRETMU RXcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=HyZi4i2h3MjcAe8ui93Zy0Le6mb9DZJuyAuhhBalDgU=; fh=R8RMUK57IAu9IGOmI8o6wryn+S2bjZPh0maQR8VmU9M=; b=aaauCvUq+pFXMcmVCeNZNzbrd6jbVYYoXiigM5W/XC4V4Bn7g6aPIDLFTMUm0rJ/2w QrtGqU0rss4ASBFnUaglshaSFcSBaS97l4dtNviXgQ8cgUjKOtxXjwA4seWzuvpXggGz 4c7Pm8BhpBz2ViASPm1EK8ThU7QIPZc3IGjJK2lRPi/VwuPVI0BnUMJhF63iEkL7nbDc FkuruqCRqC46aCouKYbgJSRP+1FKtkP1fDTjwyC97+rbSTpneCYlf3nVt22xrV7ISQFb j2v9FR09OLj5oKchzT0FQ2/kPgu3m0TWOtVrzdVjHi+O3VfV+XhnwE0B5yWTHGN4ShD+ r1eA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fairphone.com header.s=fair header.b=Ipaq+TrH; spf=pass (google.com: domain of linux-kernel+bounces-22407-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22407-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=fairphone.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:20 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:11 +0100 Subject: [PATCH v2 4/4] arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240110-fp4-panel-v2-4-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787716956564827646 X-GMAIL-MSGID: 1787716956564827646 Add the description for the display panel found on this phone. Unfortunately the LCDB module on PM6150L isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 53 +++++++++++++++++++++++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 29008e155d62..b9f4b6be7da9 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1338,7 +1338,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index ade619805519..9a7d0448fb68 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -68,6 +68,14 @@ key-volume-up { }; }; + /* Dummy regulator until PM6150L has LCDB VSP/VSN support */ + lcdb_dummy: regulator-lcdb-dummy { + compatible = "regulator-fixed"; + regulator-name = "lcdb_dummy"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + }; + reserved-memory { /* * The rmtfs memory region in downstream is 'dynamically allocated' @@ -373,6 +381,14 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7225/fairphone4/a615_zap.mbn"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -404,6 +420,43 @@ &ipa { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l22a>; + status = "okay"; + + panel@0 { + compatible = "fairphone,fp4-hx83112a-djn", "himax,hx83112a"; + reg = <0>; + + backlight = <&pm6150l_wled>; + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply = <&vreg_l1e>; + vsn-supply = <&lcdb_dummy>; + vsp-supply = <&lcdb_dummy>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l18a>; + status = "okay"; +}; + &mpss { firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; status = "okay";