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[147.75.80.249]) by mx.google.com with ESMTPS id u16-20020a50a410000000b0055872d14a61si125965edb.434.2024.01.10.03.23.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 03:23:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-22075-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ereBSzNk; spf=pass (google.com: domain of linux-kernel+bounces-22075-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22075-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 3A81C1F2125E for ; Wed, 10 Jan 2024 11:23:12 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C031848780; Wed, 10 Jan 2024 11:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ereBSzNk" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 725F84776F; Wed, 10 Jan 2024 11:21:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40A8oMxM005978; Wed, 10 Jan 2024 11:21:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=0tgyZq56LbgeyLFmlrLBCFlUmFvbEsQ/fInNhqR0U8w=; b=er eBSzNkf7G8o3TkYX5F+4IcxujDmcvxlVE9sFKhD1o/WbAOC7IvZgUZH2LDcnL8En RqnPSCvRDwuOAp5oouv52Nwathf3JBCmTQ3twHX5nl6OCvy7n4uui5idTEDVzqsE dGxsdK5bcZSSmx0zp3TYbsFeFkjhQC0zQIVyHf6iWw18i2IX+v6GmBn/v7+EX3jZ +qB0IBYT+aze+eFWOpF4M8G5jbmhYi9oCVIaNJIHKdFiarxVm7JulzyId3XRuY98 y6i+K93lrGp1iFWSYCbA8c2MsJV/6ho2DxTTITS+OMOmz+mVhga+BNcGidRvzyGe 13MwKPAa1tj+sJmv8TlQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vh85t2cqy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:22 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40ABLLxs026578 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:21 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:16 -0800 From: Luo Jie To: , , , , CC: , , , , , , , , , , Subject: [PATCH 1/6] arm64: dts: qcom: ipq9574: Add PPE device tree node Date: Wed, 10 Jan 2024 19:20:54 +0800 Message-ID: <20240110112059.2498-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _Wp0J2wSiZfHeZTx6zxGf0qmZxNgMmhN X-Proofpoint-GUID: _Wp0J2wSiZfHeZTx6zxGf0qmZxNgMmhN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787702324985077353 X-GMAIL-MSGID: 1787702324985077353 The PPE device tree node includes the PPE initialization configurations and UNIPHY instance configuration. Ther are 3 UNIPHYs(PCS) on the platform ipq9574, which register the clock provider to output the clock for PPE port to work on the different link speed. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 730 +++++++++++++++++++++++++- 1 file changed, 724 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 810cda4a850f..5fa241e27c8b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -775,16 +775,734 @@ nsscc: nsscc@39b00000 { <&bias_pll_nss_noc_clk>, <&bias_pll_ubi_nc_clk>, <&gcc_gpll0_out_aux>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, + <&uniphys 0>, + <&uniphys 1>, + <&uniphys 2>, + <&uniphys 3>, + <&uniphys 4>, + <&uniphys 5>, <&xo_board_clk>; #clock-cells = <1>; #reset-cells = <1>; }; + + qcom_ppe: qcom-ppe@3a000000 { + compatible = "qcom,ipq9574-ppe"; + reg = <0x3a000000 0xb00000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_UNIPHY2_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY2_AHB_CLK>, + <&gcc GCC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_1_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>, + <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT3_MAC_CLK>, + <&nsscc NSS_CC_PORT4_MAC_CLK>, + <&nsscc NSS_CC_PORT5_MAC_CLK>, + <&nsscc NSS_CC_PORT6_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>, + <&nsscc NSS_CC_PORT3_RX_CLK>, + <&nsscc NSS_CC_PORT3_TX_CLK>, + <&nsscc NSS_CC_PORT4_RX_CLK>, + <&nsscc NSS_CC_PORT4_TX_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK>, + <&nsscc NSS_CC_PORT5_TX_CLK>, + <&nsscc NSS_CC_PORT6_RX_CLK>, + <&nsscc NSS_CC_PORT6_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK_SRC>, + <&nsscc NSS_CC_PORT5_TX_CLK_SRC>; + clock-names = "cmn_ahb", + "cmn_sys", + "uniphy0_sys", + "uniphy1_sys", + "uniphy2_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy2_ahb", + "gcc_nsscc", + "gcc_nssnoc_nsscc", + "gcc_nssnoc_snoc", + "gcc_nssnoc_snoc_1", + "nss_ppe", + "nss_ppe_cfg", + "nssnoc_ppe", + "nssnoc_ppe_cfg", + "nss_edma", + "nss_edma_cfg", + "nss_ppe_ipe", + "nss_ppe_btq", + "port1_mac", + "port2_mac", + "port3_mac", + "port4_mac", + "port5_mac", + "port6_mac", + "nss_port1_rx", + "nss_port1_tx", + "nss_port2_rx", + "nss_port2_tx", + "nss_port3_rx", + "nss_port3_tx", + "nss_port4_rx", + "nss_port4_tx", + "nss_port5_rx", + "nss_port5_tx", + "nss_port6_rx", + "nss_port6_tx", + "uniphy_port1_rx", + "uniphy_port1_tx", + "uniphy_port2_rx", + "uniphy_port2_tx", + "uniphy_port3_rx", + "uniphy_port3_tx", + "uniphy_port4_rx", + "uniphy_port4_tx", + "uniphy_port5_rx", + "uniphy_port5_tx", + "uniphy_port6_rx", + "uniphy_port6_tx", + "nss_port5_rx_clk_src", + "nss_port5_tx_clk_src"; + + resets = <&nsscc PPE_FULL_RESET>, + <&gcc GCC_UNIPHY0_SYS_RESET>, + <&gcc GCC_UNIPHY1_SYS_RESET>, + <&gcc GCC_UNIPHY2_SYS_RESET>, + <&gcc GCC_UNIPHY0_AHB_RESET>, + <&gcc GCC_UNIPHY1_AHB_RESET>, + <&gcc GCC_UNIPHY2_AHB_RESET>, + <&gcc GCC_UNIPHY0_XPCS_RESET>, + <&gcc GCC_UNIPHY1_XPCS_RESET>, + <&gcc GCC_UNIPHY2_XPCS_RESET>, + <&nsscc UNIPHY0_SOFT_RESET>, + <&nsscc UNIPHY_PORT5_ARES>, + <&nsscc UNIPHY_PORT6_ARES>, + <&nsscc UNIPHY_PORT1_ARES>, + <&nsscc UNIPHY_PORT2_ARES>, + <&nsscc UNIPHY_PORT3_ARES>, + <&nsscc UNIPHY_PORT4_ARES>, + <&nsscc NSSPORT1_RESET>, + <&nsscc NSSPORT2_RESET>, + <&nsscc NSSPORT3_RESET>, + <&nsscc NSSPORT4_RESET>, + <&nsscc NSSPORT5_RESET>, + <&nsscc NSSPORT6_RESET>, + <&nsscc PORT1_MAC_ARES>, + <&nsscc PORT2_MAC_ARES>, + <&nsscc PORT3_MAC_ARES>, + <&nsscc PORT4_MAC_ARES>, + <&nsscc PORT5_MAC_ARES>, + <&nsscc PORT6_MAC_ARES>; + reset-names = "ppe", + "uniphy0_sys", + "uniphy1_sys", + "uniphy2_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy2_ahb", + "uniphy0_xpcs", + "uniphy1_xpcs", + "uniphy2_xpcs", + "uniphy0_soft", + "uniphy1_soft", + "uniphy2_soft", + "uniphy0_port1_dis", + "uniphy0_port2_dis", + "uniphy0_port3_dis", + "uniphy0_port4_dis", + "nss_port1", + "nss_port2", + "nss_port3", + "nss_port4", + "nss_port5", + "nss_port6", + "nss_port1_mac", + "nss_port2_mac", + "nss_port3_mac", + "nss_port4_mac", + "nss_port5_mac", + "nss_port6_mac"; + + uniphys: qcom-uniphy@7a00000 { + reg = <0x7a00000 0x10000>, + <0x7a10000 0x10000>, + <0x7a20000 0x10000>; + #clock-cells = <0x1>; + clock-output-names = "uniphy0_gcc_rx_clk", + "uniphy0_gcc_tx_clk", + "uniphy1_gcc_rx_clk", + "uniphy1_gcc_tx_clk", + "uniphy2_gcc_rx_clk", + "uniphy2_gcc_tx_clk"; + }; + + tdm-config { + /* + * qcom,tdm-bm-config = ; + */ + qcom,tdm-bm-config = <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 3 0 0>, + <1 1 3 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 4 0 0>, + <1 1 4 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 3 0 0>, + <1 1 3 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 4 0 0>, + <1 1 4 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>; + + /* + * qcom,tdm-port-scheduler-config = ; + */ + qcom,tdm-port-scheduler-config = <0x98 6 0 1 1>, + <0x94 5 6 1 3>, + <0x86 0 5 1 4>, + <0x8C 1 6 1 0>, + <0x1C 7 5 1 1>, + <0x98 2 6 1 0>, + <0x1C 5 7 1 1>, + <0x34 3 6 1 0>, + <0x8C 4 5 1 1>, + <0x98 2 6 1 0>, + <0x8C 5 4 1 1>, + <0xA8 0 6 1 2>, + <0x98 5 1 1 0>, + <0x98 6 5 1 2>, + <0x89 1 6 1 4>, + <0xA4 3 0 1 1>, + <0x8C 5 6 1 4>, + <0xA8 0 2 1 1>, + <0x98 6 5 1 0>, + <0xC4 4 3 1 1>, + <0x94 6 5 1 0>, + <0x1C 7 6 1 1>, + <0x98 2 5 1 0>, + <0x1C 6 7 1 1>, + <0x1C 5 6 1 0>, + <0x94 3 5 1 1>, + <0x8C 4 6 1 0>, + <0x94 1 5 1 3>, + <0x94 6 1 1 0>, + <0xD0 3 5 1 2>, + <0x98 6 0 1 1>, + <0x94 5 6 1 3>, + <0x94 1 5 1 0>, + <0x98 2 6 1 1>, + <0x8C 4 5 1 0>, + <0x1C 7 6 1 1>, + <0x8C 0 5 1 4>, + <0x89 1 6 1 2>, + <0x98 5 0 1 1>, + <0x94 6 5 1 3>, + <0x92 0 6 1 2>, + <0x98 1 5 1 0>, + <0x98 6 2 1 1>, + <0xD0 0 5 1 3>, + <0x94 6 0 1 1>, + <0x8C 5 6 1 4>, + <0x8C 1 5 1 0>, + <0x1C 6 7 1 1>, + <0x1C 5 6 1 0>, + <0xB0 2 3 1 1>, + <0xC4 4 5 1 0>, + <0x8C 6 4 1 1>, + <0xA4 3 6 1 0>, + <0x1C 5 7 1 1>, + <0x4C 0 5 1 4>, + <0x8C 6 0 1 1>, + <0x34 7 6 1 3>, + <0x94 5 0 1 1>, + <0x98 6 5 1 2>; + }; + + buffer-management-config { + /* qcom,group-config = ; */ + qcom,group-config = <0 1550>; + /* + * qcom,port-config = ; + */ + qcom,port-config = <0 0 0 100 1146 7 8 0 1>, + <0 1 0 100 250 4 36 0 1>, + <0 2 0 100 250 4 36 0 1>, + <0 3 0 100 250 4 36 0 1>, + <0 4 0 100 250 4 36 0 1>, + <0 5 0 100 250 4 36 0 1>, + <0 6 0 100 250 4 36 0 1>, + <0 7 0 100 250 4 36 0 1>, + <0 8 0 128 250 4 36 0 1>, + <0 9 0 128 250 4 36 0 1>, + <0 10 0 128 250 4 36 0 1>, + <0 11 0 128 250 4 36 0 1>, + <0 12 0 128 250 4 36 0 1>, + <0 13 0 128 250 4 36 0 1>, + <0 14 0 40 250 4 36 0 1>; + }; + + queue-management-config { + /* + * qcom,group-config = ; + */ + qcom,group-config = <0 2000 0 0 0>; + /* + * qcom,queue-config = ; + */ + qcom,queue-config = <0 256 0 0 400 4 36 1>, + <256 44 0 0 250 0 36 0>; + }; + + port-scheduler-resource { + port0 { + port-id = <0>; + qcom,ucast-queue = <0 63>; + qcom,mcast-queue = <256 263>; + qcom,l0sp = <0 0>; + qcom,l0cdrr = <0 7>; + qcom,l0edrr = <0 7>; + qcom,l1cdrr = <0 0>; + qcom,l1edrr = <0 0>; + }; + + port1 { + port-id = <1>; + qcom,ucast-queue = <204 211>; + qcom,mcast-queue = <272 275>; + qcom,l0sp = <51 52>; + qcom,l0cdrr = <108 115>; + qcom,l0edrr = <108 115>; + qcom,l1cdrr = <23 24>; + qcom,l1edrr = <23 24>; + }; + + port2 { + port-id = <2>; + qcom,ucast-queue = <212 219>; + qcom,mcast-queue = <276 279>; + qcom,l0sp = <53 54>; + qcom,l0cdrr = <116 123>; + qcom,l0edrr = <116 123>; + qcom,l1cdrr = <25 26>; + qcom,l1edrr = <25 26>; + }; + + port3 { + port-id = <3>; + qcom,ucast-queue = <220 227>; + qcom,mcast-queue = <280 283>; + qcom,l0sp = <55 56>; + qcom,l0cdrr = <124 131>; + qcom,l0edrr = <124 131>; + qcom,l1cdrr = <27 28>; + qcom,l1edrr = <27 28>; + }; + + port4 { + port-id = <4>; + qcom,ucast-queue = <228 235>; + qcom,mcast-queue = <284 287>; + qcom,l0sp = <57 58>; + qcom,l0cdrr = <132 139>; + qcom,l0edrr = <132 139>; + qcom,l1cdrr = <29 30>; + qcom,l1edrr = <29 30>; + }; + + port5 { + port-id = <5>; + qcom,ucast-queue = <236 243>; + qcom,mcast-queue = <288 291>; + qcom,l0sp = <59 60>; + qcom,l0cdrr = <140 147>; + qcom,l0edrr = <140 147>; + qcom,l1cdrr = <31 32>; + qcom,l1edrr = <31 32>; + }; + + port6 { + port-id = <6>; + qcom,ucast-queue = <244 251>; + qcom,mcast-queue = <292 295>; + qcom,l0sp = <61 62>; + qcom,l0cdrr = <148 155>; + qcom,l0edrr = <148 155>; + qcom,l1cdrr = <33 34>; + qcom,l1edrr = <33 34>; + }; + + port7 { + port-id = <7>; + qcom,ucast-queue = <252 255>; + qcom,mcast-queue = <296 299>; + qcom,l0sp = <63 63>; + qcom,l0cdrr = <156 159>; + qcom,l0edrr = <156 159>; + qcom,l1cdrr = <35 35>; + qcom,l1edrr = <35 35>; + }; + }; + + port-scheduler-config { + port0 { + port-id = <0>; + l1scheduler { + group0 { + /* flow ID from L0 SP */ + qcom,flow = <0>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + + l0scheduler { + group0 { + /* unicast queue */ + qcom,ucast-queue = <0>; + qcom,ucast-loop-priority = <8>; + /* multicast queue */ + qcom,mcast-queue = <256>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group1 { + qcom,ucast-queue = <8>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <257>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group2 { + qcom,ucast-queue = <16>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <258>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group3 { + qcom,ucast-queue = <24>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <259>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group4 { + qcom,ucast-queue = <32>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <260>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group5 { + qcom,ucast-queue = <40>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <261>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group6 { + qcom,ucast-queue = <48>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <262>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group7 { + qcom,ucast-queue = <56>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <263>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + }; + + port1 { + port-id = <1>; + l1scheduler { + group0 { + qcom,flow = <51>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <1 0 23 0 23>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <204>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <272>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <51 0 108 0 108>; + }; + }; + }; + + port2 { + port-id = <2>; + l1scheduler { + group0 { + qcom,flow = <53>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <2 0 25 0 25>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <212>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <276>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <53 0 116 0 116>; + }; + }; + }; + + port3 { + port-id = <3>; + l1scheduler { + group0 { + qcom,flow = <55>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <3 0 27 0 27>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <220>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <280>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <55 0 124 0 124>; + }; + }; + }; + + port4 { + port-id = <4>; + l1scheduler { + group0 { + qcom,flow = <57>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <4 0 29 0 29>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <228>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <284>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <57 0 132 0 132>; + }; + }; + }; + + port5 { + port-id = <5>; + l1scheduler { + group0 { + qcom,flow = <59>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <5 0 31 0 31>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <236>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <288>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <59 0 140 0 140>; + }; + }; + }; + + port6 { + port-id = <6>; + l1scheduler { + group0 { + qcom,flow = <61>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <6 0 33 0 33>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <244>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <292>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <61 0 148 0 148>; + }; + }; + }; + + port7 { + port-id = <7>; + l1scheduler { + group0 { + qcom,flow = <63>; + qcom,scheduler-config = <7 0 35 0 35>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <252>; + qcom,ucast-loop-priority = <4>; + qcom,mcast-queue = <296>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <63 0 156 0 156>; + }; + }; + }; + }; + }; }; thermal-zones { From patchwork Wed Jan 10 11:20:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 186814 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp724884dyi; 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There are two UNIPHYs in ipq5332 platform, which provide the root clock to the PPE port to work on the different link speed. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 370 +++++++++++++++++++++++++- 1 file changed, 366 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index a1504f6c40c1..bc89480820cb 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include / { @@ -492,15 +493,376 @@ nsscc: clock-controller@39b00000{ clocks = <&cmn_pll_nss_200m_clk>, <&cmn_pll_nss_300m_clk>, <&gcc GPLL0_OUT_AUX>, - <0>, - <0>, - <0>, - <0>, + <&uniphys 0>, + <&uniphys 1>, + <&uniphys 2>, + <&uniphys 3>, <&xo_board>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; + + qcom_ppe: qcom-ppe@3a000000 { + compatible = "qcom,ipq5332-ppe"; + reg = <0x3a000000 0xb00000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_1_CLK>, + <&gcc GCC_IM_SLEEP_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>, + <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>; + clock-names = "cmn_ahb", + "cmn_sys", + "uniphy0_sys", + "uniphy1_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "gcc_nsscc", + "gcc_nssnoc_snoc", + "gcc_nssnoc_snoc_1", + "gcc_im_sleep", + "nss_ppe", + "nss_ppe_cfg", + "nssnoc_ppe", + "nssnoc_ppe_cfg", + "nss_edma", + "nss_edma_cfg", + "nss_ppe_ipe", + "nss_ppe_btq", + "port1_mac", + "port2_mac", + "nss_port1_rx", + "nss_port1_tx", + "nss_port2_rx", + "nss_port2_tx", + "uniphy_port1_rx", + "uniphy_port1_tx", + "uniphy_port2_rx", + "uniphy_port2_tx"; + + resets = <&nsscc NSS_CC_PPE_BCR>, + <&gcc GCC_UNIPHY0_SYS_CLK_ARES>, + <&gcc GCC_UNIPHY1_SYS_CLK_ARES>, + <&gcc GCC_UNIPHY0_AHB_CLK_ARES>, + <&gcc GCC_UNIPHY1_AHB_CLK_ARES>, + <&gcc GCC_UNIPHY0_XPCS_ARES>, + <&gcc GCC_UNIPHY1_XPCS_ARES>, + <&gcc GCC_UNIPHY0_BCR>, + <&gcc GCC_UNIPHY1_BCR>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_RX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT2_RX_CLK_ARES>, + <&nsscc NSS_CC_PORT2_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_MAC_CLK_ARES>, + <&nsscc NSS_CC_PORT2_MAC_CLK_ARES>; + reset-names = "ppe", + "uniphy0_sys", + "uniphy1_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy0_xpcs", + "uniphy1_xpcs", + "uniphy0_soft", + "uniphy1_soft", + "uniphy_port1_rx", + "uniphy_port1_tx", + "uniphy_port2_rx", + "uniphy_port2_tx", + "nss_port1_rx", + "nss_port1_tx", + "nss_port2_rx", + "nss_port2_tx", + "nss_port1_mac", + "nss_port2_mac"; + + uniphys: qcom-uniphy@7a00000 { + reg = <0x7a00000 0x10000>, + <0x7a10000 0x10000>; + #clock-cells = <0x1>; + clock-output-names = "uniphy0_gcc_rx_clk", + "uniphy0_gcc_tx_clk", + "uniphy1_gcc_rx_clk", + "uniphy1_gcc_tx_clk"; + }; + + tdm-config { + /* + * qcom,tdm-bm-config = + * ; + */ + qcom,tdm-bm-config = <1 0 2 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 2 0 0>, + <1 1 1 0 0>, + <1 0 1 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 1 0 0>, + <1 1 0 0 0>, + <1 0 2 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 2 0 0>, + <1 0 2 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 2 0 0>, + <1 0 1 0 0>, + <0 0 0 0 0>; + + /* + * qcom,tdm-port-scheduler-config = + * ; + */ + qcom,tdm-port-scheduler-config = <0x0 2 0 0 0>, + <0x0 1 2 0 0>, + <0x0 0 1 0 0>, + <0x0 0 2 0 0>, + <0x0 1 0 0 0>, + <0x0 2 1 0 0>, + <0x0 0 2 0 0>, + <0x0 0 1 0 0>, + <0x0 0 2 0 0>, + <0x0 0 1 0 0>; + }; + + buffer-management-config { + /* qcom,group-config = ; */ + qcom,group-config = <0 240>; + /* + * qcom,port-config = + * ; + */ + qcom,port-config = <0 0 12 40 30 7 5 20 1>, + <0 1 12 40 30 7 5 20 1>, + <0 2 12 40 30 7 5 20 1>, + <0 3 12 40 30 7 5 20 1>, + <0 4 12 40 30 7 5 20 1>, + <0 5 12 40 30 7 5 20 1>, + <0 6 12 40 30 7 5 20 1>, + <0 7 12 40 30 7 5 20 1>, + <0 8 12 128 48 7 5 20 1>, + <0 9 12 128 48 7 5 20 1>; + }; + + queue-management-config { + /* + * qcom,group-config = + * ; + */ + qcom,group-config = <0 500 0 0 0>; + /* + * qcom,queue-config = + * ; + */ + qcom,queue-config = <0 256 0 0 50 5 18 1>, + <256 44 0 0 50 0 18 0>; + }; + + port-scheduler-resource { + port0 { + port-id = <0>; + qcom,ucast-queue = <0 63>; + qcom,mcast-queue = <256 263>; + qcom,l0sp = <0 0>; + qcom,l0cdrr = <0 7>; + qcom,l0edrr = <0 7>; + qcom,l1cdrr = <0 0>; + qcom,l1edrr = <0 0>; + }; + + port1 { + port-id = <1>; + qcom,ucast-queue = <204 211>; + qcom,mcast-queue = <272 275>; + qcom,l0sp = <51 52>; + qcom,l0cdrr = <108 115>; + qcom,l0edrr = <108 115>; + qcom,l1cdrr = <23 24>; + qcom,l1edrr = <23 24>; + }; + + port2 { + port-id = <2>; + qcom,ucast-queue = <212 219>; + qcom,mcast-queue = <276 279>; + qcom,l0sp = <53 54>; + qcom,l0cdrr = <116 123>; + qcom,l0edrr = <116 123>; + qcom,l1cdrr = <25 26>; + qcom,l1edrr = <25 26>; + }; + }; + + port-scheduler-config { + port0 { + port-id = <0>; + l1scheduler { + group0 { + /* flow ID from L0 SP */ + qcom,flow = <0>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + + l0scheduler { + group0 { + /* unicast queue */ + qcom,ucast-queue = <0>; + qcom,ucast-loop-priority = <8>; + /* multicast queue */ + qcom,mcast-queue = <256>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group1 { + qcom,ucast-queue = <8>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <257>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group2 { + qcom,ucast-queue = <16>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <258>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group3 { + qcom,ucast-queue = <24>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <259>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group4 { + qcom,ucast-queue = <32>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <260>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group5 { + qcom,ucast-queue = <40>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <261>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group6 { + qcom,ucast-queue = <48>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <262>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group7 { + qcom,ucast-queue = <56>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <263>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + }; + + port1 { + port-id = <1>; + l1scheduler { + group0 { + qcom,flow = <51>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <1 0 23 0 23>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <204>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <272>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <51 0 108 0 108>; + }; + }; + }; + + port2 { + port-id = <2>; + l1scheduler { + group0 { + qcom,flow = <53>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <2 0 25 0 25>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <212>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <276>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <53 0 116 0 116>; + }; + }; + }; + }; + }; }; timer { From patchwork Wed Jan 10 11:20:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 186815 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp724970dyi; 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Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index bc89480820cb..e6c780e69d6e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -214,6 +214,38 @@ serial_0_pins: serial0-state { drive-strength = <8>; bias-pull-up; }; + + mdio0_pins: mdio0-state { + mux_0 { + pins = "gpio25"; + function = "mdc0"; + drive-strength = <8>; + bias-disable; + }; + + mux_1 { + pins = "gpio26"; + function = "mdio0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + mdio1_pins: mdio1-state { + mux_0 { + pins = "gpio27"; + function = "mdc1"; + drive-strength = <8>; + bias-disable; + }; + + mux_1 { + pins = "gpio28"; + function = "mdio1"; + drive-strength = <8>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -863,6 +895,18 @@ group0 { }; }; }; + + mdio: mdio@90000 { + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + pinctrl-0 = <&mdio1_pins &mdio0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; }; timer { From patchwork Wed Jan 10 11:20:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 186817 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp725148dyi; Wed, 10 Jan 2024 03:24:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgipUduMGlXVjIjtfn6879i5sylOCN+oZy3D0/H6uHdOuCK9KUtKtSp2WdqKtwBYecKb0o X-Received: by 2002:a50:9b14:0:b0:557:3c34:5c0c with SMTP id o20-20020a509b14000000b005573c345c0cmr382886edi.40.1704885844593; Wed, 10 Jan 2024 03:24:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704885844; cv=none; d=google.com; s=arc-20160816; b=aNRQ69QNaHCspbTDTymS5mTEcG+82O0bipkNGdt/WocT/8tHMLJ8Y/09TuvybKKhpq dHZG9WzfrfhhxBzZ1PXguQPjbxp0zVsfkpCs3ocL/AoXM17uwVdYLHt20eUJvEHBcj1w s+K61oDHmieGLeSW+sgRwXkTwrXFdDbCnay0Sn498J+1zCB/va3oNjcCYMNfugp17CVj C1NEcH94fyNGQ/Ua0u0e/+qQZQ4eEUgV3500YkZbGX/43HQ9znDislcU4gwaMJhpGkAC 8UuzxmgcDrAFvOusow9TWhlV22ncURLSV0tGWqR4suoxodsLSwtFbOEVl+3ZfS8tl+Sw +JIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QrQjWGCp/5SioZxztmEdNb7eZ3tjnjFQYAo0wxrKtZ4=; fh=I55x0ANvNkX2tDYcOPVTN40IQtoD9tfE/hZORnK+Rnk=; b=u3nGMa8q0TMaKKEE2VJSijlbF38A14i+H7kKcVbhqfWlt72J3MDnyuNyfrCq9VQSZH O8NOK4k0NwlDQS50LB7I/LZVZ3flvchuXrXmmuiNUPh2b8CaxZgZSdoMrdmlbbSY9di4 Zpt0Fftr0P0jKYUQgQ3JH88QlnYqJNkaNOjSq+cV4bRjh+fnal+mZJbak6acK4n945rE v9DSeFvodiasSUSilwzEhB7zu9E5+1LgA0VGi72dQOY8JybJiGB57PoSRmu01DdoW+MI Hbqvim8ra5XWAKNyS9FPqN0SiIAxhzOYTCh4seSNzWK1og+WmBq5K9rep2m9+CUE5b7i WbDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=CjalYQod; spf=pass (google.com: domain of linux-kernel+bounces-22079-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22079-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5fa241e27c8b..cf21ce9bf756 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -316,6 +316,22 @@ uart2_pins: uart2-state { drive-strength = <8>; bias-disable; }; + + mdio_pins: mdio-state { + mux_0 { + pins = "gpio38"; + function = "mdc"; + drive-strength = <8>; + bias-disable; + }; + + mux_1 { + pins = "gpio39"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1503,6 +1519,18 @@ group0 { }; }; }; + + mdio: mdio@90000 { + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; }; thermal-zones { From patchwork Wed Jan 10 11:20:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 186818 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp725295dyi; Wed, 10 Jan 2024 03:24:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHR9VvKCfILK7g8dVa1Y39AklCwtjxnMunYgZEbFVwK8yzLGgL2csWOx1Sc4KaiyS8HF9DB X-Received: by 2002:a05:622a:261b:b0:429:aff8:7d0b with SMTP id ci27-20020a05622a261b00b00429aff87d0bmr1110240qtb.110.1704885864418; Wed, 10 Jan 2024 03:24:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704885864; cv=none; d=google.com; s=arc-20160816; b=L2yq6CUyOv+1CSpdZzNm2SDe5ZliI6yKRbYZXL/3lcDiFOlnIo7YZCxI/oIv1+vSih jafn44Q2E/yu2O/WSFFZCjSMNWl01jK8FChITLiFfS8z7RitJN3GQisRXaSnLKhswAbO LFYDm3J2XQ9fjirk272bjSypFpiuzqOtpIzQiBSpOK3Ktn2tFoYYGpZOfZgMn8ZQwU8d /w4MMSZBxOLu84SJY7hp2g2d9sVvCik0vaZ7o0tdzQTIT937Ey4nEE9od146Wz9Ejy/K bRQ15UzC/Sm7pATFiqX0dHISjsOONx5LSoeI7aAy2c9LTz5iy4Te+vHTgGhg0KrWyiaU MJuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=d37+e83tZwogOPVrwPm8SdeiQJvavFXD5ROs6vq+SHY=; fh=I55x0ANvNkX2tDYcOPVTN40IQtoD9tfE/hZORnK+Rnk=; b=In9L4v+WcJxjNRhpVxgIP67LeKZot1bicS+dnIj8nL/2cRYBIHRYiLIW2j1HwAivZS tT9VNjqJWjBKkRdx8TsqkM146KsGB4SHxtkZy0JbxdU7VLbpWx8yePqDEMdUQvXNkbPL SdOHkduFfOShd8oLufxsRV2kKq80KAqdqJOQVxZA/QCyzx2/E/ovOsvHSFoPEiXnKsOK grflF4NP0w1ZPm7Xc+kpr7mb/PowSzKHFAaykqrlZxtQqXB1FcIkzF469k4ch5wSirXp b8HZrXmUjQZ9BVfee2RWLSVpxZqrDjlEp4ul7cl4dgbqd0CMFXVlX3JgXvK+oAkG4hqR yilQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DihKeHFo; spf=pass (google.com: domain of linux-kernel+bounces-22080-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22080-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Lei Wei Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..d51968e9d601 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -12,6 +12,15 @@ / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + soc@0 { + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&blsp1_i2c1>; + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; + }; + }; }; &blsp1_i2c1 { @@ -63,3 +72,45 @@ data-pins { }; }; }; + +&qcom_ppe { + qcom,port_phyinfo { + ppe_port0: port@0 { + port_id = <1>; + phy-mode = "2500base-x"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + ppe_port1: port@1 { + port_id = <2>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + }; +}; + +&mdio { + status = "okay"; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + + phy0: ethernet-phy@0 { + reg = <1>; + }; + + phy1: ethernet-phy@1 { + reg = <2>; + }; + + phy2: ethernet-phy@2 { + reg = <3>; + }; + + phy3: ethernet-phy@3 { + reg = <4>; + }; +}; From patchwork Wed Jan 10 11:20:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 186819 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp725454dyi; Wed, 10 Jan 2024 03:24:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IFNonD/EOH4yYgQ7r1iiJPZvNyPz3KI9LrD9Cb2BVuk4E+kJMO2Zm7jd11aRuIu73y0LqoE X-Received: by 2002:a17:903:22c3:b0:1d3:5fc4:f4cc with SMTP id y3-20020a17090322c300b001d35fc4f4ccmr909422plg.29.1704885885833; Wed, 10 Jan 2024 03:24:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704885885; cv=none; d=google.com; s=arc-20160816; b=TEG0zLQtlElVA8SCvTpYhd+ODVlE7kNs1WuOZ/NJLkoe0NwmmZSxwU0N8BO4j5DAVN imAOsUm1BI8etXoKpsIyc1i35t+xdZXJGxGqXedeRkM/HlZgImWwGWguvnU+8GZhzocg NMSLsiowxqsUdxjhM9lg3sePUPEOuSnBiPbtg8FLxU9wfelroDugHImAtxqsJWcTYDwI pfao9VCvX5U8DURDaIsj1uDbZNsJN/7HtSlzkslzhwR+/p/8T+Khbg992QHZaHTt/rEa f7PlBFQWelWnovOiT7D9anscC0lGm3zarXgDu93UuH/zvSYpdrzpUNgNou8iKyAN3e+U fT3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=6qhSHiLUEMIZqqtuODQqyRrpU7sCEv0dSwFH8nc3DCI=; fh=I55x0ANvNkX2tDYcOPVTN40IQtoD9tfE/hZORnK+Rnk=; b=FY1GyuGHoKGV9ABquk6rWE2dMzGL5F1wtBPHOQSvQ0Ra1PSQW2TmqYuQStEZ+Wf5tw hAblt5aM4Qi9qU9FfvCcn2o0w0ILGJjG/irlGeNzro27LDKytGnX7FvOSA9xJ3/czIVG HE1aDFmqfrCT7bKZmU6dlXsrhwkG87jFccPS7ixRgQBX0DVIA2IA8JJeKSq9m+FQg7qf 9LtDomFNNWhGM1LQXdWhX8H5bckAbEBM6Ki5476jKc0xtglD5Lr2DEfke2F0xU30tQ3w jxdPgzEdwnziu8544rBrfgwJNSvdWL9UTML4sT+dtNhKZylhBRuW/EXj7u5jlD8EVYKT VerA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hT9KKwT9; spf=pass (google.com: domain of linux-kernel+bounces-22081-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22081-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Lei Wei Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 66 +++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 1bb8d96c9a82..298c0853b4d2 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -60,3 +60,69 @@ rclk-pins { }; }; }; + +&qcom_ppe { + qcom,port_phyinfo { + ppe_port0: port@0 { + port_id = <1>; + phy-mode = "qsgmii"; + phy-handle = <&phy0>; + }; + ppe_port1: port@1 { + port_id = <2>; + phy-mode = "qsgmii"; + phy-handle = <&phy1>; + }; + ppe_port2: port@2 { + port_id = <3>; + phy-mode = "qsgmii"; + phy-handle = <&phy2>; + }; + ppe_port3: port@3 { + port_id = <4>; + phy-mode = "qsgmii"; + phy-handle = <&phy3>; + }; + ppe_port4: port@4 { + port_id = <5>; + phy-mode = "usxgmii"; + phy-handle = <&phy4>; + }; + ppe_port5: port@5 { + port_id = <6>; + phy-mode = "usxgmii"; + phy-handle = <&phy5>; + }; + }; +}; + +&mdio { + reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; + + phy4: ethernet-phy@4 { + compatible ="ethernet-phy-ieee802.3-c45"; + reg = <8>; + }; + + phy5: ethernet-phy@5 { + compatible ="ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; +};