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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hugues Fruchet --- .../media/st,stm32mp25-video-codec.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml new file mode 100644 index 000000000000..b8611bc8756c --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder + +maintainers: + - Hugues Fruchet + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware + decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1) + and a VENC video hardware encoder peripheral based on Verisilicon + VC8000NanoE IP (former Hantro H1). + +properties: + compatible: + enum: + - st,stm32mp25-vdec + - st,stm32mp25-venc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + video-codec@580d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x580d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + }; From patchwork Wed Jan 10 10:46:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 186784 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp708730dyi; Wed, 10 Jan 2024 02:49:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IE4vRktwKUDuMIHuQa0UTsBO7hkPA9W4F8tZWIg9CZrIx5bvCDSg1NBzzppIoOKsAEdmLd5 X-Received: by 2002:a17:90b:b14:b0:28b:3335:1489 with SMTP id bf20-20020a17090b0b1400b0028b33351489mr419836pjb.99.1704883774538; Wed, 10 Jan 2024 02:49:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704883774; cv=none; d=google.com; s=arc-20160816; b=bGMdidb8zsE50GrxNSK7rvEaCw2HhaKzWeF0K58m1NnjRQMlbo0RepVpu6DfZvNE8N eFTi7YvYtnXcGPXBDPUMvFLsnTmB8UO6LEYmLZ2GJX3Z87Lv0iBKWfxAeaCXVZL1XAH4 nxCpPXzZypBnLeOqVHFIfdMfz/drDPWc8g1H8iypL0Ni10/tTxvYZVwiHBW7FfrzTXms zQErS+vY3/FHWc6djLetphNzGNju5RO82hGV/dg3VF1nDuyuOmcrsnhoEG+kGQvz6k1v JnK7jWaSXQGxm7sdsXfFu9I++WhsiIg4zbEkh+vMBWKaW3EE7QzO8eGYyqTwlElkw8lI T7lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=bKDY4JqLAfcTateE5N/zYQ2tWG6qV9HCBIu52pV908A=; fh=ErwLDw9+98Mb4Q3i5RoHr7UOS7Ns3CK5YbB+qheGbUs=; b=VMYQUZuCZTiaWLVzJCa5z1aXLJxifnChVdcmuT+o7xeCrkojxTtHNIfMQimnjBzJIf /eyLK8gIU4Es8UQrcXybRsu+plRxYZwrzAvOW42MzBAa3W+YpAk2mIeY61KHUH+9o5J6 vj1VClvNCmCZAQFeBEGfRnvp6WHbX20IESUn8rp/x8zXAiqI11SCSS5ZiA+l3X+VYK+r mgpV2or8QEUfXGVq3d5aSFzgatAQmBuGte8Q8WlBBBsGlhbOW+nA/lMsXGWeGbol1tTG GRxVqw6rNxn8O8tyYKazbUZaW7rnkgWFAnUBtXIZtA+7FDvtfe4CQAeI+uIVmammmz9G m+CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=5pp79yS2; spf=pass (google.com: domain of linux-kernel+bounces-22011-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22011-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Support of H264/VP8 decoding. No post-processor support. VDEC has its own reset/clock/irq. Successfully tested up to full HD. Reviewed-by: Nicolas Dufresne Signed-off-by: Hugues Fruchet --- drivers/media/platform/verisilicon/Kconfig | 14 ++- drivers/media/platform/verisilicon/Makefile | 3 + .../media/platform/verisilicon/hantro_drv.c | 3 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_vpu_hw.c | 96 +++++++++++++++++++ 5 files changed, 114 insertions(+), 3 deletions(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c diff --git a/drivers/media/platform/verisilicon/Kconfig b/drivers/media/platform/verisilicon/Kconfig index 24b927d8f182..9a34d14c6e40 100644 --- a/drivers/media/platform/verisilicon/Kconfig +++ b/drivers/media/platform/verisilicon/Kconfig @@ -4,7 +4,7 @@ comment "Verisilicon media platform drivers" config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || ARCH_STM32 || COMPILE_TEST depends on V4L_MEM2MEM_DRIVERS depends on VIDEO_DEV select MEDIA_CONTROLLER @@ -15,8 +15,8 @@ config VIDEO_HANTRO select V4L2_VP9 help Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image - encoding and decoding. + Rockchip, NXP i.MX8M and STM32MP25 SoCs, which accelerate video + and image encoding and decoding. To compile this driver as a module, choose M here: the module will be called hantro-vpu. @@ -51,3 +51,11 @@ config VIDEO_HANTRO_SUNXI default y help Enable support for H6 SoC. + +config VIDEO_HANTRO_STM32MP25 + bool "Hantro STM32MP25 support" + depends on VIDEO_HANTRO + depends on ARCH_STM32 || COMPILE_TEST + default y + help + Enable support for STM32MP25 SoCs. diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/platform/verisilicon/Makefile index 6ad2ef885920..eb38a1833b02 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -39,3 +39,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ sunxi_vpu_hw.o + +hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \ + stm32mp25_vpu_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index db3df6cc4513..fe8e2240324c 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -735,6 +735,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_SUNXI { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_STM32MP25 + { .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index 9aec8a79acdc..0b4806f67630 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -408,6 +408,7 @@ extern const struct hantro_variant rk3568_vpu_variant; extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; +extern const struct hantro_variant stm32mp25_vdec_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c new file mode 100644 index 000000000000..6af6edcb6650 --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 video codec driver + * + * Copyright (C) STMicroelectronics SA 2024 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include "hantro.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_vdec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_VP8_FRAME, + .codec_mode = HANTRO_MODE_VP8_DEC, + .max_depth = 2, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] = { + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .reset = hantro_g1_reset, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .reset = hantro_g1_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + +/* + * Variants. + */ + +static const struct hantro_irq stm32mp25_vdec_irqs[] = { + { "vdec", hantro_g1_irq }, +}; + +static const char * const stm32mp25_vdec_clk_names[] = { "vdec-clk" }; + +const struct hantro_variant stm32mp25_vdec_variant = { + .dec_fmts = stm32mp25_vdec_fmts, + .num_dec_fmts = ARRAY_SIZE(stm32mp25_vdec_fmts), + .codec = HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops = stm32mp25_vdec_codec_ops, + .irqs = stm32mp25_vdec_irqs, + .num_irqs = ARRAY_SIZE(stm32mp25_vdec_irqs), + .clk_names = stm32mp25_vdec_clk_names, + .num_clocks = ARRAY_SIZE(stm32mp25_vdec_clk_names), +}; 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Support of JPEG encoding. VENC has its own reset/clock/irq. Reviewed-by: Nicolas Dufresne Signed-off-by: Hugues Fruchet --- .../media/platform/verisilicon/hantro_drv.c | 1 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_vpu_hw.c | 90 +++++++++++++++++++ 3 files changed, 92 insertions(+) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index fe8e2240324c..34b123dafd89 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -738,6 +738,7 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_STM32MP25 { .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, }, + { .compatible = "st,stm32mp25-venc", .data = &stm32mp25_venc_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index 0b4806f67630..7737320cc8cc 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -409,6 +409,7 @@ extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_variant stm32mp25_vdec_variant; +extern const struct hantro_variant stm32mp25_venc_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c index 6af6edcb6650..833821120b20 100644 --- a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c +++ b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c @@ -9,6 +9,8 @@ */ #include "hantro.h" +#include "hantro_jpeg.h" +#include "hantro_h1_regs.h" /* * Supported formats. @@ -55,6 +57,67 @@ static const struct hantro_fmt stm32mp25_vdec_fmts[] = { }, }; +static const struct hantro_fmt stm32mp25_venc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P, + }, + { + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422, + }, + { + .fourcc = V4L2_PIX_FMT_JPEG, + .codec_mode = HANTRO_MODE_JPEG_ENC, + .max_depth = 2, + .header_size = JPEG_HEADER_SIZE, + .frmsize = { + .min_width = 96, + .max_width = FMT_4K_WIDTH, + .step_width = MB_DIM, + .min_height = 96, + .max_height = FMT_4K_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + +static irqreturn_t stm32mp25_venc_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vepu_read(vpu, H1_REG_INTERRUPT); + state = (status & H1_REG_INTERRUPT_FRAME_RDY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +static void stm32mp25_venc_reset(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + + reset_control_reset(vpu->resets); +} + /* * Supported codec ops. */ @@ -74,6 +137,14 @@ static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] = { }, }; +static const struct hantro_codec_ops stm32mp25_venc_codec_ops[] = { + [HANTRO_MODE_JPEG_ENC] = { + .run = hantro_h1_jpeg_enc_run, + .reset = stm32mp25_venc_reset, + .done = hantro_h1_jpeg_enc_done, + }, +}; + /* * Variants. */ @@ -94,3 +165,22 @@ const struct hantro_variant stm32mp25_vdec_variant = { .clk_names = stm32mp25_vdec_clk_names, .num_clocks = ARRAY_SIZE(stm32mp25_vdec_clk_names), }; + +static const struct hantro_irq stm32mp25_venc_irqs[] = { + { "venc", stm32mp25_venc_irq }, +}; + +static const char * const stm32mp25_venc_clk_names[] = { + "venc-clk" +}; + +const struct hantro_variant stm32mp25_venc_variant = { + .enc_fmts = stm32mp25_venc_fmts, + .num_enc_fmts = ARRAY_SIZE(stm32mp25_venc_fmts), + .codec = HANTRO_JPEG_ENCODER, + .codec_ops = stm32mp25_venc_codec_ops, + .irqs = stm32mp25_venc_irqs, + .num_irqs = ARRAY_SIZE(stm32mp25_venc_irqs), + .clk_names = stm32mp25_venc_clk_names, + .num_clocks = ARRAY_SIZE(stm32mp25_venc_clk_names) +}; From patchwork Wed Jan 10 10:46:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 186789 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp716405dyi; Wed, 10 Jan 2024 03:06:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IGqvzCJMTsS7BDhIcEuTSXqltKuhPTvXtgbblhp+kHCrvwOG2Vc1ye1hVO/hA2P6ZrRQrTC X-Received: by 2002:a17:903:1252:b0:1d4:8be0:42a6 with SMTP id u18-20020a170903125200b001d48be042a6mr602800plh.3.1704884767992; Wed, 10 Jan 2024 03:06:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704884767; cv=none; d=google.com; s=arc-20160816; b=sAjuFIxRc1rND1JZLYg16oR/8NufiL0D56z8fLWZm3wSxROacsb1mTvgHRTNh2doiz LyZ0z5KbOv2DkMJH98O1Y94wTjHFw/9ZbNQ5Eb+e9dSJ5Hd24qHXTx87dvKdFFD3rVFp zfyDdVH521STfrERCQKelha0PTeJLzwcE1qyML0hJ5BAufFzYE2GIv9tPGwsv1lFg4ET //Sv3lnXQ3r+/uTZZqy3yg6S3B1Op+fWK3bc9+6jnXUS6qyrYhE784DQxIiBTM8XUz0F j1UkMxYtgie4Ycfb17Gh7q1CNTSB7MQbFKtVbTF5Y84Be4nWUZfb8BIFyn/JIXGbXi6s FgeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RzpMNEvKBGGGTMPiOngvcKf35zE8+NpmtuX2iQNIWo4=; fh=ErwLDw9+98Mb4Q3i5RoHr7UOS7Ns3CK5YbB+qheGbUs=; b=iCVyb6/t+TjlILOk+19mv7+8qT25ky7nd7bdjo2O3j6M+cNGueI/HRNYC0V4ObNWbf m8AT+TMOzvZbL3gVnx6zWIdQBCID4rjIAKHLwc7xsbolC0RvtoDseFX613YcSWn/Djue 3cEFR4dO08q5Qv/kADqp6Yc1JUOrgFnRfDS93yzOBNI+FZUlyb0TBVNy2Ps8x0iIZLpd lBzNLM3V0Z0N8sV3kNuxLdf819F61HnjDoLgGSyoLi8m0uy3WHFwqPJ7hRRMGWAlEx6J oo/fegzahwhp+BqKyE/Fs09nSu7wfqsG6HlEuksdeLwGF9O+FOuPRBu6SU1or9f3S5VI e0BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=5KvR+K5t; spf=pass (google.com: domain of linux-kernel+bounces-22010-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22010-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 124403f5f1f4..cd6c4f627739 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ ck_icn_ls_mcu: ck-icn-ls-mcu { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index e6fa596211f5..aea5096dac3c 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,4 +6,14 @@ #include "stm32mp253.dtsi" / { + soc@0 { + rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + }; + }; + }; }; From patchwork Wed Jan 10 10:46:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 186786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp709009dyi; Wed, 10 Jan 2024 02:50:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHrs8c/On2zCwNPK2uFcmFHH6NlgdMZqlG8QW2HVzpgoHG5jhJT4k8OQ416QmWSEbQBmFaN X-Received: by 2002:a05:622a:5a11:b0:429:7bd9:c20b with SMTP id fy17-20020a05622a5a1100b004297bd9c20bmr1384028qtb.97.1704883824111; Wed, 10 Jan 2024 02:50:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704883824; cv=none; d=google.com; s=arc-20160816; b=LbLjD0uSSZ2KnIr5egRakh4LixTe6orjLDiRVCN3kQfKLXZboCLYQA7pmZywX6nsSs lBWUJmqkY0J1rTaKUtcHDDSAzhQmROAPwKjmiwxT9nnXjHTd92PsNwrn77SquIGgAjzI Nu3BRSKyRcDvH6AXBBEku3yVaQFuJ22z9dZt7Tyn5oeCoxhe4Y6QgWP2+xUiHxhC7Iz5 aZ8XUGHfpyaEmiY2f3rTqV3HUqCdSO7GqZ7wkt9GzEbcP0evnW1+c8IR+UoyD2F6EbSY gIaCbmJU5JRwJnyi+Ml7bYqQUswLaDqXBHe20DlzHcTwhqXmBLxlh8H+HhfQhCdWJi7n fvFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=XYFUPkHCquAfdm1z7WpruAcO8XbDhwQU7gWaIj3jlwc=; fh=ErwLDw9+98Mb4Q3i5RoHr7UOS7Ns3CK5YbB+qheGbUs=; b=mdHkEUdip4/vUPLruzTwzTLQgkhCAtFm1BlLGP7+T17S3epzG4Qggw/WD4dt7ET/z3 DSZ2vtdmgJjIoeQXx4NBQZ9cnUgbh9MHUqGT9zgO8fC1bSReh8q0Sh9dwVBqu8kyz8Po VpDNybJuGRzIUQ/vSrfmtcWsAg4CZLDqCJ/Gw6z9ryoU+9usxf943RgOtKh53xI/AH9J yj2rfigPNWWYzXFa34jopnQBxZHPP7z6YjeaLrx4tfXKihqMe4C7AKFQP1r4zTxUWz3m 7Hehpv4b2Vd2oJPmZIn69gfUybe1T/vDzVj3knHgCtDl5t1ccxSNjm8Zi0cLnBHbmY9e 6riA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=si5w8zvv; spf=pass (google.com: domain of linux-kernel+bounces-22016-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-22016-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index cd6c4f627739..1584debca7f5 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -58,6 +58,12 @@ ck_icn_p_vdec: ck-icn-p-vdec { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index aea5096dac3c..17f197c5b22b 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -14,6 +14,13 @@ vdec: vdec@480d0000 { interrupts = ; clocks = <&ck_icn_p_vdec>; }; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = ; + clocks = <&ck_icn_ls_mcu>; + }; }; }; };