From patchwork Sun Nov 13 21:20:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19453 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1836405wru; Sun, 13 Nov 2022 13:21:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf7k1uV6eZHcaeIwaKKs6kUX9flHpxjyX8TDZ6QD/KYz35e+5bngslunIDRMNUyebPpue+qD X-Received: by 2002:a17:907:d387:b0:7ad:9ada:f32e with SMTP id vh7-20020a170907d38700b007ad9adaf32emr8334866ejc.591.1668374513807; Sun, 13 Nov 2022 13:21:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374513; cv=none; d=google.com; s=arc-20160816; b=RwzhErcsNMLxPE0gv3CswoXeM1PKb1B89H9CdAkWDlajsivSLFaag//wVlXgyeYTth 1J7geXwnw+MxuqazyRZ/0bYjosJo7syCoXam5+L7gkdnzRhEkgF76QJTO2xb2EWMCIVQ 8QXn9909aqWiARU1uUXEF4msnB0sb1+0M9uU0EFFLchJzxYtPM0OHJbUcj92p3aOm3vk R1M6wGgUlYbXIMQvwiOQ1kuLmUSnFQdM8OJdUtgFfIM9SX/Xu9JtVZNcLCvTHUYZECWo cB1orX2fX/OQ6F1IHwWkBR+fF+3UQdYiCeAEzhgsRxSMvjj/lB0JWGY9guxYq1HUkZUU 0zog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=xMAETwu5DqW48PO3rBFydiP/mYWqOvcAkv/VfaZBxfs=; b=mfrslo8sU4ydlDuJcuqzbXc3N/xHBwVefoTTMP9BybYMHTKocW0e9wf92x56hnQ3K7 tVYQtR9lTCWDEm4gb+cogtIexwYqFUgOPs+gW1SkxbvTSS2IGbHjKGpI5xQd0kcNMrhS sJ62Fx6iL48dDZRbAJUNum3oEIgt64K7vyRzpnVm36jfPN4AKj/xELO4TC8LO0sehAvn noVD6UeHC3G9i+OwmDM+SbyYCxMGYBj2Y6O8lLspNNx9bFAXp0ka5zT6q1+oe++P9Er/ CeveYxqVFju5ynV5S6FgMvd0qw3ypOxcfDZGdFQN2hgIU1PP02lOlHExDFE9WUQ8EiCB dkVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=JLJu98kz; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:33 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 1/8] RISC-V: Recognize xventanacondops extension Date: Sun, 13 Nov 2022 22:20:22 +0100 Message-Id: <20221113212030.4078815-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417474119410591?= X-GMAIL-MSGID: =?utf-8?q?1749417474119410591?= This adds the xventanacondops extension to the option parsing and as a default for the ventana-vt1 core: gcc/Changelog: * common/config/riscv/riscv-common.cc: Recognize "xventanacondops" as part of an architecture string. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define. (TARGET_XVENTANACONDOPS): Define. * config/riscv/riscv.opt: Add "riscv_xventanacondops". Signed-off-by: Philipp Tomsich --- Changes in v2: - Restore a (during rebase) dropped line to xventanacondops.md - Include the change to add xventanacondops to the VT1 code definition] as a separate patch. gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 8 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4b7f777c103..6b2bdda5feb 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 1be83b5107c..7962dbe5018 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -189,4 +189,7 @@ enum stack_protector_guard { ? 0 \ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define MASK_XVENTANACONDOPS (1 << 0) +#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7c3ca48d1cc..9595078bdd4 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -233,6 +233,9 @@ int riscv_zm_subext TargetVariable int riscv_sv_subext +TargetVariable +int riscv_xventanacondops = 0 + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): From patchwork Sun Nov 13 21:20:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19454 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1836469wru; Sun, 13 Nov 2022 13:22:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf48pQS0GyIkcItS6H2pPpVwyi9CBSPn0IygzlJfT83og2WPSh1qyPjmHo/aDF5hb3kHFwlq X-Received: by 2002:a17:906:3ecf:b0:7ac:db70:3ab5 with SMTP id d15-20020a1709063ecf00b007acdb703ab5mr8596727ejj.160.1668374530617; Sun, 13 Nov 2022 13:22:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374530; cv=none; d=google.com; s=arc-20160816; b=dQE0hS1pL89RpRTRvwVm1vzqG/tXJcfdLRocbfXbGDWlzd5DDBM9z3TOYlS7oJpOFg MqvvksF2pFNQycVQVeRzHLxG5Xx4hOs6i883dmQrj5XMlMaTgBHT8yeRaH7Ag/hda0jy vqS7pJ8NoVMFSqpNNQvIy8saJBXkkJ+HFp9z9Ihg5bswwra/Ri5eqUlgW2TjGiVyf2zz Gk1/O0Cns7Zxm3Sj0VBh5hmUWxVinTSw8LOSQqy2cBAXwPeESzKDc2yIyPjxK6PvviG+ HnwGuze1WKGX6W3VchKK/R0mMcGA0RNGvcqljoZ8XMNgiDwe40jjA0dyNymIoixYo/Pj 2+9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=VcVjsCWoktOoXxnBv4v5hYr5ofdM9hNIB1QOyubToak=; b=jF1hOvHmQHKHgY4IJUkRnWnAOZ0AeEvLIiuZ17QHWpyJIm83bo+a7e1OLguynp5eUf djbVSAOaFiP9GWcwCugSqfy7KO/ZFV/keHL4JEHg2jxnQ6FgrwIJCqvfkaE6D8eJwtaJ 40jHzg1UDGi9Xw193+F6jxrt7LkqVZQsq6yckTlLnegylA/FqrkNhpJA1nSGR6akHYnd DJNqoXvW3iDKN7TYlT1v+Fe/aLzNLqYss5eGnQwoY8yFPswHroxRj7xPcS6zFdQJ6msS Zjp99QH3t3JPUu90U3TOAeBeglDpad847kheUAZRXMfPFZOC2KjD+BZaeSSjczxcTCvo 9DNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=RdWP39Gz; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:34 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 2/8] RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion Date: Sun, 13 Nov 2022 22:20:23 +0100 Message-Id: <20221113212030.4078815-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417491941262195?= X-GMAIL-MSGID: =?utf-8?q?1749417491941262195?= Adds a pattern to map the output of noce_try_store_flag_mask if-conversion in the combiner onto vt.maskc; the input patterns supported are similar to the following: (set (reg/v/f:DI 75 [ ]) (and:DI (neg:DI (ne:DI (reg:DI 82) (const_int 0 [0]))) (reg/v/f:DI 75 [ ]))) This reduces dynamic instruction counts for the perlbench-workload in SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the each of the 3 workloads in the 'ref'-workload). To ensure that the combine-pass doesn't get confused about profitability, we recognize the idiom as requiring a single instruction when the XVentanaCondOps extension is present. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for vt.maskc as a single insn with TARGET_XVENTANACONDOPS. * config/riscv/riscv.md: Include xventanacondops.md. * config/riscv/xventanacondops.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ne-03.c: New test. * gcc.target/riscv/xventanacondops-ne-04.c: New test. Signed-off-by: Philipp Tomsich --- Changes in v2: - Ran whitespace-cleanup on xventanacondops-ne-03.c - Ran whitespace-cleanup on xventanacondops-ne-04.c gcc/config/riscv/riscv.cc | 14 +++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/xventanacondops.md | 30 +++++++++++++++++++ .../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++ .../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++ 5 files changed, 71 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 56fa3600f4c..43ba520885c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2336,6 +2336,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case AND: + /* vt.maskc/vt.maskcn for XVentanaCondOps */ + if (TARGET_XVENTANACONDOPS && mode == word_mode + && GET_CODE (XEXP (x, 0)) == NEG) + { + rtx inner = XEXP (XEXP (x, 0), 0); + + if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE) + && CONST_INT_P (XEXP (inner, 1)) + && INTVAL (XEXP (inner, 1)) == 0) + { + *total = COSTS_N_INSNS (1); + return true; + } + } /* slli.uw pattern for zba. */ if (TARGET_ZBA && TARGET_64BIT && mode == DImode && GET_CODE (XEXP (x, 0)) == ASHIFT) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1514e10dbd1..4331842b7b2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3196,3 +3196,4 @@ (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "xventanacondops.md") diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md new file mode 100644 index 00000000000..641cef0e44e --- /dev/null +++ b/gcc/config/riscv/xventanacondops.md @@ -0,0 +1,30 @@ +;; Machine description for X-Ventana-CondOps +;; Copyright (C) 2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator eq_or_ne [eq ne]) +(define_code_attr n [(eq "n") (ne "")]) + +(define_insn "*vt.maskc" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (neg:DI (eq_or_ne:DI + (match_operand:DI 1 "register_operand" "r") + (const_int 0))) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_XVENTANACONDOPS" + "vt.maskc\t%0,%2,%1") diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c new file mode 100644 index 00000000000..4a762a1ed61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long ne3(long long a, long long b) +{ + if (a != 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c new file mode 100644 index 00000000000..18b35ac7070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long ne4(long long a, long long b) +{ + if (a != 0) + return 0; + + return b; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ From patchwork Sun Nov 13 21:20:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19457 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1837119wru; Sun, 13 Nov 2022 13:24:13 -0800 (PST) X-Google-Smtp-Source: AA0mqf5aaezuahb9Wd0ekJvioR5hr18w+MEfJnnngHlVcgNwfOpt75tVKTTUyZ/P30QXVtZUtLwP X-Received: by 2002:a17:906:2e97:b0:7ad:79c0:547a with SMTP id o23-20020a1709062e9700b007ad79c0547amr8568964eji.41.1668374652904; Sun, 13 Nov 2022 13:24:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374652; cv=none; d=google.com; s=arc-20160816; b=EYQAM2WbpmbYBArPbyViKV+bFcCDRNHCAazUN8UK/gg0d0LLR+dkK+v6uz9Pr/PyJe 9geyOLSguEBlhpXQGxRSk7TO5pzm56yYTD7EjX4MB73w3uzsnN7k1iboqhKbLi9LH6B7 2ZMPRjnQTF71nU/S43yTfai++ToblS/j43GdvZvaivnYJApiywFzYOW4uKT629wAP0VQ ueqqdQvJJFVp3oKz3c3M8hwbXtso0g2DYWvTLAVApoB/fRrs9rvRSqh8V0MQweXnPLZX 4ksn6P67POUk7lWJC5DUcBfA0MLUXdmUISULFjzNQK6SLU8FhCKE+IMNEPRtk85l3N86 oPiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=RcdR6MpitLfibQ9CF3pkeh3wSoXK9QDYP9Oza3PCEtc=; b=sh3V0ImGjrbPtFUS2smDEJm5ykcpkI/HyUbdIhrm4f1/ryuV7WoZSprbGKn00FGyci TVNWMJrAWLYv8Dx+PgzXxQbgk5r/gG+/26rp+BriuC5W70lLcmldvAkjESIE5kr/IyIC qlIFubP0dCvb3te2pZUAEIAMrIZ/gm+uaQKcr7Cy0ycHDr4Bo2Zd7JSOAIWAiBrTm7kI 8wtPYQDtlP0DiHAuFCKFv4XiJqzkm0eOxM4KqCkhJR1z3H+NR+T/MlN42JuH4W3Xx25B ds2L+DPI5IP9VEF/D++lloKs9HU8jLjB5vu7aAUkR2dqWcMenOX6/oFUo9uPM/JEHTH6 1XCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=ql90qoXs; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:36 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc Date: Sun, 13 Nov 2022 22:20:24 +0100 Message-Id: <20221113212030.4078815-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417619577208857?= X-GMAIL-MSGID: =?utf-8?q?1749417619577208857?= When if-conversion in noce_try_store_flag_mask starts the sequence off with an order-operator, our patterns for vt.maskc will receive the result of the order-operator as a register argument; consequently, they can't know that the result will be either 1 or 0. To convey this information (and make vt.maskc applicable), we wrap the result of the order-operator in a eq/ne against (const_int 0). This commit adds the split pattern to handle these cases. During if-conversion, if noce_try_store_flag_mask succeeds, we may see if (cur < next) { next = 0; } transformed into 27: r82:SI=ltu(r76:DI,r75:DI) REG_DEAD r76:DI 28: r81:SI=r82:SI^0x1 REG_DEAD r82:SI 29: r80:DI=zero_extend(r81:SI) REG_DEAD r81:SI This currently escapes the combiner, as RISC-V does not have a pattern to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in this commit, we match such cases. gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to wrap an an order-operator suitably for generating vt.maskc. * config/riscv/predicates.md (anyge_operator): Define. (anygt_operator): Define. (anyle_operator): Define. (anylt_operator): Define. * config/riscv/riscv.md: Helpers for ge(u) & le(u). gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-le-01.c: New test. * gcc.target/riscv/xventanacondops-lt-03.c: New test. Signed-off-by: Philipp Tomsich --- Changes in v2: - Fixed a pattern that was truncated during a rebase (last line missing). - Ran whitespace-cleanup on xventanacondops-le-01.c - Ran whitespace-cleanup on xventanacondops-lt-03.c gcc/config/riscv/predicates.md | 12 +++++ gcc/config/riscv/riscv.md | 26 +++++++++++ gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++ .../gcc.target/riscv/xventanacondops-le-01.c | 16 +++++++ .../gcc.target/riscv/xventanacondops-lt-03.c | 16 +++++++ 5 files changed, 116 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index b368c11c930..490bff688a7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -204,6 +204,18 @@ (define_predicate "equality_operator" (match_code "eq,ne")) +(define_predicate "anyge_operator" + (match_code "ge,geu")) + +(define_predicate "anygt_operator" + (match_code "gt,gtu")) + +(define_predicate "anyle_operator" + (match_code "le,leu")) + +(define_predicate "anylt_operator" + (match_code "lt,ltu")) + (define_predicate "order_operator" (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4331842b7b2..d1f3270a3c8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2636,6 +2636,19 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] + { + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? LT : LTU, + mode, operands[3], operands[2]); + }) + (define_insn "*slt_" [(set (match_operand:GPR 0 "register_operand" "= r") (any_lt:GPR (match_operand:X 1 "register_operand" " r") @@ -2657,6 +2670,19 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] +{ + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + ;; ;; .................... ;; diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 641cef0e44e..f23058b95b2 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -28,3 +28,49 @@ (match_operand:DI 2 "register_operand" "r")))] "TARGET_XVENTANACONDOPS" "vt.maskc\t%0,%2,%1") + +;; Make order operators digestible to the vt.maskc logic by +;; wrapping their result in a comparison against (const_int 0). + +;; "a >= b" is "!(a < b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + +;; "a > b" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anygt_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) + +;; "a <= b" is "!(a > b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c new file mode 100644 index 00000000000..f6f80958e9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a <= b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskc\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c new file mode 100644 index 00000000000..f671f357f91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ From patchwork Sun Nov 13 21:20:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19455 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1836500wru; Sun, 13 Nov 2022 13:22:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf7TJV/SToQ+Cp1BYDAZ9IXts9q2aiIR+UyV+9o8QS5I6BIesYU2u+5on/CXCIbcIC+dENCh X-Received: by 2002:a17:907:9145:b0:78d:9f02:5458 with SMTP id l5-20020a170907914500b0078d9f025458mr8339949ejs.753.1668374536888; Sun, 13 Nov 2022 13:22:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374536; cv=none; d=google.com; s=arc-20160816; b=C2U5qPtxrd+x0PsQUZpE4vioM5b9qoTuKC+5+jUy2uBku/IUONffsR4jZWG3sppl5A YJ5vIO7fh2LE+acW2hk+UyH1yCZiYhe1whb3KvrNr2A96jBpadVEEPXuZlXcKxsRvUmD BtEyq8MhPRPYDMApktK1DFQnz5AmxhS+zswY3jfwFRCNu4OEBiKgKw1AhA79y8czhpQB 8TJLmrYCYNffmN72Nh9u+TCB1FbsQ+yXvdHL/HFulY5FnvRJz9PbZxXYS66Oa8uearCW xEAufoAVnM4RzLa7whD0rOPtZbaucKcaLMOoxrAkaDjwXScH9V/irx4gnj8RzcGi5I/x kfug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=i1CiygP7lqZttrGh8t0+Mw1ON8fR+7WJernWguWy5uk=; b=jFKOGnQrOhD4L7b5YfQlYM3y52oj9Gjxo8yegUtweFG1nhbkTjFIHynINeg7gj9qn9 DtivHiRDIBEfZYhv6Zf2/MsNV+hEJ/OvRGovoU65VuKo2PHLG0RNBL5rRf3QgkS4K/JT RnbhYYpW3K/UU63iRNg5w7HaYWXgv6pcggy+zEhJrMOSNw1f/JvI6QwwNUpV5S0C6f0b q5P9o5W/0JMr0IZR9UqwYD9szVqlGQ9xkx4PhDlNmkjdhV6yx4be3SD+ayUmKdDECZt4 +TNXob+fBDDP5+NeLxHXoEITCFzYdbUOGUR9+LU9KOJtBUT5gK8Mh0KIsRzC398mYYf0 GHOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b="UdPN/si7"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:37 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 4/8] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Date: Sun, 13 Nov 2022 22:20:25 +0100 Message-Id: <20221113212030.4078815-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417498381148206?= X-GMAIL-MSGID: =?utf-8?q?1749417498381148206?= Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combination of XVentanaCondOps and Zbs are available, this will map to the following sequences: - bexti + vt.maskc, if both Zbs and XVentanaCondOps are present - andi + vt.maskc, if only XVentanaCondOps is available and the sign-extract is operating on bits 10:0 (bit 11 can't be reached, as the immediate is sign-extended) - slli + srli + and, otherwise. gcc/ChangeLog: * config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT of a single-bit followed by AND for XVentanaCondOps. Signed-off-by: Philipp Tomsich --- (no changes since v1) gcc/config/riscv/xventanacondops.md | 45 +++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index f23058b95b2..a4068e53c13 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -74,3 +74,48 @@ [(set (match_dup 5) (match_dup 1)) (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) (match_dup 4)))]) + +;; Users might use explicit arithmetic operations to create a mask and +;; then and it, in a sequence like +;; cond = (bits >> SHIFT) & 1; +;; mask = ~(cond - 1); +;; val &= mask; +;; which will present as a single-bit sign-extract in the combiner. +;; +;; This will give rise to any of the following cases: +;; - with Zbs and XVentanaCondOps: bexti + vt.maskc +;; - with XVentanaCondOps (but w/o Zbs): +;; - andi + vt.maskc, if the mask is representable in the immediate +;; (which requires extra care due to the immediate +;; being sign-extended) +;; - slli + srli + and +;; - otherwise: slli + srli + and + +;; With Zbb, we have bexti for all possible bits... +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_XVENTANACONDOPS && TARGET_ZBS" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))]) + +;; ...whereas RV64I only allows us access to bits 0..10 in a single andi. +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))] +{ + operands[2] = GEN_INT(1 << UINTVAL(operands[2])); +}) From patchwork Sun Nov 13 21:20:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19458 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1837122wru; Sun, 13 Nov 2022 13:24:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf5J59PdVG+10/9CdLaZXm5S9l/XiQNFfJSUki9j2nNXK8MyGB2R/Pru2X40zbhsXB+cDgPT X-Received: by 2002:a17:906:53d8:b0:7ad:cc9f:4ae0 with SMTP id p24-20020a17090653d800b007adcc9f4ae0mr8001069ejo.504.1668374654158; Sun, 13 Nov 2022 13:24:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374654; cv=none; d=google.com; s=arc-20160816; b=B6DfkqaMJqh1ylYFC2ySeBjThBki/MR88M+iCYxcLPp4nWhNzdBLnFM5Bea21/xW7Y qqixNOA2xG6KAWmxmFc6xxGam1hgLb3Jiy2IAy4t+XsyIRCmqPp7sptBP0O8aqnuSOe6 OlLvvbJZr9NzhhE2qYxIHgaspycZX4F1nU7Tn3BwkhcCJIDwzWi7UtUygWNzRpDLdSbj ClsLuadd1E1q4Z4byy86TUWQ1a8i5j/ZQ1Rg2IgNCNLPALEtfqV4fhmXIDglZTSkb9qQ ZvkoM2HHiY2ACHkAZ1SAf746jFcIZ1G18r4vx20ooSkcw3A8xfr++oYSj6O8dBbZ+DqR ensA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=RIq9mP5aMinKyTfA0EYklaBArZOHJY9294/fIk2BNqY=; b=xcBoyQN85mYneRHnxB9Qu7h369e5gZNeG5eyiBfhgizRcI/KawpQu/nkcu1mJHibnN cBxM/MYO/8uj1LxbiQlv83utmINJo7c8jAJr1rDBeX5ozSYrVzNkvnlmyGXfSCRJjEdF oSCd4AOqkFmUE31FnhVf6FNZwyt09e5BSYNP9inXU6oYfzEZJL4acUrBjdauHSd6MyFg fI+svxsnNWB1qOwnacxUlaGTEFo4eU6Oo8ubzgksOCQTXyAglw4e/PQyVnKjbt3GFGtS 1HHUTsbdw+Y/hLeBjlW9Iy+NnetMeYkJd6/9eZ16wTe53H/9up/vr/LbO7yGcv+oD4LK NeFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=GdFpJlsa; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:39 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 5/8] RISC-V: Recognize bexti in negated if-conversion Date: Sun, 13 Nov 2022 22:20:26 +0100 Message-Id: <20221113212030.4078815-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417621509417015?= X-GMAIL-MSGID: =?utf-8?q?1749417621509417015?= While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with XVentanaCondOps (andi + vt.maskc) the inverted/negated case results in andi a5,a0,1024 seqz a5,a5 neg a5,a5 and a5,a5,a1 due to how the sequence presents to the combine pass. This adds an additional splitter to reassociate the polarity reversed case into bexti + addi, if Zbs is present. gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to reassociate "andi + seqz + neg" into "bexti + addi". Signed-off-by: Philipp Tomsich --- Changes in v2: - Removed spurious empty line at the end of xventanacondops.md. gcc/config/riscv/xventanacondops.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index a4068e53c13..81e5e8a8298 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -119,3 +119,13 @@ { operands[2] = GEN_INT(1 << UINTVAL(operands[2])); }) + +(define_split + [(set (match_operand:X 0 "register_operand") + (neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (const_int 0))))] + "!TARGET_XVENTANACONDOPS && TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))]) From patchwork Sun Nov 13 21:20:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19456 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1837033wru; Sun, 13 Nov 2022 13:23:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf7/ZYtvlSjUqgHjMZbYaCivTwqVZA2dgRnYFwuHCZIGd6z6Y79bTZBKrb1tV3q6AN0oI/pS X-Received: by 2002:a17:906:5ac6:b0:7ad:ab0e:76aa with SMTP id x6-20020a1709065ac600b007adab0e76aamr8255685ejs.435.1668374637758; Sun, 13 Nov 2022 13:23:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374637; cv=none; d=google.com; s=arc-20160816; b=O8qxg0V72gDSxs6BIeeMcjo1oYSXv1jamgNzFu5aOcqFIzQ9gHoVJ1O38FDlMIsBLl RO8DBga2WId7TSVrjyP94LOtcGfxVeL3zH+7KoKYIdiRFENtwuJ+zk0sE9Can+gIJ6/4 qZ6p76Io8AUtADwsTkY0EPzOjfglfp/Fo+x6/JdpQ/Nq9ZyzrLxrxn0OwsojpORmOeqg v9WaqYivdPOHA/DBkHsG5yn6s2mOFfTrJh0Ah9v87OewkmwUL2/Z6yBH5nZ21Omr0DwB gDd5gP5FeMbRRlGyycufCtfZIrdeg3i0Vd/RxCq5jDpNMt8ABHm2JmWJLDODgV9xRz4j 4CGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=b3VGfLPXdNiqtWor6/bIjoP03UtomcZJKF6AQhGr5xo=; b=rpBbYiUq63vD8HP6gbkw/B6wJbIEAkY7LPxAMuPSBkzvJN+WeJwnizBfcgqXcjbhpJ eA9tMaB/TSkflTMcgGzTznBCCw4jQGtgqqaP6Gmgs1plbb6TeoqGO6jxNM+k/MdH8piv WB9mF0fRdFLMVO3r1BES3khACu9djyXTqdewvokjx/Em/yKy6mcXEUg3X70v/MIQTEI+ k8QFGWhcnfKrt0I8UDd2ItAJW+3O7rtfH4L/NXjFEvYOgseqrhWHUSM0XaX26ukAEU9U dBUFRHAY9xQg4qoEQ1mSsQ+Xee7Ki5RFWLzlmLGh7aHVnT035GYHRmu6D/YsnaL2NbFg w3sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=r6Gd3i34; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:40 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich , Henry Brausen Subject: [PATCH v2 6/8] RISC-V: Support immediates in XVentanaCondOps Date: Sun, 13 Nov 2022 22:20:27 +0100 Message-Id: <20221113212030.4078815-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417604390753330?= X-GMAIL-MSGID: =?utf-8?q?1749417604390753330?= When if-conversion encounters sequences using immediates, the sequences can't trivially map back onto vt.maskc/vt.maskcn (even if benefitial) due to vt.maskc and vt.maskcn not having immediate forms. This adds a splitter to rewrite opportunities for XVentanaCondOps that operate on an immediate by first putting the immediate into a register to enable the non-immediate vt.maskc/vt.maskcn instructions to operate on the value. Consider code, such as long func2 (long a, long c) { if (c) a = 2; else a = 5; return a; } which will be converted to func2: seqz a0,a2 neg a0,a0 andi a0,a0,3 addi a0,a0,2 ret Following this change, we generate li a0,3 vt.maskcn a0,a0,a2 addi a0,a0,2 ret This commit also introduces a simple unit test for if-conversion with immediate (literal) values as the sources for simple sets in the THEN and ELSE blocks. The test checks that Ventana's conditional mask instruction (vt.maskc) is emitted as part of the resultant branchless instruction sequence. gcc/ChangeLog: * config/riscv/xventanacondops.md: Support immediates for vt.maskc/vt.maskcn through a splitter. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ifconv-imm.c: New test. Signed-off-by: Philipp Tomsich Reviewed-by: Henry Brausen --- Ref #204 (no changes since v1) gcc/config/riscv/xventanacondops.md | 24 +++++++++++++++++-- .../riscv/xventanacondops-ifconv-imm.c | 19 +++++++++++++++ 2 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 81e5e8a8298..e3e109828a2 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -29,6 +29,26 @@ "TARGET_XVENTANACONDOPS" "vt.maskc\t%0,%2,%1") +;; XVentanaCondOps does not have immediate forms, so we need to do extra +;; work to support these: if we encounter a vt.maskc/n with an immediate, +;; we split this into a load-immediate followed by a vt.maskc/n. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (neg:DI (match_operator:DI 1 "equality_operator" + [(match_operand:DI 2 "register_operand") + (const_int 0)])) + (match_operand:DI 3 "immediate_operand"))) + (clobber (match_operand:DI 4 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (and:DI (neg:DI (match_dup 1)) + (match_dup 4)))] +{ + /* Eliminate the clobber/temporary, if it is not needed. */ + if (!rtx_equal_p (operands[0], operands[2])) + operands[4] = operands[0]; +}) + ;; Make order operators digestible to the vt.maskc logic by ;; wrapping their result in a comparison against (const_int 0). @@ -37,7 +57,7 @@ [(set (match_operand:X 0 "register_operand") (and:X (neg:X (match_operator:X 1 "anyge_operator" [(match_operand:X 2 "register_operand") - (match_operand:X 3 "register_operand")])) + (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] "TARGET_XVENTANACONDOPS" @@ -54,7 +74,7 @@ [(set (match_operand:X 0 "register_operand") (and:X (neg:X (match_operator:X 1 "anygt_operator" [(match_operand:X 2 "register_operand") - (match_operand:X 3 "register_operand")])) + (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] "TARGET_XVENTANACONDOPS" diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c new file mode 100644 index 00000000000..0012e7b669c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* Each function below should emit a vt.maskcn instruction */ + +long +foo0 (long a, long b, long c) +{ + if (c) + a = 0; + else + a = 5; + return a; +} + +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ +/* { dg-final { scan-assembler-not "beqz\t" } } */ +/* { dg-final { scan-assembler-not "bnez\t" } } */ From patchwork Sun Nov 13 21:20:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19460 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1837511wru; Sun, 13 Nov 2022 13:25:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf7NiL34Q975HX7CUy+n/iHFx6TY62XnPq8Ju7CuEABoiqZ2Ry8v6QXpLgA0FgpaZzdIWC5f X-Received: by 2002:a17:906:b019:b0:78e:ebb:cbb7 with SMTP id v25-20020a170906b01900b0078e0ebbcbb7mr8596709ejy.38.1668374734396; Sun, 13 Nov 2022 13:25:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374734; cv=none; d=google.com; s=arc-20160816; b=fuHuNfjgv+EB9VLuFYn+xGmqfd3Bx0xP256Ppv8HLhsqRUPpP+877OWOdtR8HCVca5 FrEPWEzuBERdtioBFqntmcvzhRm3pOfNZmQvX6xP0HglAcXsXR5NlOjufItXq+jqSL/X baE0WmNmJX4zSnM6XmUJnJTbDbuEuDTxxS9ablAUyb/ldK6zCejgnFdyBaP8DiYRVtPe yQ/Nop3NVyZ/X1xmgbXMg27nZwtHTFnlakVSB4u3Djpj1iFzD1YtMY6zKU/fU4LZLzPs M+sG8Z0baM8nw8/XzZp/w9RYW50uo++jhc3xv1KbPc9L415OsgZu6AQaWFmZyF/zHQVk hp2w== ARC-Message-Signature: i=1; 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:41 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps Date: Sun, 13 Nov 2022 22:20:28 +0100 Message-Id: <20221113212030.4078815-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417705705296901?= X-GMAIL-MSGID: =?utf-8?q?1749417705705296901?= gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Update the Ventana-VT1 definition to include the xventanacondops extension. Signed-off-by: Philipp Tomsich --- Changes in v2: - New in v2. gcc/config/riscv/riscv-cores.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index aef1e92ae24..9e38e9dc72e 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") -RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei", "ventana-vt1") +RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops", "ventana-vt1") #undef RISCV_CORE From patchwork Sun Nov 13 21:20:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19459 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1837472wru; Sun, 13 Nov 2022 13:25:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Zk6hHwbURU4pNdU1xBC9gkI6noTdui4dTUuIFmfoHJdpr6mD6YDiDwGJ3fbO/00tQwfle X-Received: by 2002:a50:fc1a:0:b0:461:8972:e3b8 with SMTP id i26-20020a50fc1a000000b004618972e3b8mr8902016edr.110.1668374724531; Sun, 13 Nov 2022 13:25:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668374724; cv=none; d=google.com; s=arc-20160816; b=Rxd4aXnVoVLX0PzsEA0W1ehRND8Dp6VHT8fhYLNEoSn4Relbx2rnzUch7ImVa1S3mM pUcsHkKHKd5NCu/LD6lb97N/mJQ2Ra7F6j8gMVycUToMAqeGm88V+CtAbTXa9H/Ul32E Ws4VLhY8QGJ2nEKdjstq7PiYsxnaFjw6zzxQ+AlWj7Nwd3VS2JsSk4IBLwC70F8Q7Tvp RJw1N7sS5gQw6MOPWEg/gdL1fPO1I9gYxgT6AkzaN2lBSOEwMpwF2PVdPq9D4RM3uCs5 xxbPSisZ7mZ76UwUZDHKuqrUADHaqdBvHS/DWjoDkJrWFB+s3pMctJuhFsB1Fn0NscXT 0Dzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=e9g0FsBUqz9m/xhcis4pcpyWgBccXzLyPEaywT1sOoM=; b=Xf3nwyZwPgyRxjGRLK43dCIwYJRcnz76nZdCiRz+/WXpCOP5yyUa0wtkLOFiHM2bmm HCJRQgjpnoRTNN/J/SklBY20Mf5ToRaLtoPeuWi4ObDOHfa51zzBnZxT+PpRXRTkRZjp DSmfe9Au/hPNR9pnW3KG/weNk6X6knmgMePrMRIdRLBTRE0mTgv2yOkMMW5KhWpG8hOb uiWZNCTtQYvJK1ASIZ878e4WtiBzsie7tG6dH3H91eNSVmyyUp+ypN8S73e/FWHn/Vit coR1cf3Yvvq/TkGuVvwvQpRaPSMxtJsDFlxMkWXRVb0uq2IKTxkCH7QXbt4+o9rP9uaI UyNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=ng3hVvgI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:43 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 8/8] ifcvt: add if-conversion to conditional-zero instructions Date: Sun, 13 Nov 2022 22:20:29 +0100 Message-Id: <20221113212030.4078815-9-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417694716483713?= X-GMAIL-MSGID: =?utf-8?q?1749417694716483713?= Some architectures, as it the case on RISC-V with the proposed ZiCondOps and the vendor-defined XVentanaCondOps, define a conditional-zero instruction that is equivalent to: - the positive form: rd = (rc != 0) ? rs : 0 - the negated form: rd = (rc == 0) ? rs : 0 While noce_try_store_flag_mask will somewhat work for this case, it will generate a number of atomic RTX that will misdirect the cost calculation and may be too long (i.e., 4 RTX and more) to successfully merge at combine-time. Instead, we add two new transforms that attempt to build up what we define as the canonical form of a conditional-zero expression: (set (match_operand 0 "register_operand" "=r") (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") (const_int 0))) (match_operand 2 "register_operand" "r"))) Architectures that provide a conditional-zero are thus expected to define an instruction matching this pattern in their backend. Based on this, we support the following cases: - noce_try_condzero: a ? a : b a ? b : 0 (and then/else swapped) !a ? b : 0 (and then/else swapped) - noce_try_condzero_arith: conditional-plus, conditional-minus, conditional-and, conditional-or, conditional-xor, conditional-shift, conditional-and Given that this is hooked into the CE passes, it is less powerful than a tree-pass (e.g., it can not transform cases where an extension, such as for uint16_t operations is in either the then or else-branch together with the arithmetic) but already covers a good array of cases and triggers across SPEC CPU 2017. Adding transofmrations in a tree pass will be considered as a future improvement. gcc/ChangeLog: * ifcvt.cc (noce_emit_insn): Add prototype. (noce_emit_condzero): Helper for noce_try_condzero and noce_try_condzero_arith transforms. (noce_try_condzero): New transform. (noce_try_condzero_arith): New transform for conditional arithmetic that can be built up by exploiting that the conditional-zero instruction will inject 0, which acts as the neutral element for operations. (noce_process_if_block): Call noce_try_condzero and noce_try_condzero_arith. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-and-01.c: New test. * gcc.target/riscv/xventanacondops-and-02.c: New test. * gcc.target/riscv/xventanacondops-eq-01.c: New test. * gcc.target/riscv/xventanacondops-eq-02.c: New test. * gcc.target/riscv/xventanacondops-lt-01.c: New test. * gcc.target/riscv/xventanacondops-ne-01.c: New test. * gcc.target/riscv/xventanacondops-xor-01.c: New test. Signed-off-by: Philipp Tomsich --- Changes in v2: - Ran whitespace-cleanup on xventanacondops-ne-01.c. gcc/ifcvt.cc | 214 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 10 + .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ 8 files changed, 310 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index eb8efb89a89..41c58876d05 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -97,6 +97,7 @@ static int find_if_case_2 (basic_block, edge, edge); static int dead_or_predicable (basic_block, basic_block, basic_block, edge, int); static void noce_emit_move_insn (rtx, rtx); +static rtx_insn *noce_emit_insn (rtx); static rtx_insn *block_has_only_trap (basic_block); static void need_cmov_or_rewire (basic_block, hash_set *, hash_map *); @@ -787,6 +788,9 @@ static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **); static int noce_try_minmax (struct noce_if_info *); static int noce_try_abs (struct noce_if_info *); static int noce_try_sign_mask (struct noce_if_info *); +static rtx noce_emit_condzero (struct noce_if_info *, rtx, bool = false); +static int noce_try_condzero (struct noce_if_info *); +static int noce_try_condzero_arith (struct noce_if_info *); /* Return the comparison code for reversed condition for IF_INFO, or UNKNOWN if reversing the condition is not possible. */ @@ -1664,6 +1668,212 @@ noce_try_addcc (struct noce_if_info *if_info) return FALSE; } +/* Helper to noce_try_condzero: cond ? a : 0. */ +static rtx +noce_emit_condzero (struct noce_if_info *if_info, rtx a, bool reverse) +{ + /* The canonical form for a conditional-zero-or-value is: + (set (match_operand 0 "register_operand" "=r") + (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") + (const_int 0))) + (match_operand 2 "register_operand" "r"))) + */ + + machine_mode opmode = GET_MODE (if_info->x); + enum rtx_code code = GET_CODE (if_info->cond); + rtx cond; + rtx op_a = XEXP (if_info->cond, 0); + rtx op_b = XEXP (if_info->cond, 1); + + /* If it is not a EQ/NE comparison against const0_rtx, canonicalize + by first synthesizing a truth-value and then building a NE + condition around it. */ + if ((code != EQ && code != NE) || XEXP (if_info->cond, 1) != const0_rtx) + { + rtx tmp = gen_reg_rtx (opmode); + + start_sequence (); + cond = gen_rtx_fmt_ee (code, opmode, op_a, op_b); + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) + { + end_sequence (); + + /* If we can't emit this pattern, try to reverse it and + invert the polarity of the second test. */ + start_sequence (); + cond = gen_rtx_fmt_ee (reverse_condition (code), opmode, op_a, op_b); + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) { + end_sequence (); + return NULL_RTX; + } + + /* We have recovered by reversing the first comparison, + so we need change the second one around as well... */ + reverse = !reverse; + } + rtx_insn *seq = get_insns (); + end_sequence (); + emit_insn (seq); + + /* Set up the second comparison that will be embedded in the + canonical conditional-zero-or-value RTX. */ + code = NE; + op_a = tmp; + op_b = const0_rtx; + } + + cond = gen_rtx_fmt_ee (reverse ? reverse_condition (code) : code, + opmode, op_a, op_b); + + /* Build (and (neg (eq_or_ne ... const0_rtx)) (reg )) */ + rtx target = gen_reg_rtx (opmode); + rtx czero = gen_rtx_AND (opmode, gen_rtx_NEG (opmode, cond), a); + noce_emit_move_insn (target, czero); + + return target; +} + +/* Use a conditional-zero instruction for "if (test) x = 0;", if available. */ +static int +noce_try_condzero (struct noce_if_info *if_info) +{ + rtx target; + rtx_insn *seq; + int reversep = 0; + rtx orig_b = NULL_RTX; + rtx cond = if_info->cond; + enum rtx_code code = GET_CODE (cond); + rtx cond_arg0 = XEXP (cond, 0); + rtx cond_arg1 = XEXP (cond, 1); + + if (!noce_simple_bbs (if_info)) + return FALSE; + + /* We may encounter the form "(a != 0) ? a : b", which can be + simplified to "a | ((a != 0) ? 0 : b)". */ + if (code == NE && cond_arg1 == const0_rtx && + REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0)) + { + orig_b = if_info->b; + if_info->b = const0_rtx; + } + + /* We may encounter the form "(a != 0) ? b : a", which can be + simplied to "(a != 0) ? b : 0". */ + if (code == EQ && cond_arg1 == const0_rtx && + REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0)) + { + /* We know that cond_arg0 is const_0, if the THEN branch is + taken... so if it is the same as if_info->b (yes, things are + backwards!), we can rewrite it with that knowledge. */ + if_info->b = const0_rtx; + } + + start_sequence (); + + if ((if_info->a == const0_rtx + && (REG_P (if_info->b) || rtx_equal_p (if_info->b, if_info->x))) + || ((reversep = (noce_reversed_cond_code (if_info) != UNKNOWN)) + && if_info->b == const0_rtx + && (REG_P (if_info->a) || rtx_equal_p (if_info->a, if_info->x)))) + { + target = noce_emit_condzero(if_info, + reversep ? if_info->a : if_info->b, + reversep); + + if (orig_b && target) + target = expand_simple_binop (GET_MODE (if_info->x), IOR, orig_b, + target, if_info->x, 0, OPTAB_WIDEN); + + if (target) + { + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc (seq, if_info->jump, + INSN_LOCATION (if_info->insn_a)); + if_info->transform_name = "noce_try_condzero"; + + return TRUE; + } + } + + end_sequence (); + + return FALSE; +} + +/* Convert "if (test) x op= a;" to a branchless sequence using the + canonical form for a conditional-zero. */ +static int +noce_try_condzero_arith (struct noce_if_info *if_info) +{ + rtx target; + rtx_insn *seq; + rtx_code op = GET_CODE (if_info->a); + const rtx arg0 = XEXP (if_info->a, 0); + const rtx arg1 = XEXP (if_info->a, 1); + + if (!noce_simple_bbs (if_info)) + return FALSE; + + /* Check for no else condition. */ + if (!rtx_equal_p (if_info->x, if_info->b)) + return FALSE; + + if (op != PLUS && op != MINUS && op != IOR && op != XOR && + op != ASHIFT && op != ASHIFTRT && op != LSHIFTRT && op != AND) + return FALSE; + + if (!rtx_equal_p (if_info->x, arg0)) + return FALSE; + + start_sequence (); + + target = noce_emit_condzero(if_info, arg1, op != AND ? true : false); + + if (target) + { + rtx op1 = if_info->x; + + if (op == AND) + { + /* Emit "tmp = x & val;" followed by "tmp |= !cond ? x : 0;" */ + op1 = expand_simple_binop (GET_MODE (if_info->x), AND, op1, + arg1, NULL_RTX, 0, OPTAB_WIDEN); + op = IOR; + } + + if (op1) + target = expand_simple_binop (GET_MODE (if_info->x), op, op1, + target, if_info->x, 0, OPTAB_WIDEN); + } + + if (target) + { + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc(seq, if_info->jump, + INSN_LOCATION(if_info->insn_a)); + if_info->transform_name = "noce_try_condzero_arith"; + + return TRUE; + } + + end_sequence (); + + return FALSE; +} + /* Convert "if (test) x = 0;" to "x &= -(test == 0);" */ static int @@ -3967,8 +4177,12 @@ noce_process_if_block (struct noce_if_info *if_info) { if (noce_try_addcc (if_info)) goto success; + if (noce_try_condzero (if_info)) + goto success; if (noce_try_store_flag_mask (if_info)) goto success; + if (noce_try_condzero_arith (if_info)) + goto success; if (HAVE_conditional_move && noce_try_cmove_arith (if_info)) goto success; diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c new file mode 100644 index 00000000000..9b26cdf0513 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long and1(long a, long b, long c, long d) +{ + if (c < d) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "slt" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c new file mode 100644 index 00000000000..66d2ec10211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +int and2(int a, int b, long c) +{ + if (c) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c new file mode 100644 index 00000000000..bc877d9e81b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq1 (long a, long b) +{ + return (a == 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c new file mode 100644 index 00000000000..28317613ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq2 (long a, long b) +{ + if (a == 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c new file mode 100644 index 00000000000..db7498801f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "vt.maskcn\" 1 } } */ +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c new file mode 100644 index 00000000000..be8375ba5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long ne1(long long a, long long b) +{ + return (a != 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c new file mode 100644 index 00000000000..43020790a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long xor1(long crc, long poly) +{ + if (crc & 1) + crc ^= poly; + + return crc; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ +/* { dg-final { scan-assembler-times "xor\t" 1 } } */