From patchwork Wed Jan 10 01:31:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 186662 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp519377dyi; Tue, 9 Jan 2024 17:34:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IE/K4qqzzezVmQ6EVsWMD+2qewpWtiFDkYcl7dQSSQZIJFREF9eCuJv8pwVTx6CTs1ayAc4 X-Received: by 2002:a05:622a:291:b0:429:9fb1:1665 with SMTP id z17-20020a05622a029100b004299fb11665mr445054qtw.10.1704850476272; Tue, 09 Jan 2024 17:34:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704850476; cv=pass; d=google.com; s=arc-20160816; b=QSknibUK2fY1wNSJ8p7HliKVzpzONZga73sDA4bDkYojoHQLir67W/0kPe4Z0OjlWZ 57mO+Uqp3KD5YgtMOnLkZjupaO4n3DDzEAnGv8SU5jgysRYDiCUKv26aeZjI1V4mvTBF +r9WlzZTNIYOkAfuII4RiN8Pk+2/IdNNWZ/pdWu8G4bzyLh3Soqa5CyyE1hvkWfDjoRM xqBdbCogiB+bFDY/PGfGPaHpwP6xplqNlx5SrWigPl5TKXHgE31wvvdkW8q09FYq5LhN PuHVvqE0UTGL2ipA0/SD/IzYNGRIx42tEZJWNmo39hNlx7svMuibNEHSNW24nli6pwtt UGyQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=r75FalXl267s3Hg8YOUcuGNHEDpupBXiC9a8eHEdu54=; fh=r+SIYcgLopsTG8D0vSkuNNcbfbLGreWBAuINt5YEr6Q=; b=skHuRTV+1JntcMdWAcVeptD0oVSmX6CWOfKvCVZdMg906SzN+QBVpi5xUENT/XVQts bq/WPD3Sov37V3bzcDeNJZ/Df8kPwXUx08ZYq9XiOjO7FGnBzDav/TwfLmd5gyF/J0pV /Hs1QtXqVHIBZwBc8yEp73mNZmHiJ4jWOMtBhtenDi+W2K7geyd5sBMig4uaTztDmxVE rcysf6WFO7KQ7VXM1EQ/dnU4uQxHbLPLvDJRdKWyO8RH7iFD3HRG8H/yeCUXC6tERNTB KCUifLnXXWhee64zylRGH8FhKOCB2oQkuV/BEea8V5xfUdc0sEJTGFnW8Lti6HJIfSgy QUdQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=A3dOt5qm; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id cn6-20020a05622a248600b00429aa10bf11si2268170qtb.214.2024.01.09.17.34.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:34:36 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=A3dOt5qm; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EA32E38582AC for ; Wed, 10 Jan 2024 01:34:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by sourceware.org (Postfix) with ESMTPS id 6496A3858D33 for ; Wed, 10 Jan 2024 01:32:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6496A3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6496A3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:4860:4864:20::34 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850336; cv=none; b=qRXOCEt6bxneqNSziEF5Ub5qaZgnrOkzEP0oHiWKl9wcSsTqhIroeiXbscQ9x4N+tZDVaSOWXzwmvqB629bjmSP8rAhGl17XUbAer20YJeFJkCDVW9AXKsIA70O5i7C2Kfgl9QFVzXA+qId40+9i0ZT2JXdEhbC2hZEcsz6UJEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850336; c=relaxed/simple; bh=OVZ5JaT5KYvRih8rpDBUDg6GI6E2H2UhYFENS5ymO54=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=rBsgybJdCoVECMePOqf3ytYD0W75OUsZ/Gh2rSfpEWl/+qRKutOWtSDrYMy2IZbHmUDC3UuaoZNrzSTnHUJfaTNfYugGqDjwsTqTM/Dt8FbPGgA+yQaae0E2TAinlojdWwTzLC7zE1fUGTXpVOFyxHBQyAtG2wJTuRClJmNZ0UY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-20503dc09adso2558750fac.2 for ; Tue, 09 Jan 2024 17:32:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704850330; x=1705455130; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r75FalXl267s3Hg8YOUcuGNHEDpupBXiC9a8eHEdu54=; b=A3dOt5qmOvHT9XEW/doWomFJp47GpMigNH8TJfwpP2x8lkuh/l+6qdHaueqOAXdALH Vrvlz1Ev2g/48h7aP8o503rew9qsQXYWare92a0hUHACJ9a8KT1OfPsqXxmZ9uXy718u Gvp/pf5P7xA3jZlH3qf/X2SJivmeaF8MmRdcS31R9Wu+CNv6Ih7umY8opt0FWfLwum47 sg1FWOevATSkIXztD5DVCJ+IMSugekvzwqmirRgNXyboRzvf3Bdtd6S0C8f2VJvYlCoL 7ZjeQoM6D+AJWVPY34CCMtfvIta91rhr71Su+BWIfWiuwlP1GQKg8yf51NMGii1DkZG5 spbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704850330; x=1705455130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r75FalXl267s3Hg8YOUcuGNHEDpupBXiC9a8eHEdu54=; b=pvDIasgQJsddpdlSGneKSQzXYThLfa8Mj2nw/7IIJAt9XsjnlWRexjddkr6vQMeOrt bmt7A1v9mr5BMdQBv34Uko/AQba+iIr3v+5oWvt4JsIh6wFDshYB4omChyo/AHBO+0IQ g8znmhZkflzuXYeeEoYGhg6cYfXXWF04FM8fLhmBMSxHNPNqRQpNJgNU6REgxf862+/v ljfzpylMqtoskkOdHQVCHbAnWFueie05pux8h71ra0vUeiI5aEFit3x+A5Sj0vC7dlwW K85DStkCiEcsghqTJZawGQHK/4k7ar0McDMBzPDhJIE5QGqh5bXSCuSv+iJ7uw65tuEy wS1g== X-Gm-Message-State: AOJu0YxRoztm+iFV5TtnMCgkiLss5QpzC2hzPZuPFrgiiBbANrp/9bNj idNAVKUUi2rtoGDs2LQc96WejAG3Qmw2ewq6B4TkchQ1rJI= X-Received: by 2002:a05:6871:3a20:b0:204:1ed0:83ef with SMTP id pu32-20020a0568713a2000b002041ed083efmr443336oac.36.1704850330185; Tue, 09 Jan 2024 17:32:10 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id a9-20020a9d4709000000b006dc81d1d203sm565423otf.73.2024.01.09.17.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:32:09 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines Date: Tue, 9 Jan 2024 17:31:56 -0800 Message-Id: <20240110013159.2645757-2-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110013159.2645757-1-ewlu@rivosinc.com> References: <20240110013159.2645757-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787665292876174957 X-GMAIL-MSGID: 1787665292876174957 This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): ditto * config/riscv/generic.md (generic_sfb_alu): ditto (generic_fmul_half): ditto * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation (sifive_7_popcount): ditto * config/riscv/vector.md: change rdfrm to fmove * config/riscv/zc.md: change pushpop to load/store Signed-off-by: Edwin Lu --- V2: - Add insn reservations for HF fmul - Remove/adjust insn types --- gcc/config/riscv/generic-ooo.md | 15 +++++- gcc/config/riscv/generic.md | 20 +++++-- gcc/config/riscv/riscv.md | 18 +++---- gcc/config/riscv/sifive-7.md | 17 +++++- gcc/config/riscv/vector.md | 2 +- gcc/config/riscv/zc.md | 96 ++++++++++++++++----------------- 6 files changed, 102 insertions(+), 66 deletions(-) diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index 421a7bb929d..ef8cb96daf4 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10 (define_insn_reservation "generic_ooo_alu" 1 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ - move,bitmanip,min,max,minu,maxu,clz,ctz")) + move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\ + condmove,mvpair,zicond")) "generic_ooo_issue,generic_ooo_ixu_alu") +(define_insn_reservation "generic_ooo_sfb_alu" 2 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "sfb_alu")) + "generic_ooo_issue,generic_ooo_ixu_alu") + +;; Branch instructions +(define_insn_reservation "generic_ooo_branch" 1 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) + "generic_ooo_issue,generic_ooo_ixu_alu") ;; Float move, convert and compare. (define_insn_reservation "generic_ooo_float_move" 3 @@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2 (define_insn_reservation "generic_ooo_vec_alu" 3 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov")) + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector float comparison, conversion etc. diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index b99ae345bb3..45986cfea89 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0") (define_insn_reservation "generic_alu" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop")) + (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ + move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\ + condmove,crypto,mvpair,zicond")) "alu") (define_insn_reservation "generic_load" 3 @@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3 (define_insn_reservation "generic_branch" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "branch,jump,call,jalr")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) + "alu") + +(define_insn_reservation "generic_sfb_alu" 2 + (and (eq_attr "tune" "generic") + (eq_attr "type" "sfb_alu")) "alu") (define_insn_reservation "generic_imul" 10 (and (eq_attr "tune" "generic") - (eq_attr "type" "imul,clmul")) + (eq_attr "type" "imul,clmul,cpop")) "imuldiv*10") (define_insn_reservation "generic_idivsi" 34 @@ -67,6 +74,12 @@ (define_insn_reservation "generic_idivdi" 66 (eq_attr "mode" "DI"))) "imuldiv*66") +(define_insn_reservation "generic_fmul_half" 5 + (and (eq_attr "tune" "generic") + (and (eq_attr "type" "fadd,fmul,fmadd") + (eq_attr "mode" "HF"))) + "alu") + (define_insn_reservation "generic_fmul_single" 5 (and (eq_attr "tune" "generic") (and (eq_attr "type" "fadd,fmul,fmadd") @@ -88,3 +101,4 @@ (define_insn_reservation "generic_fsqrt" 25 (and (eq_attr "tune" "generic") (eq_attr "type" "fsqrt")) "fdivsqrt*25") + diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 84212430dc0..afa15c433d0 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -322,9 +322,7 @@ (define_attr "ext_enabled" "no,yes" ;; rotate rotation instructions ;; atomic atomic instructions ;; condmove conditional moves -;; cbo cache block instructions ;; crypto cryptography instructions -;; pushpop zc push and pop instructions ;; mvpair zc move pair instructions ;; zicond zicond instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. @@ -464,8 +462,8 @@ (define_attr "type" mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip, rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm, - rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts, + atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm, + vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax, @@ -3649,7 +3647,7 @@ (define_insn "riscv_clean_" UNSPECV_CLEAN)] "TARGET_ZICBOM" "cbo.clean\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_flush_" @@ -3657,7 +3655,7 @@ (define_insn "riscv_flush_" UNSPECV_FLUSH)] "TARGET_ZICBOM" "cbo.flush\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_inval_" @@ -3665,7 +3663,7 @@ (define_insn "riscv_inval_" UNSPECV_INVAL)] "TARGET_ZICBOM" "cbo.inval\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_zero_" @@ -3673,7 +3671,7 @@ (define_insn "riscv_zero_" UNSPECV_ZERO)] "TARGET_ZICBOZ" "cbo.zero\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "prefetch" @@ -3689,7 +3687,7 @@ (define_insn "prefetch" default: gcc_unreachable (); } } - [(set_attr "type" "cbo")]) + [(set_attr "type" "store")]) (define_insn "riscv_prefetchi_" [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") @@ -3697,7 +3695,7 @@ (define_insn "riscv_prefetchi_" UNSPECV_PREI)] "TARGET_ZICBOP" "prefetch.i\t%a0" - [(set_attr "type" "cbo")]) + [(set_attr "type" "store")]) (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index a63394c8c58..52904f546ed 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -34,7 +34,7 @@ (define_insn_reservation "sifive_7_fpstore" 1 (define_insn_reservation "sifive_7_branch" 1 (and (eq_attr "tune" "sifive_7") - (eq_attr "type" "branch")) + (eq_attr "type" "branch,ret,trap")) "sifive_7_B") (define_insn_reservation "sifive_7_sfb_alu" 2 @@ -59,7 +59,8 @@ (define_insn_reservation "sifive_7_div" 16 (define_insn_reservation "sifive_7_alu" 2 (and (eq_attr "tune" "sifive_7") - (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move")) + (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\ + rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,crypto,mvpair,zicond")) "sifive_7_A|sifive_7_B") (define_insn_reservation "sifive_7_load_immediate" 1 @@ -67,6 +68,12 @@ (define_insn_reservation "sifive_7_load_immediate" 1 (eq_attr "type" "nop,const,auipc")) "sifive_7_A|sifive_7_B") +(define_insn_reservation "sifive_7_hfma" 5 + (and (eq_attr "tune" "sifive_7") + (and (eq_attr "type" "fadd,fmul,fmadd") + (eq_attr "mode" "HF"))) + "sifive_7_B") + (define_insn_reservation "sifive_7_sfma" 5 (and (eq_attr "tune" "sifive_7") (and (eq_attr "type" "fadd,fmul,fmadd") @@ -106,6 +113,12 @@ (define_insn_reservation "sifive_7_f2i" 3 (eq_attr "type" "mfc")) "sifive_7_A") +;; Popcount and clmul. +(define_insn_reservation "sifive_7_popcount" 2 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "cpop,clmul")) + "sifive_7_A") + (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu" "sifive_7_alu,sifive_7_branch") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 24b7b4394be..a379ba7439e 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1036,7 +1036,7 @@ (define_insn "frrmsi" (reg:SI FRM_REGNUM))] "TARGET_VECTOR" "frrm\t%0" - [(set_attr "type" "rdfrm") + [(set_attr "type" "fmove") (set_attr "mode" "SI")] ) diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md index 216232cb9f2..462ab37569e 100644 --- a/gcc/config/riscv/zc.md +++ b/gcc/config/riscv/zc.md @@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_push_up_to_ra_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_" (match_operand 0 "stack_push_up_to_ra_operand" "I")))] "TARGET_ZCMP" "cm.push {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s0_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_" (match_operand 0 "stack_push_up_to_s0_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s1_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_" (match_operand 0 "stack_push_up_to_s1_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s2_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_" (match_operand 0 "stack_push_up_to_s2_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s3_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_" (match_operand 0 "stack_push_up_to_s3_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s4_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_" (match_operand 0 "stack_push_up_to_s4_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s5_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_" (match_operand 0 "stack_push_up_to_s5_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s6_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_" (match_operand 0 "stack_push_up_to_s6_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s7_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_" (match_operand 0 "stack_push_up_to_s7_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s8_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_" (match_operand 0 "stack_push_up_to_s8_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s9_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_" (match_operand 0 "stack_push_up_to_s9_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s11_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_" (match_operand 0 "stack_push_up_to_s11_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) ;; ZCMP mv (define_insn "*mva01s" From patchwork Wed Jan 10 01:31:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 186660 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp519022dyi; Tue, 9 Jan 2024 17:33:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IEoUts43Pv/QOFs7oktyIitLe7P1hPuf5ew50BcmIHeMxwRUpEBkn13eArpCfj4mAis+8gB X-Received: by 2002:a05:620a:4612:b0:783:2266:77c3 with SMTP id br18-20020a05620a461200b00783226677c3mr390476qkb.8.1704850412330; Tue, 09 Jan 2024 17:33:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704850412; cv=pass; d=google.com; s=arc-20160816; b=zlm2s36RCzuiVT89rDoN8FatNyCXNcdwUvUsbbItATmePPuLvrHroADqVv9Vz4xBNv m7xFKu29l2fESRpyecQpzoNBb0mtaCUKMdV4S+2/PHv6mEhGcdHLmKylmKZpR2saIY4q Gm5r14rgvn4Qr96/JgHIlbCVgqU8YIno/MXAIK9thiunuZ0yenN6zrmQBhogZDfffdW+ Phr/YVkluhDfjZl+wmMmWddAR4QAtrIxDgbvqoSd2zoZUmNgXNxTgWpXXwdQZkMjALyZ a6LsJGTOLvsrd5ppofYjOLkA7JcFgXi8oN60wx8R0FvdYhLuoTxo8ueFUb0kUAETlK4L T0kw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=osNRHets0YvU4fpPS2xZ+IiqxvAJIINUahgzHCDnBAo=; fh=ANzN1WR3bSeXc7JdDHqJLMrZ6a4Yn0IEU8lUx/TAa0c=; b=VDwTbqx6DLbdVdRY4jrlS7O3ILlIWpa1gG3KXgPzBJBpdYJ6E0vZYhtbsGFvHxhiod MA90OKC5swp3ygYIfMvJWzNGKow3fBtftkayFiZzQbDNtSbepmKeSIq8WYnSF8wxgk41 pvgLRIm7w+u9r1YlPGG5oD4qw/WHGu1WGcsfxuUm2JDa+RnWssyl6BmPAemzDnDLi5NL vr5YOVELOVhQtYrYmnKK4JOiCKbrCxD2GTp+DY4V0DAJYL5QtuWc5Dm3avrwmr1S/med 26WTKCYizisVc8hqw57FGBGkkKg6d6sWpmTQKBikOriCsMR48cmYCniVoz9kjVfaN4EF ZTlQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b="E8/JNz2x"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id u14-20020a05620a430e00b00781795b7cb0si3346599qko.156.2024.01.09.17.33.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:33:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b="E8/JNz2x"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0745D3858407 for ; Wed, 10 Jan 2024 01:33:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by sourceware.org (Postfix) with ESMTPS id 322333858C41 for ; Wed, 10 Jan 2024 01:32:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 322333858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 322333858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::336 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850338; cv=none; b=lMwovvPMWVUthqcGjyPpx+H8odiTdmf47fIrqFbrXvp2lt/UP0jFa1Zk/6MxGPKSLhtVeLSO5X6ihwxNQjYS8o9QR0oq0C7CrbtFHmkvdKuU4+NG3Rjny8bSxwdyvHfDuEtQP4RtpxavoVEEKHjSTCuWPKZDRb2yHoktzbdnCxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850338; c=relaxed/simple; bh=x/ynKF4K0RioDyxe7EthwOwCCJ1CrXHdtDkDlBDjwQ8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=iSEWk/EcmmniywuU9tYp4an4YUzvjKMDCxsv+L6nfEFBOgOBgBdPcvDYiOhgUm40SWJs9ffHYWCq0TTHCxz+gGr5z/e2mAptPFENTR5adZTOqDTukx/QVb36KhXulabpemyRK+OeRI0XREg+EnMII559OKFI2kAHfKjJbVtIvt0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x336.google.com with SMTP id 46e09a7af769-6dde882e5ccso626048a34.3 for ; Tue, 09 Jan 2024 17:32:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704850334; x=1705455134; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=osNRHets0YvU4fpPS2xZ+IiqxvAJIINUahgzHCDnBAo=; b=E8/JNz2x5ejK6HB3wBkzdPb6tojVdOCKZcanOL6NV5WK10oWLZdn7zb5mAdHDi0bYH uUmPqzkUZJuYc6ditu7aJYaHarbu5TDgCwmA3aPkHlzCLdtbpO0TVQBwpVdAIXlYpCCP yt1zUFZ5FNxwcGJHCAx8o8TygpWNGkPBmgy2GXUHA5RK9CVmYhzQkdAkLXt5SvQmbCuz UiWVMUqPvRYdzoLk8rSd3rxKXaI9+3V22RsuOGKlPrFpzRdDj1tHTbU3uxWC+FIQe02y RB7tCy2XVS0PrBp65vlKNjwPE6ssPlBNE7iD0eWeOzOlz5MpcZkhx79HEeh8mlR0bJOM /2Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704850334; x=1705455134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=osNRHets0YvU4fpPS2xZ+IiqxvAJIINUahgzHCDnBAo=; b=IvPB2DFh1gYnUpcvnXxYm6/OudZt0FemjRpNN+77D51TWd7D/Pz6yTNGilg6pwAhlv A1ARxhohqU1JWsYIPnwjLrmPW46PULG+94DM29a98BI2sYTWSrChaye4/1DEDkWm4u0R uCvty9t4e8nMY+2Jkhtw4M+rHXP4s5y2yb2anlQXyPAn1a5/xWDiOaut6Lg0172j5ERw TcSA1waCfC/NGH1AC6WpR8RownNGzLzrBxuFZQfeKJCWz2UXooXYzVumseI5lmmsEHME gTw9BFrHP2pOHlrnXxAlZ33Hy8cx8m1V2lybmTg4PX5dUswBncI4FNm5IWpyRzx1G4Gw oMPA== X-Gm-Message-State: AOJu0YyozR4HG64eL8/x+SQAP7EDwRdKLYdV9MuCAPKw/Xs43trGPyv9 ft/mg/NjXJSZqY+UTOU65XtuRb6X3xQPa/PTAvWt+4nFwG4= X-Received: by 2002:a9d:66d5:0:b0:6dd:e8fe:f657 with SMTP id t21-20020a9d66d5000000b006dde8fef657mr318846otm.74.1704850334191; Tue, 09 Jan 2024 17:32:14 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id a9-20020a9d4709000000b006dc81d1d203sm565423otf.73.2024.01.09.17.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:32:13 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu , Robin Dapp Subject: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations Date: Tue, 9 Jan 2024 17:31:57 -0800 Message-Id: <20240110013159.2645757-3-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110013159.2645757-1-ewlu@rivosinc.com> References: <20240110013159.2645757-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787665225857550670 X-GMAIL-MSGID: 1787665225857550670 This patch copies the vector reservations from generic-ooo.md and inserts them into generic.md and sifive.md. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_crypto_aes): create reservation (generic_ooo_crypto_sha): ditto (generic_ooo_crypto_sm): ditto (generic_ooo_vec_vesetvl): ditto (generic_ooo_vec_vsetvl): ditto * config/riscv/generic.md (pipe0): ditto (generic_vec_load): ditto (generic_vec_store): ditto (generic_vec_loadstore_seg): ditto (generic_vec_alu): ditto (generic_vec_fcmp): ditto (generic_vec_imul): ditto (generic_vec_fadd): ditto (generic_vec_fmul): ditto (generic_crypto): ditto (generic_crypto_aes): ditto (generic_crypto_sha): ditto (generic_crypto_sm): ditto (generic_perm): ditto (generic_vec_reduction): ditto (generic_vec_ordered_reduction): ditto (generic_vec_idiv): ditto (generic_vec_float_divsqrt): ditto (generic_vec_mask): ditto (generic_vec_vesetvl): ditto (generic_vec_setrm): ditto (generic_vec_readlen): ditto * config/riscv/sifive-7.md (sifive_7): ditto (sifive_7_vec_load): ditto (sifive_7_vec_store): ditto (sifive_7_vec_loadstore_seg): ditto (sifive_7_vec_alu): ditto (sifive_7_vec_fcmp): ditto (sifive_7_vec_imul): ditto (sifive_7_vec_fadd): ditto (sifive_7_vec_fmul): ditto (sifive_7_crypto): ditto (sifive_7_crypto_aes): ditto (sifive_7_crypto_sha): ditto (sifive_7_crypto_sm): ditto (sifive_7_perm): ditto (sifive_7_vec_reduction): ditto (sifive_7_vec_ordered_reduction): ditto (sifive_7_vec_idiv): ditto (sifive_7_vec_float_divsqrt): ditto (sifive_7_vec_mask): ditto (sifive_7_vec_vesetvl): ditto (sifive_7_vec_setrm): ditto (sifive_7_vec_readlen): ditto Signed-off-by: Edwin Lu Co-authored-by: Robin Dapp --- V2: - Remove unnecessary syntax changes in generic-ooo - Add new vector crypto reservations and types to pipelines --- gcc/config/riscv/generic-ooo.md | 27 +++++- gcc/config/riscv/generic.md | 143 +++++++++++++++++++++++++++++++ gcc/config/riscv/sifive-7.md | 144 ++++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index ef8cb96daf4..fb5f34c0ef2 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -195,7 +195,8 @@ (define_insn_reservation "generic_ooo_popcount" 2 (define_insn_reservation "generic_ooo_vec_alu" 3 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\ + vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector float comparison, conversion etc. @@ -209,7 +210,8 @@ (define_insn_reservation "generic_ooo_vec_fcmp" 3 ;; Vector integer multiplication. (define_insn_reservation "generic_ooo_vec_imul" 4 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul")) + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\ + vghsh,vgmul")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector float addition. @@ -230,6 +232,25 @@ (define_insn_reservation "generic_ooo_crypto" 4 (eq_attr "type" "crypto")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") +;; Vector crypto, AES +(define_insn_reservation "generic_ooo_crypto_aes" 4 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz")) + "generic_ooo_vxu_issue,generic_ooo_vxu_alu") + +;; Vector crypto, sha +(define_insn_reservation "generic_ooo_crypto_sha" 4 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl")) + "generic_ooo_vxu_issue,generic_ooo_vxu_alu") + +;; Vector crypto, SM3/4 +(define_insn_reservation "generic_ooo_crypto_sm" 4 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c")) + "generic_ooo_vxu_issue,generic_ooo_vxu_alu") + + ;; Vector permute. (define_insn_reservation "generic_ooo_perm" 3 (and (eq_attr "tune" "generic_ooo") @@ -271,7 +292,7 @@ (define_insn_reservation "generic_ooo_vec_mask" 2 "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector vsetvl. -(define_insn_reservation "generic_ooo_vec_vesetvl" 1 +(define_insn_reservation "generic_ooo_vec_vsetvl" 1 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "vsetvl,vsetvl_pre")) "generic_ooo_vxu_issue") diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index 45986cfea89..45c9027229a 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -25,6 +25,15 @@ (define_cpu_unit "alu" "pipe0") (define_cpu_unit "imuldiv" "pipe0") (define_cpu_unit "fdivsqrt" "pipe0") +;; Separate issue queue for vector instructions. +(define_cpu_unit "generic_vxu_issue" "pipe0") + +;; Vector execution unit. +(define_cpu_unit "generic_vxu_alu" "pipe0") + +;; Vector subunit that does mult/div/sqrt. +(define_cpu_unit "generic_vxu_multicycle" "pipe0") + (define_insn_reservation "generic_alu" 1 (and (eq_attr "tune" "generic") (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ @@ -102,3 +111,137 @@ (define_insn_reservation "generic_fsqrt" 25 (eq_attr "type" "fsqrt")) "fdivsqrt*25") +;; Vector load/store +(define_insn_reservation "generic_vec_load" 6 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr")) + "generic_vxu_issue,generic_vxu_alu") + +(define_insn_reservation "generic_vec_store" 6 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector segment loads/stores. +(define_insn_reservation "generic_vec_loadstore_seg" 10 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ + vssegte,vssegts,vssegtux,vssegtox")) + "generic_vxu_issue,generic_vxu_alu") + +;; Regular vector operations and integer comparisons. +(define_insn_reservation "generic_vec_alu" 3 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\ + vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector float comparison, conversion etc. +(define_insn_reservation "generic_vec_fcmp" 3 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ + vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ + vfncvtftoi,vfncvtftof")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector integer multiplication. +(define_insn_reservation "generic_vec_imul" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\ + vghsh,vgmul")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector float addition. +(define_insn_reservation "generic_vec_fadd" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfalu,vfwalu")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector float multiplication and FMA. +(define_insn_reservation "generic_vec_fmul" 6 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector crypto, assumed to be a generic operation for now. +(define_insn_reservation "generic_crypto" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "crypto")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector crypto, AES +(define_insn_reservation "generic_crypto_aes" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector crypto, sha +(define_insn_reservation "generic_crypto_sha" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector crypto, SM3/4 +(define_insn_reservation "generic_crypto_sm" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector permute. +(define_insn_reservation "generic_perm" 3 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector reduction. +(define_insn_reservation "generic_vec_reduction" 8 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vired,viwred,vfredu,vfwredu")) + "generic_vxu_issue,generic_vxu_multicycle") + +;; Vector ordered reduction, assume the latency number is for +;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost +;; for larger vectors. +(define_insn_reservation "generic_vec_ordered_reduction" 10 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfredo,vfwredo")) + "generic_vxu_issue,generic_vxu_multicycle*3") + +;; Vector integer division, assume not pipelined. +(define_insn_reservation "generic_vec_idiv" 16 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vidiv")) + "generic_vxu_issue,generic_vxu_multicycle*3") + +;; Vector float divisions and sqrt, assume not pipelined. +(define_insn_reservation "generic_vec_float_divsqrt" 16 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfdiv,vfsqrt")) + "generic_vxu_issue,generic_vxu_multicycle*3") + +;; Vector mask operations. +(define_insn_reservation "generic_vec_mask" 2 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ + vfmovvf,vfmovfv")) + "generic_vxu_issue,generic_vxu_alu") + +;; Vector vsetvl. +(define_insn_reservation "generic_vec_vesetvl" 1 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vsetvl,vsetvl_pre")) + "generic_vxu_issue") + +;; Vector rounding mode setters, assume pipeline barrier. +(define_insn_reservation "generic_vec_setrm" 20 + (and (eq_attr "tune" "generic") + (eq_attr "type" "wrvxrm,wrfrm")) + "generic_vxu_issue,generic_vxu_issue*3") + +;; Vector read vlen/vlenb. +(define_insn_reservation "generic_vec_readlen" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "rdvlenb,rdvl")) + "generic_vxu_issue,generic_vxu_issue") diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index 52904f546ed..97ec7d0847c 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -12,6 +12,15 @@ (define_cpu_unit "sifive_7_B" "sifive_7") (define_cpu_unit "sifive_7_idiv" "sifive_7") (define_cpu_unit "sifive_7_fpu" "sifive_7") +;; Separate issue queue for vector instructions. +(define_cpu_unit "sifive_7_vxu_issue" "sifive_7") + +;; Vector execution unit. +(define_cpu_unit "sifive_7_vxu_alu" "sifive_7") + +;; Vector subunit that does mult/div/sqrt. +(define_cpu_unit "sifive_7_vxu_multicycle" "sifive_7") + (define_insn_reservation "sifive_7_load" 3 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "load")) @@ -119,6 +128,141 @@ (define_insn_reservation "sifive_7_popcount" 2 (eq_attr "type" "cpop,clmul")) "sifive_7_A") +;; Vector load/store +(define_insn_reservation "sifive_7_vec_load" 6 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +(define_insn_reservation "sifive_7_vec_store" 6 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector segment loads/stores. +(define_insn_reservation "sifive_7_vec_loadstore_seg" 10 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ + vssegte,vssegts,vssegtux,vssegtox")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Regular vector operations and integer comparisons. +(define_insn_reservation "sifive_7_vec_alu" 3 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\ + vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector float comparison, conversion etc. +(define_insn_reservation "sifive_7_vec_fcmp" 3 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ + vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ + vfncvtftoi,vfncvtftof")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector integer multiplication. +(define_insn_reservation "sifive_7_vec_imul" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\ + vghsh,vgmul")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector float addition. +(define_insn_reservation "sifive_7_vec_fadd" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfalu,vfwalu")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector float multiplication and FMA. +(define_insn_reservation "sifive_7_vec_fmul" 6 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector crypto, assumed to be a generic operation for now. +(define_insn_reservation "sifive_7_crypto" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "crypto")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector crypto, AES +(define_insn_reservation "sifive_7_crypto_aes" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector crypto, sha +(define_insn_reservation "sifive_7_crypto_sha" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector crypto, SM3/4 +(define_insn_reservation "sifive_7_crypto_sm" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector permute. +(define_insn_reservation "sifive_7_perm" 3 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector reduction. +(define_insn_reservation "sifive_7_vec_reduction" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vired,viwred,vfredu,vfwredu")) + "sifive_7_vxu_issue,sifive_7_vxu_multicycle") + +;; Vector ordered reduction, assume the latency number is for +;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost +;; for larger vectors. +(define_insn_reservation "sifive_7_vec_ordered_reduction" 10 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfredo,vfwredo")) + "sifive_7_vxu_issue,sifive_7_vxu_multicycle*3") + +;; Vector integer division, assume not pipelined. +(define_insn_reservation "sifive_7_vec_idiv" 16 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vidiv")) + "sifive_7_vxu_issue,sifive_7_vxu_multicycle*3") + +;; Vector float divisions and sqrt, assume not pipelined. +(define_insn_reservation "sifive_7_vec_float_divsqrt" 16 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfdiv,vfsqrt")) + "sifive_7_vxu_issue,sifive_7_vxu_multicycle*3") + +;; Vector mask operations. +(define_insn_reservation "sifive_7_vec_mask" 2 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ + vfmovvf,vfmovfv")) + "sifive_7_vxu_issue,sifive_7_vxu_alu") + +;; Vector vsetvl. +(define_insn_reservation "sifive_7_vec_vesetvl" 1 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vsetvl,vsetvl_pre")) + "sifive_7_vxu_issue") + +;; Vector rounding mode setters, assume pipeline barrier. +(define_insn_reservation "sifive_7_vec_setrm" 20 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "wrvxrm,wrfrm")) + "sifive_7_vxu_issue,sifive_7_vxu_issue*3") + +;; Vector read vlen/vlenb. +(define_insn_reservation "sifive_7_vec_readlen" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "rdvlenb,rdvl")) + "sifive_7_vxu_issue,sifive_7_vxu_issue") + (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu" "sifive_7_alu,sifive_7_branch") From patchwork Wed Jan 10 01:31:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 186663 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp519731dyi; Tue, 9 Jan 2024 17:35:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IF8VMZh95yjGxeo9uaiASrEMYN8e/gZCkswjgqVOau/2jQtNppMmttREZ5PM0MhkrfAgaXP X-Received: by 2002:ad4:596f:0:b0:681:924:3f05 with SMTP id eq15-20020ad4596f000000b0068109243f05mr431955qvb.30.1704850540054; Tue, 09 Jan 2024 17:35:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704850540; cv=pass; d=google.com; s=arc-20160816; b=wHcSZQUF0csJQoM5JcfUBkdKlfan0Yg8E9Wav1VdUgUvTyNmmaRFYdZMUFVKm79j7o WNKkqzODun4tyQYvq6MQToEsDxQsuPjNtcXbzUCiHd945/XRU+NqqxOFYaOby2L2N2cs 7tMP3p6+LyDAt84u3PajbX/jP61tis5UUdcImqgacDTgtri1cqWvfg1Ro5+ZvLkqXJJ5 dD2WRqlYDFMRI2k6TDqL7Oe3Srih3+6CEOp1paVh4LoLvv1NElYFGqf6nyyxtEscocW4 /T94dmax5Af6ybMNWnpLbsF/AA/USCPe+3VzrV6Cf92P/E2HgYplJmcvxLBMe3CMfR/U JGMQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=1z/V/42ULoRVZzJFwmLbhUTqnbNmbQmtpSLL+fCrlEo=; fh=r+SIYcgLopsTG8D0vSkuNNcbfbLGreWBAuINt5YEr6Q=; b=T8VyCGBM8wvTZ55KKHOqW4X0USl2FLOqaGZB1zlXKPeKI15abfyxSvPVoIDZ/pmvTq AhxjwiAO3oGu0k6NaGDBqGQLgVqFfR0d/MwsMj3swo9R7lICEKAsBHb+F5Lgg9qqummi o+f5ShaVUV95Xsgik0q8hDMoodXZ79RZH3WmEnw6LYTWLeQWgst70cTiavC/TvVitVPK ig014y5R/f96Xsg95/0/+fdh9BwZWPLCw8PqiVZUH/a0OwqssK3Mhb7Rq+rNrv7j3XFx Ms7pGxwu80h7xucPJeej463W7g+MDfa24J5xniRkYbtlXLJBkH1WZa7i4PSHkP+2FrZ6 KGeQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=0PEMZBBd; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id b12-20020a0cc98c000000b0067f9fd8e2afsi3433064qvk.376.2024.01.09.17.35.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:35:40 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=0PEMZBBd; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BA75138582BF for ; Wed, 10 Jan 2024 01:35:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x334.google.com (mail-ot1-x334.google.com [IPv6:2607:f8b0:4864:20::334]) by sourceware.org (Postfix) with ESMTPS id 8CC7C3858C50 for ; Wed, 10 Jan 2024 01:32:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8CC7C3858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8CC7C3858C50 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::334 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850343; cv=none; b=YjM5F8JwmurQ1oqPpbRtTp0K5yI0zXyPfZlTMpBjXEduk9wYXYXYiZoSC95D1MEBhlsniwYXyD2E7bJpJ4FuIKcm7nZDCV2AGU/Gv9ZmdBlyEMvYnb1vvi8ULzK8+4AfOKYcyUL6At0romG8KYIwz+6rpABBX1+0wzZg1HgSbAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850343; c=relaxed/simple; bh=qPCbCcetPltNCMEoqX2+FCGmKNH6tEeF7VUb5Rc2064=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=cr7z8vUO5pHfSMDTdomvQScrkryc4naUu0hxEGaEy6r/z8A/RFQuYs5iRA0vbp04286tVP2hgasQusQePeToMYDktsQ7vAc32Kpd81mKLHrc+e7DW02kyy5GHUaFttaiMsfq30/quuajb2TRZVx3rOaHjbwXCDUWV5CyRpYWkks= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x334.google.com with SMTP id 46e09a7af769-6ddef319fabso251813a34.1 for ; Tue, 09 Jan 2024 17:32:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704850338; x=1705455138; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1z/V/42ULoRVZzJFwmLbhUTqnbNmbQmtpSLL+fCrlEo=; b=0PEMZBBdUwfZOKhCC+W4Qo/RzctJe17UofNuFr7J1QHfQSDKvNdbZR/NyTqaX3U42Z hKQGMCNERYTnafzR/7+NzX5pUzeErYdTi20+RxlqG0Hoj1ovWlMT0XHga4Z9qEeTlwtp HdxAM/0YFPGa5bV6JTBKGUnj3jrRtEPvFlwG5S1xKcviRv1tTAapScB0czlMNnmb56jo ZBw6Xo0M9gtA6PxCjzUmJEz0OQXFUzAAdDQlHpIz4inn++1f3UypEvkQ8OhorlcD8SE9 oJrN56W6/ihnif8MpTutFDcHPmEjGk83hnrJej3WIje08WGF36IOiqrhqXNjExUCWxvd VhmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704850338; x=1705455138; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1z/V/42ULoRVZzJFwmLbhUTqnbNmbQmtpSLL+fCrlEo=; b=JRh0xPcDxxGSPEhuyykerkPHstvl34C83cxcps8dMuFdZ8Inu8t+yC/bXn40wWDtF9 g6UFuxgkJdAEamGZTOBHmtXDmq+83EA4WKZzz6c3ziS5ObtO9MlAe1z+POgi3VWrmvkg R6uqZfPH0WNbi+WG4ckAHxeNXfhwzkb5v2YN0DlKhcHTinyKp6wuFDg0ugG9jDs3Qwxe AgMMKpZMGAyGcgmD0dNJHfP50SLwjhEj5vs99p9+XnVbk0sF62/YymfjGlYqFZJynVar 4z6dmcEVsnRyoFgZxs02teMMQhZCrsMvGzaydxWIoKv23hE5isgysEVz6/DO7WZelMfe FCXg== X-Gm-Message-State: AOJu0YwhE9Pax0S2g4mVgz5PZ10ewV0AonFt7CAkcBsG4qA9rkMMUpv4 PF8Z0OjYPUKILzypv4rzZ9GM0ULOTG4NX0Fd1+CXpdvVRbQ= X-Received: by 2002:a05:6830:1dad:b0:6db:adb6:a857 with SMTP id z13-20020a0568301dad00b006dbadb6a857mr289524oti.27.1704850337064; Tue, 09 Jan 2024 17:32:17 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id a9-20020a9d4709000000b006dc81d1d203sm565423otf.73.2024.01.09.17.32.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:32:16 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249 Date: Tue, 9 Jan 2024 17:31:58 -0800 Message-Id: <20240110013159.2645757-4-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110013159.2645757-1-ewlu@rivosinc.com> References: <20240110013159.2645757-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787665360086940396 X-GMAIL-MSGID: 1787665360086940396 Use default cost model scheduling on these test cases. All these tests introduce scan dump failures with -mtune generic-ooo. Since the vector cost models are the same across all three tunes, some of the tests in PR113249 will be fixed with this patch series. Unfortunately, 40 unique testsuite failures (scan dumps) will still be present. I don't know how optimal the new output is compared to the old. Should I update the testcase expected output to match the new scan dumps? PR target/113249 gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/bug-1.C: use default tune scheduling * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto * gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto * gcc.target/riscv/rvv/base/pr108185-1.c: ditto * gcc.target/riscv/rvv/base/pr108185-2.c: ditto * gcc.target/riscv/rvv/base/pr108185-3.c: ditto * gcc.target/riscv/rvv/base/pr108185-4.c: ditto * gcc.target/riscv/rvv/base/pr108185-5.c: ditto * gcc.target/riscv/rvv/base/pr108185-6.c: ditto * gcc.target/riscv/rvv/base/pr108185-7.c: ditto * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto * gfortran.dg/vect/vect-8.f90: ditto Signed-off-by: Edwin Lu --- V2: - New patch --- gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-17.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-19.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-21.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-23.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-25.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-27.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-29.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-31.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-33.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-35.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-40.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-44.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-50.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-56.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-62.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-68.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-74.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-79.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-84.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-90.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-96.c | 2 ++ .../gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 ++ gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 ++ 58 files changed, 116 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C index c1070f9eb16..6f62a64224d 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" template < class T > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c index 7be22d60bf2..17a6b6f27fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c index 4b24b971cba..8386b42e9b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c index 99acc51b4ff..e2ed4b76a16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c index d595c446503..61340be8362 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c index 0b51175f66c..0f1485e3c0a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, uint64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c index 634c12a4c0e..173ac625ada 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c index 651d61001c1..1edba8980b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c index d19a9fda235..75340c3da6c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c index 16f431542d8..7e4aedc1cdc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c index 347c846dcbb..755e92a9cd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c index bc414440ba2..2c82dc0688a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c index ce3f3af9c3d..e2ac6a3d9e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c index 4946f84b916..436a0e85f3d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c index 5f2eede0422..72b321607c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c index 5f2eede0422..72b321607c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c index 88fcba60345..6908c78e19b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c index 88fcba60345..6908c78e19b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c index 87a16453fea..ee1db1c41ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c index c0321cefb9a..fb969eb50a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c index ab0f13ba255..542f43eca49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c index 3893e17511d..31109a81ec3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c index b0ea553bf89..924f4507ba3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c index 350697d764d..659d8d9e702 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c index 0f138c5d3c6..63874605759 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c index f4cbf095357..a214d70cb2c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c index d606078e85f..efa659b2752 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c index 9bf9ff59de7..6a26248096d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c index bca55b239f9..429fe129003 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, uint64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c index 586e26499db..0cd0af76186 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c index d1bbb78f5ed..bb1690e81e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c index bf5772073f7..5b666a920da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c index c3d0b10271a..4c6e88e7eed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c index bd13ba916da..0844e3e8713 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c index 99928f7b1cc..49a574485fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c index 321cd5c818e..cef0a11b2d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c index 575a7842cdf..3f0d67726bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c index 95a11d37016..4ed658899f4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c index 8f6f0b11f09..95b7ff97666 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c index 250e017cc86..9e0b41ccba7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c index 110e55b3cbe..5e1859cd13b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c index 4583504bd5a..f4f0e52971a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c index f16f4b9c37d..7e01b81682b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c index 43b443be6cb..5615cb1f97f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c index 67855581fb2..c906b153ab8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c index 960c9bff765..006df7edf8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c index 5f22e8d0e8e..cc6d8221516 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c index e5f35c0f018..9704e444d54 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c index 0532c7d4207..476735dcb2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c index b664c4b67eb..c7b7db33849 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c index 04c4b886eec..80ff75f6d2a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c index 1404c9dc0d5..127dc7ff06d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c index 1404c9dc0d5..127dc7ff06d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c index 609c68dfcbe..e19e869e241 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c index 043f17737ae..90eca5b1ae6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c index 0bedde84005..17b217bc82c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c index 0bedde84005..17b217bc82c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90 index 938dfc29754..f77ec9fb87a 100644 --- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 +++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90 @@ -1,6 +1,8 @@ ! { dg-do compile } ! { dg-require-effective-target vect_double } ! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" } +! PR113249 +! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } } module lfk_prec integer, parameter :: dp=kind(1.d0) From patchwork Wed Jan 10 01:31:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 186661 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp519379dyi; Tue, 9 Jan 2024 17:34:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IHQt4F7DS2sphS0J9vXvOytXRQZk4BUXPWw8c6JGONTWMWlTdVxVW0AXwXHZVeTJtD+/3mZ X-Received: by 2002:a05:620a:2792:b0:783:1567:8826 with SMTP id g18-20020a05620a279200b0078315678826mr340288qkp.30.1704850476165; Tue, 09 Jan 2024 17:34:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704850476; cv=pass; d=google.com; s=arc-20160816; b=FLRYzF5qUajFLDwK+Po24tX+qb00cje+Whyzd0rsZ6eZf3sVGByItCDM4uIcrI4n9K HiDiG7gQXSnhvOoCOAZLfK6LZy/aOd/W6MG/QHrRd9tMj9II4Z9ryz0QaYkyGJTXUtI0 x6bJRPw9VwpwA3U1qMn1VgnJ9yEHKXkoS+zG4SuiYh3eLsjb+eieZ61E172k/n1MTxHN 7OUyi4B9tZW7jj7hZ2wiKdBDzdyHnHTwG0HVJYKVmksP6TvXizUBnyplyemGtYGDxsK4 n6LNF9IY/b5qTVOFbrrlepqYaEJMXyjtU5GJ8jHHdvRRZjnQgu7eL4VjU5maHebPdxPA YhxQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=++kFcIdrCJcOrBFKyqFfbuaKSQqveMaYPEHiI5uIcXs=; fh=r+SIYcgLopsTG8D0vSkuNNcbfbLGreWBAuINt5YEr6Q=; b=YVNwtrckQ940cZ9n/mX1LQqPgbtZ+jz0iOAxuE/3gduUKHzBqU1/tDJjhBZgsNQHo1 yfodGfU1GrXMtvBGKyTt+9pWeLn+XnKOYGVXkjVTbDInKCsX18R+9Bd1YdLYBOV4i/GO 7nAdk9YdE5dSfPNnqrU+PwcZuowOf/2QrJF/jGdackpVB7K3pwxoFj4x7MeLEMU3YS9p KmD68ncPOFVhRpUY/VGLTIyHXozCIjjNSocomXkIg/q1xwetgMfnbvvxRelyQvF1R2pM uuVlkh7h9YBPpYn4Mkjlq0YYzAKud0JTd5+GvkAbCfd2vz2PoNTP9X/95wQtfGe8Ys4u 7kiQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=NE74diNI; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id oq47-20020a05620a612f00b0078314f7fb63si2940843qkn.396.2024.01.09.17.34.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:34:36 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=NE74diNI; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D486D3858D33 for ; Wed, 10 Jan 2024 01:34:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by sourceware.org (Postfix) with ESMTPS id C53E43858C52 for ; Wed, 10 Jan 2024 01:32:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C53E43858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C53E43858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::32b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850342; cv=none; b=bwhnimkmIWZgBTf56TiR39aisjayxVlzgkj0HyaTH7gJdMosQFtsnT9j/oBnzANaeAyZHXYTA0dHLKbM0mEg1f5x2P2A2tTLdirr7c4PNXDFwOHh2+E/Ggoyef6HAM2KtF5nj1Lf3WY6pC/yqT3YYDgt8KwaPqb6L2GQ6GnCbjo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704850342; c=relaxed/simple; bh=TAmk0UWjVKDFk2ul+1pwhui1ZSEWpibrUjy3mLDsbAg=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=OjXNLPUKjdfnRWEQq/5L+O/ALF7H6j6+iNj/Bfc1FvNwjHj0jqt8t2plVw3rVkwoDl1ajdlR1p+f+tZnRnluK9rhmjPnpYAAU0Md8WnwYZUV9eHNKvX5Wwe294uAU3Ijllcgp2QK+4oDnk8etAi4D2J/OGBeb7zEoXdUgwrVN7M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-6ddeec84e35so299564a34.3 for ; Tue, 09 Jan 2024 17:32:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704850340; x=1705455140; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=++kFcIdrCJcOrBFKyqFfbuaKSQqveMaYPEHiI5uIcXs=; b=NE74diNI0H+r2wKFy+Dq77XR6am/nN8HuVQBsL1OB1gnVhpdnhtAp9zYq5nG9T7hU1 lutehsT/pWtOSFoHfHZGg1ayDX5NL4qpT6uXf5pMo0UNi7KyfNmKBz/KLApwYnUOWc9z /RVyng3qMsCH6DU+X+/l96vDIi5fAS4zjoidgbhUHvwiCywQtX2bxY0Nr9stSO+kdAey wXL6NEpf9EXsSPxhb+HUgNN63Wi+3QSI1aBS5aZhHGrwPwB5vzCZ7/KSH45rBSAgPIRK CvClCKb/w10qcNNHveHJEId+lYv2mgBGLBO79ICJ9MGiDQwQR9xcEOolno/8HMPSkTsd Z7qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704850340; x=1705455140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=++kFcIdrCJcOrBFKyqFfbuaKSQqveMaYPEHiI5uIcXs=; b=nE4HR4idS5Crlstnnc1EhgTEtaHAsKeBNrslPZvOAi98aM3vSY9eX/50eyHne40R9l OkxH26xI/C+TebohVa6c3vdnAXGYMXmIUcmJQPFlAZzDxyVV2JxQNy7jq7ka1AaqY2uP obYbslmc88aTradztEwF8rRqQEZjEvpHzZUm5Sg1jtuIvbULLEds2AFvUNSqshMW13B5 VoXvoREKtBt7hO5uIS0rvrfToUrxAG1rdshw8KMWl5cnw7ot7x7Ouy7jTpHJeBsrHM41 /e+vncnmv/83x9QxSKkoWaKtgaJIbqV6zeH27KHNVVYOsxERtAzSm9yoRNAPtYOAWym9 ERAA== X-Gm-Message-State: AOJu0Yy2+voqrjPwSb+6v3i0uKaLbYKYqePXP7YtkKxoTYWfsTfvxv+k wFNWwjqUcJxSVsneJVfb3nzJFq6TbboHxPrFMVa8zZnJBXk= X-Received: by 2002:a9d:6e0f:0:b0:6dc:2e3a:fef6 with SMTP id e15-20020a9d6e0f000000b006dc2e3afef6mr210543otr.56.1704850340133; Tue, 09 Jan 2024 17:32:20 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id a9-20020a9d4709000000b006dc81d1d203sm565423otf.73.2024.01.09.17.32.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 17:32:19 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation Date: Tue, 9 Jan 2024 17:31:59 -0800 Message-Id: <20240110013159.2645757-5-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110013159.2645757-1-ewlu@rivosinc.com> References: <20240110013159.2645757-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787665293004948086 X-GMAIL-MSGID: 1787665293004948086 Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert Signed-off-by: Edwin Lu --- V2: - No changes --- gcc/config/riscv/riscv.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 32183d63180..e275fcc2245 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8150,9 +8150,11 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) /* If we ever encounter an insn without an insn reservation, trip an assert so we can find and fix this problem. */ -#if 0 + if (! insn_has_dfa_reservation_p (insn)) { + print_rtl(stderr, insn); + fprintf(stderr, "%d", get_attr_type (insn)); + } gcc_assert (insn_has_dfa_reservation_p (insn)); -#endif return more - 1; }