From patchwork Sun Nov 13 18:13:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 19397 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1782435wru; Sun, 13 Nov 2022 10:14:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf4/4RPWmRD3X84AdpY3IXASfilkOqKr35hYDVwMuP2t4TW7J9/NoWNFJrm6FPhO+8jn6in5 X-Received: by 2002:a05:6a00:4ac1:b0:571:8e12:3ad3 with SMTP id ds1-20020a056a004ac100b005718e123ad3mr10744382pfb.71.1668363250077; Sun, 13 Nov 2022 10:14:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668363250; cv=none; d=google.com; s=arc-20160816; b=Zgj20DD9iosE6/QFQ0e6GpEMXUHEAE+KQvEvmklGcrniBuaVT6nBSEzftq49PVSYI3 LrXPL7hW90Q5XORMOD+Au/KeIAQ8TRETrCBnMvdwNiiP1mW6qI6h5BnML6n8V/5rVVAF kfpTmvwpY26MWYJj4y1Ik3wnI6Bl37IJ6oOSz6GvfWO5zn3xm8v3pQuFe5J4ZjCOno4S 5RwVko91OswHPyX+FvTbmBYZYbowSo0dP65TjilUM3n722QW0TwE+2bfVhh1n0LAG6NS MdtWZu1/esiEw7l3XWHWyAIlaHMTY4fBKF0nW4vtVH1XkUQCyv1LnGIZkHBtApj2eU0Y 8zFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Wd7qt9Y69GxtzzaG+0eDdZVNxTR8osN5UREXRUPZGYY=; b=o9eMH8N0bAkrBrN8/8/Sp072qUJs398FUKLxEc+B4GW6BKaqV3d0tvJ/g1M6gNjBpb qWfoOY5h0CfyTihy5Crroq8q+oRRhxbFeKuwz6rbZgImop1Gab0qqS2TAL/jXLB8kCIK SJCGD1QSnlAaJDSI6u89IlNqnCZaqSemjj46Q6LniEQQGsuuWLAt53KVbeMRXidPsM0k fIzsYpG8ywf1xt1//c4KW3DOglsRXmQN3CuqkkIghcghSsDVr1zsGPaq1JA8AxJtbA19 WHtL56JiQA9mka/mXjNEa9m6cBMupIR+6xuBaaiG5bkgbvUjOu7JjtRATc4uwHlTldEt TNIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=r4iRi3u3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 33-20020a631361000000b0046fbe60747asi7736474pgt.594.2022.11.13.10.13.56; Sun, 13 Nov 2022 10:14:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=r4iRi3u3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235490AbiKMSNm (ORCPT + 99 others); Sun, 13 Nov 2022 13:13:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235474AbiKMSNg (ORCPT ); Sun, 13 Nov 2022 13:13:36 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF7F5640E for ; Sun, 13 Nov 2022 10:13:33 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id k2so23469652ejr.2 for ; Sun, 13 Nov 2022 10:13:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wd7qt9Y69GxtzzaG+0eDdZVNxTR8osN5UREXRUPZGYY=; b=r4iRi3u3f673NIkdZ3T0jiFFltpdfE82+xUBTwgsXeRfYRzz5dKJLaHp/2urJCzPW1 k4KBqywiSJFEzrXn3j3cvHI/fDcXloQk2SvCmNcGPM0Ccb15eq8kA3HuHdsUzdyUtEtB /phHo37+5AHff6OgCqKs86m06FwqfzZPH94jY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wd7qt9Y69GxtzzaG+0eDdZVNxTR8osN5UREXRUPZGYY=; b=x9P00JCH7axGdoB8XDGytomH/IFuDwHWcdUwfYFszjHF+0Yj2DxIg/ljqKPDm4PvSS HRLKVtm7KPRw/6fsawURY0essRmIZZvOfCD3EK5L13+ALpZTPd0Sj9K6LksZkFmc12OI JewM6X2baunjQYy19oS1eo7d3T61TqCR23vmQY+p7Ty3wEXbaKHJ8fZAR1LOJ0RfRnEi FrQ5S+8b5XLAPeGWDYFdkPgn0uud0wFrSU0WnOW39AXVTrNy3KhrXX9kxJY850vU/s22 pX7FTZLNy0IiODz7PNELePtwLe+SmAirNalCfk3XX0I9PA7nhd7b1StgbtLh01Xgo4QY zPYA== X-Gm-Message-State: ANoB5plhyYuZ464j3eZbRPKk9VAFZlLGp/4mPp8t+jxqDCz6mt443F/Z 5iBiCXoo50z31MdprOz9KfZcHwGmijWunA== X-Received: by 2002:a17:906:6843:b0:7ae:65e4:7204 with SMTP id a3-20020a170906684300b007ae65e47204mr7780374ejs.579.1668363212177; Sun, 13 Nov 2022 10:13:32 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-40-103-33.business.telecomitalia.it. [79.40.103.33]) by smtp.gmail.com with ESMTPSA id iy6-20020a170907818600b0078de26f66b9sm3225487ejc.114.2022.11.13.10.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 10:13:31 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Marc Kleine-Budde , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , Christophe Roullier , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND RFC PATCH v5 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Sun, 13 Nov 2022 19:13:18 +0100 Message-Id: <20221113181322.1627084-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> References: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749405663288177090?= X-GMAIL-MSGID: =?utf-8?q?1749405663288177090?= Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi Acked-by: Rob Herring --- Changes in v5: - Add Rob Herring's Acked-by tag. .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 6f846d69c5e1..8646350dac44 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks From patchwork Sun Nov 13 18:13:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 19399 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1782506wru; Sun, 13 Nov 2022 10:14:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf51Qv5HM2Mu8IKACLVMtJcQI8Fvd+oZsO2QgfSww975hIbNz+Bq+GgTsMyrnDiCN9K1KfSv X-Received: by 2002:a17:902:d191:b0:186:c483:f017 with SMTP id m17-20020a170902d19100b00186c483f017mr10931892plb.136.1668363262773; Sun, 13 Nov 2022 10:14:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668363262; cv=none; d=google.com; s=arc-20160816; b=IkPV2BR0fQb9l+KEpMCH3M/OxefmIW6dONJPeYqzo/Oh5mG6mKPXkOlZBa4UpcvvyW 9jCJsgl/Gxkokp3smIauGy6d1o4iJKmU1FF6xN/EVHLsprOgpM1ezQgfHMGMHXnObH8W cXDtEyikE21ApditH2BQ4LYMiPGfuq4UchLjrb2vb0LFg8lFJLISz7NGMgyGJWR3pcwc FujKWXLRhKFuKDLKhvcS0b3tFK1pMuxSZJNw22pNupRdl7WGK9Xh0ZVApA/JJWl4jBZu ngPPkJALmMaWPQAfPZTYCe2SzX3deb9ObZmKIb8JQgwrBKWvJG06N7C0qKcaxY4IPNiS sRWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D8/Md0NYJHUSKcz4MJWTxhKaskWW/ctRpyjjxqRRhnc=; b=d6OS6WUL2fwiXTRcirY9S2/QeT3+kHR7U1WLGld9lBqE6yCfIIf1zQNUmgiiPir8Sy 5BBjGCXI3nAckK8+bAORRmxs4+QWOEhS/nA32LtSBaoewKPiAtUjVx88mkjaGxgtzOzw 2Nrr0+tphuoScY4lwWPiYFQXx7BIuu1zbgz3DDBnJ9zx3fQAAWd75fM/OOaw4en89WeW 9qg4O50HJGFs7ephJnuTPH0AATFTnr5Ug2/JMdOWoE7/huPbi4xRxlipskhkvIvKtuaY turJKdC1UwQyQOcYqEVoA95wmPnDsRpRgUzSqcxDjQlk/vgtr0S04LDFumFbyXXbdv0L GElA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZOmYYgrE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c18-20020a170902c1d200b00179c921918esi7705782plc.17.2022.11.13.10.14.09; Sun, 13 Nov 2022 10:14:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZOmYYgrE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235521AbiKMSNt (ORCPT + 99 others); Sun, 13 Nov 2022 13:13:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235483AbiKMSNh (ORCPT ); Sun, 13 Nov 2022 13:13:37 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6731A64DA for ; Sun, 13 Nov 2022 10:13:35 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id f5so23420315ejc.5 for ; Sun, 13 Nov 2022 10:13:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D8/Md0NYJHUSKcz4MJWTxhKaskWW/ctRpyjjxqRRhnc=; b=ZOmYYgrEGoVimA2TEfidyVQgl7KwexHNHm+svvev3mYj94RrJx9jxXLI+SRn2X05S6 Q99YX4bhsALtW3GQZdqYRzwitFsbhTXlF8jNOePfnjudIoVPFDFqwv/2Zm30AvuJ4MlQ qhjfB8i4c9xMAR13TW0wLXDJqheW2bM+CLRUo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D8/Md0NYJHUSKcz4MJWTxhKaskWW/ctRpyjjxqRRhnc=; b=Kfho56f/p/259ACTtVD5QCZnuCo0TwA2qxBqAySc2rHmNq9dS0GckdGYFolKI/NIhj vk5+QsuGXNNI20Rz0QnyZSNLjP1wGnuRsq06etKPKVyEtPIB4B6LAgEbDmieCkO4K2qS xo31SGLRhX1gf4RyY2a7Qkc2vaNYPwW2h6U7JrDNm/zMbZ9ClsubyrTo2HEes/khIIm9 rZa8VORnHhmanB45xf7zZmruTSBGbRyOuf2l28ZxHOmprw3AFEJrYm+7Au7Hro7jWtsX K20ao6p2zdmX13Xh1mTuUtWUlSF82RoGAL8xVdDqfLOAVDuL77CrzpnBso6WSOVNoIJZ SUww== X-Gm-Message-State: ANoB5pn0fSc9edanYX2dW0NxVHykDXX895x+Ae5xHQFTjXDkKzFLMdqG V0wSabpKMIvs5uZAKCfqfG13KFl3AOm1jw== X-Received: by 2002:a17:906:b855:b0:7ac:f8e3:d547 with SMTP id ga21-20020a170906b85500b007acf8e3d547mr8089231ejb.53.1668363213667; Sun, 13 Nov 2022 10:13:33 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-40-103-33.business.telecomitalia.it. [79.40.103.33]) by smtp.gmail.com with ESMTPSA id iy6-20020a170907818600b0078de26f66b9sm3225487ejc.114.2022.11.13.10.13.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 10:13:33 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Marc Kleine-Budde , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Maxime Coquelin , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [RESEND RFC PATCH v5 2/5] dt-bindings: net: can: add STM32 bxcan DT bindings Date: Sun, 13 Nov 2022 19:13:19 +0100 Message-Id: <20221113181322.1627084-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> References: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749405676353909306?= X-GMAIL-MSGID: =?utf-8?q?1749405676353909306?= Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- Changes in v5: - Add Rob Herring's Reviewed-by tag. Changes in v4: - Remove "st,stm32f4-bxcan-core" compatible. In this way the can nodes (compatible "st,stm32f4-bxcan") are no longer children of a parent node with compatible "st,stm32f4-bxcan-core". - Add the "st,gcan" property (global can memory) to can nodes which references a "syscon" node containing the shared clock and memory addresses. Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add description to the parent of the two child nodes. - Move "patterProperties:" after "properties: in top level before "required". - Add "clocks" to the "required:" list of the child nodes. Changes in v2: - Change the file name into 'st,stm32-bxcan-core.yaml'. - Rename compatibles: - st,stm32-bxcan-core -> st,stm32f4-bxcan-core - st,stm32-bxcan -> st,stm32f4-bxcan - Rename master property to st,can-master. - Remove the status property from the example. - Put the node child properties as required. .../bindings/net/can/st,stm32-bxcan.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml new file mode 100644 index 000000000000..c9194345d202 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + enum: + - st,stm32f4-bxcan + + st,can-master: + description: + Master and slave mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share + some of the required logic. + type: boolean + + reg: + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + st,gcan: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + The phandle to the gcan node which allows to access the 512-bytes + SRAM memory shared by the two bxCAN cells (CAN1 master and CAN2 + slave) in dual CAN peripheral configuration. + +required: + - compatible + - reg + - interrupts + - resets + - clocks + - st,gcan + +additionalProperties: false + +examples: + - | + #include + #include + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + }; From patchwork Sun Nov 13 18:13:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 19400 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1789201wru; Sun, 13 Nov 2022 10:37:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf6EbMiHPYqa9md7X49j8GH7FYicWoJO29FYJ0bf2Vn8NVauO6dVeRb46I5SobMz80JhpT6e X-Received: by 2002:a63:3343:0:b0:46f:c182:b658 with SMTP id z64-20020a633343000000b0046fc182b658mr8832408pgz.182.1668364634264; Sun, 13 Nov 2022 10:37:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668364634; cv=none; d=google.com; s=arc-20160816; b=mb+bGE417nyZjHMIXTjgJr5ix9NiTQTnfpP+C7ZXSHL3ZuXeUc/ypsRWocwB9csRhp dVsDLzi5chU/lnz/LK/D9qGoztQp6W1kZqIs6UFMVKPzz0rECESzsM4zRMfJzGFzhb0P 7MTEhHa+AXAkCsocqIXZDozc4d/JfGKz4p9UTxgpk4p/1xE83d5OPCexjRGGJ0SVO2Yq W1/bb9Wejl5U5FTS6IE/5jNK3/nmLLRObsU+4g/kywgI/+OqqVao5gzqxsF4yGHurksk oSK/3r8y1KiG3P9CRz5izAMqM85YDTYOBq0SwJaZuv2veFyTB5EK+b0FfVfIA2LIsPW1 tvGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ytjq+5ZqtJJOKrYEaXmPKz3aw/q9ijl/XXCtqz4EuF4=; b=qW+vhs8ahXTXPSHjlt5qLatAWtLm5gvJRfC4jz4Ram+PDsDdbLH6tCm1pfI7EIl6wI PypBQiYQcXYtss11NNf21sszFQvKNZpt+flxuP84kvMud2qEKkUzeGx4+oLxRVjmgjrG K3d3EM9yBjkAl/SstFZ8l3EJSl73Pvl4aaHdUaEREOSvEiKhFumryXMTvbOI4gIQj1Q0 m0iZq0L86Z6m/uWQMVkWylDWWxBDSuq1GQNnmJake6KYSZKqtsrplH15ALQqKUlGNC/0 jLVdlo8rUlhynfyAoNmlsqARXrz9cyw2uRGN5lClqZbrJ4B4Er7FFpInNz53Q/LPs+dM ByoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=LcgO6u9a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l191-20020a6391c8000000b004703fc2ac2fsi7888550pge.877.2022.11.13.10.36.42; Sun, 13 Nov 2022 10:37:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=LcgO6u9a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235529AbiKMSNz (ORCPT + 99 others); Sun, 13 Nov 2022 13:13:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235467AbiKMSNh (ORCPT ); Sun, 13 Nov 2022 13:13:37 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945616352 for ; Sun, 13 Nov 2022 10:13:36 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id x2so14321405edd.2 for ; Sun, 13 Nov 2022 10:13:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ytjq+5ZqtJJOKrYEaXmPKz3aw/q9ijl/XXCtqz4EuF4=; b=LcgO6u9aDFX7W4e8I8fmr7EsdAQ0E8Uj9NyZCEZC5m8WQeZEPixbQydwqSxn6eMXlz 96Gyr9JqWxyZ7oJyQpZgyZqHm4kxNd+GsnWlDOtRWIlEqyHjtRNwdl0vpIP5Xmp0qMTV 2gwe1DAQVJOB12fCoDNE0xvMCTlWE0mcYV+nU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ytjq+5ZqtJJOKrYEaXmPKz3aw/q9ijl/XXCtqz4EuF4=; b=GklNctGyA42kBZLmaXhnRStmP/LRoTi+oop9RUXS2HL0GwvtIw99mx9zK1L+LTCS45 TrJc6Lm3v7OJ2LhzGFLL+Bbff8Va/YiSTD8sFppz0Ap3nkYqSiL7QMKAu7xbj4n3rGhB ZN5tfQaM4E70p8qh5pT0RIPIs2PM84OZ87tVIM1gdkTXMyM3u78sIZ6LZec7RzBGDhpS kJh9N+outNEiA8STi9eZn9Zm6POBgPPkZdGp74Sm3/Td0x5w1yyAWgsPDKDZE+oVe/x4 L6KdsfpQm+cllQqoKQNoTMSIyJI58wpsC131c8xdecJikxrvOJtjDMCwol4feaZrRUQA uASQ== X-Gm-Message-State: ANoB5plCFZvqqTU1CORM3bTkfbY+Uv/24zcko4isdPBY/Hg0uv6iM5F7 T5SLSM+BfFi8SKbMr4xa59SIRusWuq3Jjg== X-Received: by 2002:aa7:cd13:0:b0:45d:2a5:2db8 with SMTP id b19-20020aa7cd13000000b0045d02a52db8mr8700763edw.105.1668363214952; Sun, 13 Nov 2022 10:13:34 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-40-103-33.business.telecomitalia.it. [79.40.103.33]) by smtp.gmail.com with ESMTPSA id iy6-20020a170907818600b0078de26f66b9sm3225487ejc.114.2022.11.13.10.13.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 10:13:34 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Marc Kleine-Budde , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND RFC PATCH v5 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Sun, 13 Nov 2022 19:13:20 +0100 Message-Id: <20221113181322.1627084-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> References: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749407114751629498?= X-GMAIL-MSGID: =?utf-8?q?1749407114751629498?= Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the master and CAN2 the slave, that share some of the required logic like clock and filters. This means that the slave CAN can't be used without the master CAN. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..ce08872109b8 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + status = "disabled"; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; From patchwork Sun Nov 13 18:13:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 19398 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1782501wru; Sun, 13 Nov 2022 10:14:22 -0800 (PST) X-Google-Smtp-Source: AA0mqf6KXLf7PIzLyN8wpDya6Ov8GLGwnsaP3xAjHc2sufPZdkZwo3UpjCLSGY+gS8/uHduUifr0 X-Received: by 2002:a17:90a:9b85:b0:212:f8e5:81ab with SMTP id g5-20020a17090a9b8500b00212f8e581abmr10995979pjp.114.1668363262338; Sun, 13 Nov 2022 10:14:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668363262; cv=none; d=google.com; s=arc-20160816; b=Z9JKAHjXGSOTyPppHv00WliRQpNgaL9K6KbelocxttW3Ww1AUkcwRg9UlooWMPhCKv phacwBnC4ZAm6mJE5JpePLOyYyYV4ArxLC0ZPf0aNyysT/XbebEjbfds9ufe+fVTDPX6 +O/OAHoH4VpkGEjYa0c5WJwm2k4G9U1rdkBJn8ZCYSGVavVh2oMfz2vFmqKLzSgI9L8G R6tW8InyR+sDCmM3KCHdbD9x3nSxw+OAgGeiEiqrQgzFRNYDo8oTTwFzuJuLz8nZnoVO L39+apL0j1H+PjaHSx8jhSDZjlyneSt6JwkadXlmaSE+DMs8Z/EliOAkgrWfpzJNGqLn TDhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jfErmyZAWFClEhl0ayKENaiIcOOkglWFws7K0nbLI8s=; b=TnDlX47hMo5NhECgeDL6AxBsLbPiPBoNDNlqginSuGcoX3cFtUXGBmobc+ifO8zP5Q uCbeViexn4PQcoO90p+WYPF4BEztME0KPihpTxoIp1Qlw8nAalqqoVQKQnJcJnpI2UeR f2qu/hGlpAno7mcLwT4Bh5JucIKbkD7draabw+gTnyu3TuM5YjHArWiODy0gWRQWoZWY geMQGwNxe+HNJhosV7r7NjpKNfGdtvDcgb+rFOqZKexkxALF4QXzqH0W8QBn+OgqLs5y aTLF8rPSaQq8D+RTmHIYx/v4aT6xBXMQjc2knGcrXsFjFXwb7IU9dADuXT+3+uTvFSCB oQBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BkL5YgTw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f14-20020a170902ce8e00b00186a4783b53si8919793plg.478.2022.11.13.10.14.07; Sun, 13 Nov 2022 10:14:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BkL5YgTw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235515AbiKMSNq (ORCPT + 99 others); Sun, 13 Nov 2022 13:13:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235493AbiKMSNj (ORCPT ); Sun, 13 Nov 2022 13:13:39 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCF7D6440 for ; Sun, 13 Nov 2022 10:13:37 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id m22so23344204eji.10 for ; Sun, 13 Nov 2022 10:13:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jfErmyZAWFClEhl0ayKENaiIcOOkglWFws7K0nbLI8s=; b=BkL5YgTwGRmPOHa53TbvbuIBYxleFaIrL+sDkKmaQ9HYCgMUP4SFkb8HHgz7mYGtqO Lk1hgxQK28YAdtvPoZobkiqYvcWkLbvDLmGYC6sPtvAhg3tOmQ7SsFRdm2JTt50lrUCv OEZ8aaFpuMb1nBBVV5gso//0VSdvHlUq6e1yE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jfErmyZAWFClEhl0ayKENaiIcOOkglWFws7K0nbLI8s=; b=3QgQpQodVQjdVIp5mCcO2T5kFwD1wuXmNOfvRwWBoLyK1o/SE35FX34UwuL+G6/WUP 0/ithxh5olcMfN7ryxdnunxkOySm/mCc9zYKDiIvMd2lgFydJrUVfS9pwknPg5KMOLPx mqIqCFVXXZg8WATWtaHbaJDTtC8jejp64ZJtc1jMBzPPoCA+VeRhGT9ThgY9iWAlVzWo 3qOs1CuCl2mlqk8UyIFSSMS+slBzuYdSdsxfS/HmeW4dDwXjx1R7u/vxfy1PTTEvukpo EpwAoOeqSI3wTgikz7vlHvY6qlcJEbgJJTh5NSh/nhBfZinXR0z8Rmnx8fdlRmHfXtik cKsA== X-Gm-Message-State: ANoB5pl2SFVxaTUEK/XjfMBCn5Z0ZGHsEy/y6bLkDWTIbjFKdRwYTTxS uRzeUsNqJRahxx9y9fY/lqDAN+ObPjCKAA== X-Received: by 2002:a17:907:d608:b0:7ad:934e:d542 with SMTP id wd8-20020a170907d60800b007ad934ed542mr8894284ejc.20.1668363216162; Sun, 13 Nov 2022 10:13:36 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-40-103-33.business.telecomitalia.it. [79.40.103.33]) by smtp.gmail.com with ESMTPSA id iy6-20020a170907818600b0078de26f66b9sm3225487ejc.114.2022.11.13.10.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 10:13:35 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Marc Kleine-Budde , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND RFC PATCH v5 4/5] ARM: dts: stm32: add pin map for CAN controller on stm32f4 Date: Sun, 13 Nov 2022 19:13:21 +0100 Message-Id: <20221113181322.1627084-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> References: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749405676031866514?= X-GMAIL-MSGID: =?utf-8?q?1749405676031866514?= Add pin configurations for using CAN controller on stm32f469-disco board. They are located on the Arduino compatible connector CN5 (CAN1) and on the extension connector CN12 (CAN2). Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Remove 'Dario Binacchi ' SOB. - Remove a blank line. Changes in v2: - Remove a blank line. arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 500bcc302d42..8a4d51f97248 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -448,6 +448,36 @@ pins2 { slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; }; }; }; From patchwork Sun Nov 13 18:13:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 19401 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1792477wru; Sun, 13 Nov 2022 10:48:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf63CergiGcyDIa0ZrXZC2aKxmFxrQKzAqqF4SLwEYmuGaoYjeAx14M/1bcFCxqhfDpt/940 X-Received: by 2002:a17:90b:2308:b0:215:e103:91fd with SMTP id mt8-20020a17090b230800b00215e10391fdmr10798982pjb.186.1668365330389; Sun, 13 Nov 2022 10:48:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668365330; cv=none; d=google.com; s=arc-20160816; b=Lkt9+8W8XCLUbqDDRnXKT8kpsLCZj9ghD5nmapnxjyzsauH7HGBvYMLcVoPlSgN6RZ jqTecx1CxHyLW3Oi5rT3BjzvLde0clQIX6IpUFVYH/1GDoHi3jXkrlo00BIaS0kA+zLs QLk+f/TWot7OAgH84hWJw9lC00ECAzxdr9kyZ8SAic4AyWwnQXnV8mfGx/j+Fl5mmfKA QBFfaSVXzGhn21uo+fjetLOGUDvDTjm7MWPVeifDTZayKmPi385dd3IYKubq4PUNzo+u +t8d1izjZDE7vuCuMPqm6wKReMrVJ+zzDaIZPg6CGxYLiYILKKISGS+ZiftqHvJwzxpx rhTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XSkk05HK9Fak8Si3RFSUjVQkoCdRsocGt30Z7267NXU=; b=uXPOig2ssF5greCuXR19D6qgTX9Wh3Ir+IEj3j3vNwwfBVvGLLoNOQ2w5LWT0+68NZ Unk24v4TR6Pt4frwcawBIiyWl4sZ/A1hpiJSlyRAp1IdQTjGVPc7V52acBb9vjqxyv27 +2s0ZipjkdVfYWSM3HS8qWeK4ey3TpQ2IDVClRukIDvw5Cr5fHgBSqkMZfoDzv9773L5 GPKiTLPTJZz5AK2HSsUd+Z3cK93D0O9yFQ+1Q5O13n6l2y29Iy3kW0REUGYR04tyH3RT oM41620noPbkrux4CzN1UAejXdOKaf/TC7ViRNGvpv37Mr2F4P+4OfrxUJLcLStmYjtl oxYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=M+L3ec+4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qa13-20020a17090b4fcd00b0020a97a92a2fsi7655555pjb.135.2022.11.13.10.48.37; Sun, 13 Nov 2022 10:48:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=M+L3ec+4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235552AbiKMSOA (ORCPT + 99 others); Sun, 13 Nov 2022 13:14:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235513AbiKMSNm (ORCPT ); Sun, 13 Nov 2022 13:13:42 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0A46BF65 for ; Sun, 13 Nov 2022 10:13:38 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id n20so2799494ejh.0 for ; Sun, 13 Nov 2022 10:13:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XSkk05HK9Fak8Si3RFSUjVQkoCdRsocGt30Z7267NXU=; b=M+L3ec+4PgpEpbI21oXF1uj3u6ty6SX0Wn+85OC5hW++5o88wL8hgtxNoApAEMVhIz YvUCe48cnfrwvntWs3pkUh8MWNWYfja2CcssUQMmDlkku7LwKEhoXhcc3zR+cSz8watk UBEnfE5n/fvMAf0FQLB1sAk/IlXTULwcs5xdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XSkk05HK9Fak8Si3RFSUjVQkoCdRsocGt30Z7267NXU=; b=gLvRjkO1KupUrpOL5MTWHsUDWJhr+gX4xzw9PlQAMG0FNrGhNgJGJrB1fTVBOourOL j7a9oaArYFQ2xq/jO8NY9alAfRCzbXaci84Z8syJvoM7w/VdaNAXoi6lsLvCX91usGgt 8Bh3rPR5Fm1R7pOmyi/k+kYMKyfDovRVh3Un9moy2Qh7SOIWgM4CQ7lpFnjual0rrx5B ErSXpvMW8A3rlSJO0156CCb16TRT+oRrBWpw0PQvycg324e3TaURiVDuQ1yvQKc9GPPk sCxI19rK47e/30PnImD+PwN0dpnugW7fQxkYkpc1XrJDQxxAA+RuGPsIUVKZaGT7GQWy 8p/Q== X-Gm-Message-State: ANoB5pkhKM6+vSbaJhIOofGlzMentvLxI0KxTekPnJ/h+X2N3S25/eE7 ODn9UlCh+j86SByQGbiEiOntWUbKCSLJ1w== X-Received: by 2002:a17:906:5f88:b0:7ad:92fa:589e with SMTP id a8-20020a1709065f8800b007ad92fa589emr7813536eju.668.1668363217552; Sun, 13 Nov 2022 10:13:37 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-40-103-33.business.telecomitalia.it. [79.40.103.33]) by smtp.gmail.com with ESMTPSA id iy6-20020a170907818600b0078de26f66b9sm3225487ejc.114.2022.11.13.10.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 10:13:37 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Marc Kleine-Budde , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Wolfgang Grandegger , linux-can@vger.kernel.org, netdev@vger.kernel.org Subject: [RESEND RFC PATCH v5 5/5] can: bxcan: add support for ST bxCAN controller Date: Sun, 13 Nov 2022 19:13:22 +0100 Message-Id: <20221113181322.1627084-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> References: <20221113181322.1627084-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749405669794949489?= X-GMAIL-MSGID: =?utf-8?q?1749407844715653568?= Add support for the basic extended CAN controller (bxCAN) found in many low- to middle-end STM32 SoCs. It supports the Basic Extended CAN protocol versions 2.0A and B with a maximum bit rate of 1 Mbit/s. The controller supports two channels (CAN1 as master and CAN2 as slave) and the driver can enable either or both of the channels. They share some of the required logic (e. g. clocks and filters), and that means you cannot use the slave CAN without enabling some hardware resources managed by the master CAN. Each channel has 3 transmit mailboxes, 2 receive FIFOs with 3 stages and 28 scalable filter banks. It also manages 4 dedicated interrupt vectors: - transmit interrupt - FIFO 0 receive interrupt - FIFO 1 receive interrupt - status change error interrupt Driver uses all 3 available mailboxes for transmission and FIFO 0 for reception. Rx filter rules are configured to the minimum. They accept all messages and assign filter 0 to CAN1 and filter 14 to CAN2 in identifier mask mode with 32 bits width. It enables and uses transmit, receive buffers for FIFO 0 and error and status change interrupts. Signed-off-by: Dario Binacchi --- Changes in v5: - Put static in front of bxcan_enable_filters() definition. Changes in v4: - Add "dt-bindings: arm: stm32: add compatible for syscon gcan node" patch. - Drop the core driver. Thus bxcan-drv.c has been renamed to bxcan.c and moved to the drivers/net/can folder. The drivers/net/can/bxcan directory has therefore been removed. - Use the regmap_*() functions to access the shared memory registers. - Use spinlock to protect bxcan_rmw(). - Use 1 space, instead of tabs, in the macros definition. - Drop clock ref-counting. - Drop unused code. - Drop the _SHIFT macros and use FIELD_GET()/FIELD_PREP() directly. - Add BXCAN_ prefix to lec error codes. - Add the macro BXCAN_RX_MB_NUM. - Enable time triggered mode and use can_rx_offload(). - Use readx_poll_timeout() in function with timeouts. - Loop from tail to head in bxcan_tx_isr(). - Check bits of tsr register instead of pkts variable in bxcan_tx_isr(). - Don't return from bxcan_handle_state_change() if skb/cf are NULL. - Enable/disable the generation of the bus error interrupt depending on can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING. - Don't return from bxcan_handle_bus_err() if skb is NULL. - Drop statistics updating from bxcan_handle_bus_err(). - Add an empty line in front of 'return IRQ_HANDLED;' - Rename bxcan_start() to bxcan_chip_start(). - Rename bxcan_stop() to bxcan_chip_stop(). - Disable all IRQs in bxcan_chip_stop(). - Rename bxcan_close() to bxcan_ndo_stop(). - Use writel instead of bxcan_rmw() to update the dlc register. Changes in v3: - Remove 'Dario Binacchi ' SOB. - Fix the documentation file path in the MAINTAINERS entry. - Do not increment the "stats->rx_bytes" if the frame is remote. - Remove pr_debug() call from bxcan_rmw(). Changes in v2: - Fix sparse errors. - Create a MAINTAINERS entry. - Remove the print of the registers address. - Remove the volatile keyword from bxcan_rmw(). - Use tx ring algorithm to manage tx mailboxes. - Use can_{get|put}_echo_skb(). - Update DT properties. MAINTAINERS | 7 + drivers/net/can/Kconfig | 12 + drivers/net/can/Makefile | 1 + drivers/net/can/bxcan.c | 1110 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 1130 insertions(+) create mode 100644 drivers/net/can/bxcan.c diff --git a/MAINTAINERS b/MAINTAINERS index 256f03904987..0306d2939cb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4498,6 +4498,13 @@ S: Maintained F: drivers/scsi/BusLogic.* F: drivers/scsi/FlashPoint.* +BXCAN CAN NETWORK DRIVER +M: Dario Binacchi +L: linux-can@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml +F: drivers/net/can/bxcan.c + C-MEDIA CMI8788 DRIVER M: Clemens Ladisch L: alsa-devel@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig index 3048ad77edb3..b3a9fb9bcf92 100644 --- a/drivers/net/can/Kconfig +++ b/drivers/net/can/Kconfig @@ -93,6 +93,18 @@ config CAN_AT91 This is a driver for the SoC CAN controller in Atmel's AT91SAM9263 and AT91SAM9X5 processors. +config CAN_BXCAN + tristate "STM32 Basic Extended CAN (bxCAN) devices" + depends on OF || ARCH_STM32 || COMPILE_TEST + depends on HAS_IOMEM + select CAN_RX_OFFLOAD + help + Say yes here to build support for the STMicroelectronics STM32 basic + extended CAN Controller (bxCAN). + + This driver can also be built as a module. If so, the module + will be called bxcan. + config CAN_CAN327 tristate "Serial / USB serial ELM327 based OBD-II Interfaces (can327)" depends on TTY diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile index 61c75ce9d500..bc859399eeb6 100644 --- a/drivers/net/can/Makefile +++ b/drivers/net/can/Makefile @@ -14,6 +14,7 @@ obj-y += usb/ obj-y += softing/ obj-$(CONFIG_CAN_AT91) += at91_can.o +obj-$(CONFIG_CAN_BXCAN) += bxcan.o obj-$(CONFIG_CAN_CAN327) += can327.o obj-$(CONFIG_CAN_CC770) += cc770/ obj-$(CONFIG_CAN_C_CAN) += c_can/ diff --git a/drivers/net/can/bxcan.c b/drivers/net/can/bxcan.c new file mode 100644 index 000000000000..7f8831aef9c9 --- /dev/null +++ b/drivers/net/can/bxcan.c @@ -0,0 +1,1110 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// bxcan.c - STM32 Basic Extended CAN controller driver +// +// Copyright (c) 2022 Dario Binacchi +// + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BXCAN_NAPI_WEIGHT 3 +#define BXCAN_TIMEOUT_US 10000 + +#define BXCAN_RX_MB_NUM 2 +#define BXCAN_TX_MB_NUM 3 + +/* Master control register (MCR) bits */ +#define BXCAN_MCR_DBF BIT(16) +#define BXCAN_MCR_RESET BIT(15) +#define BXCAN_MCR_TTCM BIT(7) +#define BXCAN_MCR_ABOM BIT(6) +#define BXCAN_MCR_AWUM BIT(5) +#define BXCAN_MCR_NART BIT(4) +#define BXCAN_MCR_RFLM BIT(3) +#define BXCAN_MCR_TXFP BIT(2) +#define BXCAN_MCR_SLEEP BIT(1) +#define BXCAN_MCR_INRQ BIT(0) + +/* Master status register (MSR) bits */ +#define BXCAN_MSR_RX BIT(11) +#define BXCAN_MSR_SAMP BIT(10) +#define BXCAN_MSR_RXM BIT(9) +#define BXCAN_MSR_TXM BIT(8) +#define BXCAN_MSR_SLAKI BIT(4) +#define BXCAN_MSR_WKUI BIT(3) +#define BXCAN_MSR_ERRI BIT(2) +#define BXCAN_MSR_SLAK BIT(1) +#define BXCAN_MSR_INAK BIT(0) + +/* Transmit status register (TSR) bits */ +#define BXCAN_TSR_LOW2 BIT(31) +#define BXCAN_TSR_LOW1 BIT(30) +#define BXCAN_TSR_LOW0 BIT(29) +#define BXCAN_TSR_TME_MASK GENMASK(28, 26) +#define BXCAN_TSR_TME2 BIT(28) +#define BXCAN_TSR_TME1 BIT(27) +#define BXCAN_TSR_TME0 BIT(26) +#define BXCAN_TSR_CODE_MASK GENMASK(25, 24) +#define BXCAN_TSR_ABRQ2 BIT(23) +#define BXCAN_TSR_TERR2 BIT(19) +#define BXCAN_TSR_ALST2 BIT(18) +#define BXCAN_TSR_TXOK2 BIT(17) +#define BXCAN_TSR_RQCP2 BIT(16) +#define BXCAN_TSR_ABRQ1 BIT(15) +#define BXCAN_TSR_TERR1 BIT(11) +#define BXCAN_TSR_ALST1 BIT(10) +#define BXCAN_TSR_TXOK1 BIT(9) +#define BXCAN_TSR_RQCP1 BIT(8) +#define BXCAN_TSR_ABRQ0 BIT(7) +#define BXCAN_TSR_TERR0 BIT(3) +#define BXCAN_TSR_ALST0 BIT(2) +#define BXCAN_TSR_TXOK0 BIT(1) +#define BXCAN_TSR_RQCP0 BIT(0) + +/* Receive FIFO 0 register (RF0R) bits */ +#define BXCAN_RF0R_RFOM0 BIT(5) +#define BXCAN_RF0R_FOVR0 BIT(4) +#define BXCAN_RF0R_FULL0 BIT(3) +#define BXCAN_RF0R_FMP0_MASK GENMASK(1, 0) + +/* Interrupt enable register (IER) bits */ +#define BXCAN_IER_SLKIE BIT(17) +#define BXCAN_IER_WKUIE BIT(16) +#define BXCAN_IER_ERRIE BIT(15) +#define BXCAN_IER_LECIE BIT(11) +#define BXCAN_IER_BOFIE BIT(10) +#define BXCAN_IER_EPVIE BIT(9) +#define BXCAN_IER_EWGIE BIT(8) +#define BXCAN_IER_FOVIE1 BIT(6) +#define BXCAN_IER_FFIE1 BIT(5) +#define BXCAN_IER_FMPIE1 BIT(4) +#define BXCAN_IER_FOVIE0 BIT(3) +#define BXCAN_IER_FFIE0 BIT(2) +#define BXCAN_IER_FMPIE0 BIT(1) +#define BXCAN_IER_TMEIE BIT(0) + +/* Error status register (ESR) bits */ +#define BXCAN_ESR_REC_MASK GENMASK(31, 24) +#define BXCAN_ESR_TEC_MASK GENMASK(23, 16) +#define BXCAN_ESR_LEC_MASK GENMASK(6, 4) +#define BXCAN_ESR_BOFF BIT(2) +#define BXCAN_ESR_EPVF BIT(1) +#define BXCAN_ESR_EWGF BIT(0) + +/* Bit timing register (BTR) bits */ +#define BXCAN_BTR_SILM BIT(31) +#define BXCAN_BTR_LBKM BIT(30) +#define BXCAN_BTR_SJW_MASK GENMASK(25, 24) +#define BXCAN_BTR_TS2_MASK GENMASK(22, 20) +#define BXCAN_BTR_TS1_MASK GENMASK(19, 16) +#define BXCAN_BTR_BRP_MASK GENMASK(9, 0) + +/* TX mailbox identifier register (TIxR, x = 0..2) bits */ +#define BXCAN_TIxR_STID_MASK GENMASK(31, 21) +#define BXCAN_TIxR_EXID_MASK GENMASK(31, 3) +#define BXCAN_TIxR_IDE BIT(2) +#define BXCAN_TIxR_RTR BIT(1) +#define BXCAN_TIxR_TXRQ BIT(0) + +/* TX mailbox data length and time stamp register (TDTxR, x = 0..2 bits */ +#define BXCAN_TDTxR_TIME_MASK GENMASK(31, 16) +#define BXCAN_TDTxR_TGT BIT(8) +#define BXCAN_TDTxR_DLC_MASK GENMASK(3, 0) + +/* RX FIFO mailbox identifier register (RIxR, x = 0..1 */ +#define BXCAN_RIxR_STID_MASK GENMASK(31, 21) +#define BXCAN_RIxR_EXID_MASK GENMASK(31, 3) +#define BXCAN_RIxR_IDE BIT(2) +#define BXCAN_RIxR_RTR BIT(1) + +/* RX FIFO mailbox data length and timestamp register (RDTxR, x = 0..1) bits */ +#define BXCAN_RDTxR_TIME_MASK GENMASK(31, 16) +#define BXCAN_RDTxR_FMI_MASK GENMASK(15, 8) +#define BXCAN_RDTxR_DLC_MASK GENMASK(3, 0) + +#define BXCAN_FMR_REG 0x00 +#define BXCAN_FM1R_REG 0x04 +#define BXCAN_FS1R_REG 0x0c +#define BXCAN_FFA1R_REG 0x14 +#define BXCAN_FA1R_REG 0x1c +#define BXCAN_FiR1_REG(b) (0x40 + (b) * 8) +#define BXCAN_FiR2_REG(b) (0x44 + (b) * 8) + +#define BXCAN_FILTER_ID(master) (master ? 0 : 14) + +/* Filter master register (FMR) bits */ +#define BXCAN_FMR_CANSB_MASK GENMASK(13, 8) +#define BXCAN_FMR_FINIT BIT(0) + +enum bxcan_lec_code { + BXCAN_LEC_NO_ERROR = 0, + BXCAN_LEC_STUFF_ERROR, + BXCAN_LEC_FORM_ERROR, + BXCAN_LEC_ACK_ERROR, + BXCAN_LEC_BIT1_ERROR, + BXCAN_LEC_BIT0_ERROR, + BXCAN_LEC_CRC_ERROR, + BXCAN_LEC_UNUSED +}; + +/* Structure of the message buffer */ +struct bxcan_mb { + u32 id; /* can identifier */ + u32 dlc; /* data length control and timestamp */ + u32 data[2]; /* data */ +}; + +/* Structure of the hardware registers */ +struct bxcan_regs { + u32 mcr; /* 0x00 - master control */ + u32 msr; /* 0x04 - master status */ + u32 tsr; /* 0x08 - transmit status */ + u32 rf0r; /* 0x0c - FIFO 0 */ + u32 rf1r; /* 0x10 - FIFO 1 */ + u32 ier; /* 0x14 - interrupt enable */ + u32 esr; /* 0x18 - error status */ + u32 btr; /* 0x1c - bit timing*/ + u32 reserved0[88]; /* 0x20 */ + struct bxcan_mb tx_mb[BXCAN_TX_MB_NUM]; /* 0x180 - tx mailbox */ + struct bxcan_mb rx_mb[BXCAN_RX_MB_NUM]; /* 0x1b0 - rx mailbox */ +}; + +struct bxcan_priv { + struct can_priv can; + struct can_rx_offload offload; + struct device *dev; + struct net_device *ndev; + + struct bxcan_regs __iomem *regs; + struct regmap *gcan; + int tx_irq; + int sce_irq; + bool master; + struct clk *clk; + spinlock_t rmw_lock; /* lock for read-modify-write operations */ + unsigned int tx_head; + unsigned int tx_tail; + u32 timestamp; +}; + +static const struct can_bittiming_const bxcan_bittiming_const = { + .name = KBUILD_MODNAME, + .tseg1_min = 1, + .tseg1_max = 16, + .tseg2_min = 1, + .tseg2_max = 8, + .sjw_max = 4, + .brp_min = 1, + .brp_max = 1024, + .brp_inc = 1, +}; + +static inline void bxcan_rmw(struct bxcan_priv *priv, void __iomem *addr, + u32 clear, u32 set) +{ + unsigned long flags; + u32 old, val; + + spin_lock_irqsave(&priv->rmw_lock, flags); + old = readl(addr); + val = (old & ~clear) | set; + if (val != old) + writel(val, addr); + + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + +static void bxcan_disable_filters(struct bxcan_priv *priv, bool master) +{ + unsigned int fid = BXCAN_FILTER_ID(master); + u32 fmask = BIT(fid); + + regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, 0); +} + +static void bxcan_enable_filters(struct bxcan_priv *priv, bool master) +{ + unsigned int fid = BXCAN_FILTER_ID(master); + u32 fmask = BIT(fid); + + /* Filter settings: + * + * Accept all messages. + * Assign filter 0 to CAN1 and filter 14 to CAN2 in identifier + * mask mode with 32 bits width. + */ + + /* Enter filter initialization mode and assing filters to CAN + * controllers. + */ + regmap_update_bits(priv->gcan, BXCAN_FMR_REG, + BXCAN_FMR_CANSB_MASK | BXCAN_FMR_FINIT, + FIELD_PREP(BXCAN_FMR_CANSB_MASK, 14) | + BXCAN_FMR_FINIT); + + /* Deactivate filter */ + regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, 0); + + /* Two 32-bit registers in identifier mask mode */ + regmap_update_bits(priv->gcan, BXCAN_FM1R_REG, fmask, 0); + + /* Single 32-bit scale configuration */ + regmap_update_bits(priv->gcan, BXCAN_FS1R_REG, fmask, fmask); + + /* Assign filter to FIFO 0 */ + regmap_update_bits(priv->gcan, BXCAN_FFA1R_REG, fmask, 0); + + /* Accept all messages */ + regmap_write(priv->gcan, BXCAN_FiR1_REG(fid), 0); + regmap_write(priv->gcan, BXCAN_FiR2_REG(fid), 0); + + /* Activate filter */ + regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, fmask); + + /* Exit filter initialization mode */ + regmap_update_bits(priv->gcan, BXCAN_FMR_REG, BXCAN_FMR_FINIT, 0); +} + +static inline u8 bxcan_get_tx_head(const struct bxcan_priv *priv) +{ + return priv->tx_head % BXCAN_TX_MB_NUM; +} + +static inline u8 bxcan_get_tx_tail(const struct bxcan_priv *priv) +{ + return priv->tx_tail % BXCAN_TX_MB_NUM; +} + +static inline u8 bxcan_get_tx_free(const struct bxcan_priv *priv) +{ + return BXCAN_TX_MB_NUM - (priv->tx_head - priv->tx_tail); +} + +static bool bxcan_tx_busy(const struct bxcan_priv *priv) +{ + if (bxcan_get_tx_free(priv) > 0) + return false; + + netif_stop_queue(priv->ndev); + + /* Memory barrier before checking tx_free (head and tail) */ + smp_mb(); + + if (bxcan_get_tx_free(priv) == 0) { + netdev_dbg(priv->ndev, + "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n", + priv->tx_head, priv->tx_tail, + priv->tx_head - priv->tx_tail); + + return true; + } + + netif_start_queue(priv->ndev); + + return false; +} + +static int bxcan_chip_softreset(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, 0, BXCAN_MCR_RESET); + return readx_poll_timeout(readl, ®s->msr, value, + value & BXCAN_MSR_SLAK, BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_enter_init_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, 0, BXCAN_MCR_INRQ); + return readx_poll_timeout(readl, ®s->msr, value, + value & BXCAN_MSR_INAK, BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_leave_init_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, BXCAN_MCR_INRQ, 0); + return readx_poll_timeout(readl, ®s->msr, value, + !(value & BXCAN_MSR_INAK), BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_enter_sleep_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, 0, BXCAN_MCR_SLEEP); + return readx_poll_timeout(readl, ®s->msr, value, + value & BXCAN_MSR_SLAK, BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_leave_sleep_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, BXCAN_MCR_SLEEP, 0); + return readx_poll_timeout(readl, ®s->msr, value, + !(value & BXCAN_MSR_SLAK), BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static inline +struct bxcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) +{ + return container_of(offload, struct bxcan_priv, offload); +} + +static struct sk_buff *bxcan_mailbox_read(struct can_rx_offload *offload, + unsigned int mbxno, u32 *timestamp, + bool drop) +{ + struct bxcan_priv *priv = rx_offload_to_priv(offload); + struct bxcan_regs __iomem *regs = priv->regs; + struct bxcan_mb __iomem *mb_regs = ®s->rx_mb[0]; + struct sk_buff *skb = NULL; + struct can_frame *cf; + u32 rf0r, id, dlc; + + rf0r = readl(®s->rf0r); + if (unlikely(drop)) { + skb = ERR_PTR(-ENOBUFS); + goto mark_as_read; + } + + if (!(rf0r & BXCAN_RF0R_FMP0_MASK)) + goto mark_as_read; + + skb = alloc_can_skb(offload->dev, &cf); + if (unlikely(!skb)) { + skb = ERR_PTR(-ENOMEM); + goto mark_as_read; + } + + id = readl(&mb_regs->id); + if (id & BXCAN_RIxR_IDE) + cf->can_id = FIELD_GET(BXCAN_RIxR_EXID_MASK, id) | CAN_EFF_FLAG; + else + cf->can_id = FIELD_GET(BXCAN_RIxR_STID_MASK, id) & CAN_SFF_MASK; + + dlc = readl(&mb_regs->dlc); + priv->timestamp = FIELD_GET(BXCAN_RDTxR_TIME_MASK, dlc); + cf->len = can_cc_dlc2len(FIELD_GET(BXCAN_RDTxR_DLC_MASK, dlc)); + + if (id & BXCAN_RIxR_RTR) { + cf->can_id |= CAN_RTR_FLAG; + } else { + int i, j; + + for (i = 0, j = 0; i < cf->len; i += 4, j++) + *(u32 *)(cf->data + i) = readl(&mb_regs->data[j]); + } + + mark_as_read: + rf0r |= BXCAN_RF0R_RFOM0; + writel(rf0r, ®s->rf0r); + return skb; +} + +static irqreturn_t bxcan_rx_isr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct bxcan_priv *priv = netdev_priv(ndev); + + can_rx_offload_irq_offload_fifo(&priv->offload); + can_rx_offload_irq_finish(&priv->offload); + + return IRQ_HANDLED; +} + +static irqreturn_t bxcan_tx_isr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + struct net_device_stats *stats = &ndev->stats; + u32 tsr, rqcp_bit; + int idx; + + tsr = readl(®s->tsr); + if (!(tsr & (BXCAN_TSR_RQCP0 | BXCAN_TSR_RQCP1 | BXCAN_TSR_RQCP2))) + return IRQ_HANDLED; + + while (priv->tx_head - priv->tx_tail > 0) { + idx = bxcan_get_tx_tail(priv); + rqcp_bit = BXCAN_TSR_RQCP0 << (idx << 3); + if (!(tsr & rqcp_bit)) + break; + + stats->tx_packets++; + stats->tx_bytes += can_get_echo_skb(ndev, idx, NULL); + priv->tx_tail++; + } + + writel(tsr, ®s->tsr); + + if (bxcan_get_tx_free(priv)) { + /* Make sure that anybody stopping the queue after + * this sees the new tx_ring->tail. + */ + smp_mb(); + netif_wake_queue(ndev); + } + + return IRQ_HANDLED; +} + +static void bxcan_handle_state_change(struct net_device *ndev, u32 esr) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + enum can_state new_state = priv->can.state; + struct can_berr_counter bec; + enum can_state rx_state, tx_state; + struct sk_buff *skb; + struct can_frame *cf; + + /* Early exit if no error flag is set */ + if (!(esr & (BXCAN_ESR_EWGF | BXCAN_ESR_EPVF | BXCAN_ESR_BOFF))) + return; + + bec.txerr = FIELD_GET(BXCAN_ESR_TEC_MASK, esr); + bec.rxerr = FIELD_GET(BXCAN_ESR_REC_MASK, esr); + + if (esr & BXCAN_ESR_BOFF) + new_state = CAN_STATE_BUS_OFF; + else if (esr & BXCAN_ESR_EPVF) + new_state = CAN_STATE_ERROR_PASSIVE; + else if (esr & BXCAN_ESR_EWGF) + new_state = CAN_STATE_ERROR_WARNING; + + /* state hasn't changed */ + if (unlikely(new_state == priv->can.state)) + return; + + skb = alloc_can_err_skb(ndev, &cf); + + tx_state = bec.txerr >= bec.rxerr ? new_state : 0; + rx_state = bec.txerr <= bec.rxerr ? new_state : 0; + can_change_state(ndev, cf, tx_state, rx_state); + + if (new_state == CAN_STATE_BUS_OFF) { + can_bus_off(ndev); + } else if (skb) { + cf->data[6] = bec.txerr; + cf->data[7] = bec.rxerr; + } + + if (skb) { + int err; + + err = can_rx_offload_queue_timestamp(&priv->offload, skb, + priv->timestamp); + if (err) + ndev->stats.rx_fifo_errors++; + } +} + +static void bxcan_handle_bus_err(struct net_device *ndev, u32 esr) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + enum bxcan_lec_code lec_code; + struct can_frame *cf; + struct sk_buff *skb; + + lec_code = FIELD_GET(BXCAN_ESR_LEC_MASK, esr); + + /* Early exit if no lec update or no error. + * No lec update means that no CAN bus event has been detected + * since CPU wrote BXCAN_LEC_UNUSED value to status reg. + */ + if (lec_code == BXCAN_LEC_UNUSED || lec_code == BXCAN_LEC_NO_ERROR) + return; + + /* Common for all type of bus errors */ + priv->can.can_stats.bus_error++; + + /* Propagate the error condition to the CAN stack */ + skb = alloc_can_err_skb(ndev, &cf); + if (skb) + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; + + switch (lec_code) { + case BXCAN_LEC_STUFF_ERROR: + netdev_dbg(ndev, "Stuff error\n"); + ndev->stats.rx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_STUFF; + + break; + case BXCAN_LEC_FORM_ERROR: + netdev_dbg(ndev, "Form error\n"); + ndev->stats.rx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_FORM; + + break; + case BXCAN_LEC_ACK_ERROR: + netdev_dbg(ndev, "Ack error\n"); + ndev->stats.tx_errors++; + if (skb) { + cf->can_id |= CAN_ERR_ACK; + cf->data[3] = CAN_ERR_PROT_LOC_ACK; + } + + break; + case BXCAN_LEC_BIT1_ERROR: + netdev_dbg(ndev, "Bit error (recessive)\n"); + ndev->stats.tx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_BIT1; + + break; + case BXCAN_LEC_BIT0_ERROR: + netdev_dbg(ndev, "Bit error (dominant)\n"); + ndev->stats.tx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_BIT0; + + break; + case BXCAN_LEC_CRC_ERROR: + netdev_dbg(ndev, "CRC error\n"); + ndev->stats.rx_errors++; + if (skb) { + cf->data[2] |= CAN_ERR_PROT_BIT; + cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; + } + + break; + default: + break; + } + + if (skb) { + int err; + + err = can_rx_offload_queue_timestamp(&priv->offload, skb, + priv->timestamp); + if (err) + ndev->stats.rx_fifo_errors++; + } +} + +static irqreturn_t bxcan_state_change_isr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + u32 msr, esr; + + msr = readl(®s->msr); + if (!(msr & BXCAN_MSR_ERRI)) + return IRQ_NONE; + + esr = readl(®s->esr); + bxcan_handle_state_change(ndev, esr); + + if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) + bxcan_handle_bus_err(ndev, esr); + + msr |= BXCAN_MSR_ERRI; + writel(msr, ®s->msr); + can_rx_offload_irq_finish(&priv->offload); + + return IRQ_HANDLED; +} + +static int bxcan_chip_start(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + struct can_bittiming *bt = &priv->can.bittiming; + u32 clr, set; + int err; + + err = bxcan_chip_softreset(priv); + if (err) { + netdev_err(ndev, "failed to reset chip, error %d\n", err); + return err; + } + + err = bxcan_leave_sleep_mode(priv); + if (err) { + netdev_err(ndev, "failed to leave sleep mode, error %d\n", err); + goto failed_leave_sleep; + } + + err = bxcan_enter_init_mode(priv); + if (err) { + netdev_err(ndev, "failed to enter init mode, error %d\n", err); + goto failed_enter_init; + } + + /* MCR + * + * select request order priority + * enable time triggered mode + * bus-off state left on sw request + * sleep mode left on sw request + * retransmit automatically on error + * do not lock RX FIFO on overrun + */ + bxcan_rmw(priv, ®s->mcr, + BXCAN_MCR_ABOM | BXCAN_MCR_AWUM | BXCAN_MCR_NART | + BXCAN_MCR_RFLM, BXCAN_MCR_TTCM | BXCAN_MCR_TXFP); + + /* Bit timing register settings */ + set = FIELD_PREP(BXCAN_BTR_BRP_MASK, bt->brp - 1) | + FIELD_PREP(BXCAN_BTR_TS1_MASK, bt->phase_seg1 + + bt->prop_seg - 1) | + FIELD_PREP(BXCAN_BTR_TS2_MASK, bt->phase_seg2 - 1) | + FIELD_PREP(BXCAN_BTR_SJW_MASK, bt->sjw - 1); + + /* loopback + silent mode put the controller in test mode, + * useful for hot self-test + */ + if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) + set |= BXCAN_BTR_LBKM; + + if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) + set |= BXCAN_BTR_SILM; + + netdev_dbg(ndev, + "TQ[ns]: %d, PrS: %d, PhS1: %d, PhS2: %d, SJW: %d, BRP: %d, CAN_BTR: 0x%08x\n", + bt->tq, bt->prop_seg, bt->phase_seg1, bt->phase_seg2, + bt->sjw, bt->brp, set); + bxcan_rmw(priv, ®s->btr, BXCAN_BTR_SILM | BXCAN_BTR_LBKM | + BXCAN_BTR_BRP_MASK | BXCAN_BTR_TS1_MASK | BXCAN_BTR_TS2_MASK | + BXCAN_BTR_SJW_MASK, set); + + bxcan_enable_filters(priv, priv->master); + + /* Clear all internal status */ + priv->tx_head = 0; + priv->tx_tail = 0; + + err = bxcan_leave_init_mode(priv); + if (err) { + netdev_err(ndev, "failed to leave init mode, error %d\n", err); + goto failed_leave_init; + } + + /* Set a `lec` value so that we can check for updates later */ + bxcan_rmw(priv, ®s->esr, BXCAN_ESR_LEC_MASK, + FIELD_PREP(BXCAN_ESR_LEC_MASK, BXCAN_LEC_UNUSED)); + + /* IER + * + * Enable interrupt for: + * bus-off + * passive error + * warning error + * last error code + * RX FIFO pending message + * TX mailbox empty + */ + clr = BXCAN_IER_WKUIE | BXCAN_IER_SLKIE | BXCAN_IER_FOVIE1 | + BXCAN_IER_FFIE1 | BXCAN_IER_FMPIE1 | BXCAN_IER_FOVIE0 | + BXCAN_IER_FFIE0; + set = BXCAN_IER_ERRIE | BXCAN_IER_BOFIE | BXCAN_IER_EPVIE | + BXCAN_IER_EWGIE | BXCAN_IER_FMPIE0 | BXCAN_IER_TMEIE; + + if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) + set |= BXCAN_IER_LECIE; + else + clr |= BXCAN_IER_LECIE; + + bxcan_rmw(priv, ®s->ier, clr, set); + + priv->can.state = CAN_STATE_ERROR_ACTIVE; + return 0; + +failed_leave_init: +failed_enter_init: +failed_leave_sleep: + bxcan_chip_softreset(priv); + return err; +} + +static int bxcan_open(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + int err; + + err = open_candev(ndev); + if (err) { + netdev_err(ndev, "open_candev() failed, error %d\n", err); + return err; + } + + can_rx_offload_enable(&priv->offload); + err = request_irq(ndev->irq, bxcan_rx_isr, IRQF_SHARED, ndev->name, + ndev); + if (err) { + netdev_err(ndev, "failed to register rx irq(%d), error %d\n", + ndev->irq, err); + goto out_close_candev; + } + + err = request_irq(priv->tx_irq, bxcan_tx_isr, IRQF_SHARED, ndev->name, + ndev); + if (err) { + netdev_err(ndev, "failed to register tx irq(%d), error %d\n", + priv->tx_irq, err); + goto out_free_rx_irq; + } + + err = request_irq(priv->sce_irq, bxcan_state_change_isr, IRQF_SHARED, + ndev->name, ndev); + if (err) { + netdev_err(ndev, "failed to register sce irq(%d), error %d\n", + priv->sce_irq, err); + goto out_free_tx_irq; + } + + err = bxcan_chip_start(ndev); + if (err) + goto out_free_sce_irq; + + netif_start_queue(ndev); + return 0; + +out_free_sce_irq: + free_irq(priv->sce_irq, ndev); +out_free_tx_irq: + free_irq(priv->tx_irq, ndev); +out_free_rx_irq: + free_irq(ndev->irq, ndev); +out_close_candev: + can_rx_offload_disable(&priv->offload); + close_candev(ndev); + return err; +} + +static void bxcan_chip_stop(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + + /* disable all interrupts */ + bxcan_rmw(priv, ®s->ier, BXCAN_IER_SLKIE | BXCAN_IER_WKUIE | + BXCAN_IER_ERRIE | BXCAN_IER_LECIE | BXCAN_IER_BOFIE | + BXCAN_IER_EPVIE | BXCAN_IER_EWGIE | BXCAN_IER_FOVIE1 | + BXCAN_IER_FFIE1 | BXCAN_IER_FMPIE1 | BXCAN_IER_FOVIE0 | + BXCAN_IER_FFIE0 | BXCAN_IER_FMPIE0 | BXCAN_IER_TMEIE, 0); + bxcan_disable_filters(priv, priv->master); + bxcan_enter_sleep_mode(priv); + priv->can.state = CAN_STATE_STOPPED; +} + +static int bxcan_stop(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + + netif_stop_queue(ndev); + bxcan_chip_stop(ndev); + free_irq(ndev->irq, ndev); + free_irq(priv->tx_irq, ndev); + free_irq(priv->sce_irq, ndev); + can_rx_offload_disable(&priv->offload); + close_candev(ndev); + return 0; +} + +static netdev_tx_t bxcan_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct can_frame *cf = (struct can_frame *)skb->data; + struct bxcan_regs __iomem *regs = priv->regs; + struct bxcan_mb __iomem *mb_regs; + unsigned int idx; + u32 id; + int i, j; + + if (can_dropped_invalid_skb(ndev, skb)) + return NETDEV_TX_OK; + + if (bxcan_tx_busy(priv)) + return NETDEV_TX_BUSY; + + idx = bxcan_get_tx_head(priv); + priv->tx_head++; + if (bxcan_get_tx_free(priv) == 0) + netif_stop_queue(ndev); + + mb_regs = ®s->tx_mb[idx]; + if (cf->can_id & CAN_EFF_FLAG) + id = FIELD_PREP(BXCAN_TIxR_EXID_MASK, cf->can_id) | + BXCAN_TIxR_IDE; + else + id = FIELD_PREP(BXCAN_TIxR_STID_MASK, cf->can_id); + + if (cf->can_id & CAN_RTR_FLAG) + id |= BXCAN_TIxR_RTR; + + writel(FIELD_PREP(BXCAN_TDTxR_DLC_MASK, cf->len), &mb_regs->dlc); + + for (i = 0, j = 0; i < cf->len; i += 4, j++) + writel(*(u32 *)(cf->data + i), &mb_regs->data[j]); + + can_put_echo_skb(skb, ndev, idx, 0); + + /* Start transmission */ + writel(id | BXCAN_TIxR_TXRQ, &mb_regs->id); + + return NETDEV_TX_OK; +} + +static const struct net_device_ops bxcan_netdev_ops = { + .ndo_open = bxcan_open, + .ndo_stop = bxcan_stop, + .ndo_start_xmit = bxcan_start_xmit, + .ndo_change_mtu = can_change_mtu, +}; + +static int bxcan_do_set_mode(struct net_device *ndev, enum can_mode mode) +{ + int err; + + switch (mode) { + case CAN_MODE_START: + err = bxcan_chip_start(ndev); + if (err) + return err; + + netif_wake_queue(ndev); + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int bxcan_get_berr_counter(const struct net_device *ndev, + struct can_berr_counter *bec) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + u32 esr; + int err; + + err = clk_prepare_enable(priv->clk); + if (err) + return err; + + esr = readl(®s->esr); + bec->txerr = FIELD_GET(BXCAN_ESR_TEC_MASK, esr); + bec->rxerr = FIELD_GET(BXCAN_ESR_REC_MASK, esr); + clk_disable_unprepare(priv->clk); + return 0; +} + +static int bxcan_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct net_device *ndev; + struct bxcan_priv *priv; + struct clk *clk = NULL; + void __iomem *regs; + struct regmap *gcan; + bool master; + int err, rx_irq, tx_irq, sce_irq; + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(regs); + } + + gcan = syscon_regmap_lookup_by_phandle(np, "st,gcan"); + if (IS_ERR(gcan)) { + dev_err(dev, "failed to get shared memory base address\n"); + return PTR_ERR(gcan); + } + + master = of_property_read_bool(np, "st,can-master"); + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(clk); + } + + rx_irq = platform_get_irq_byname(pdev, "rx0"); + if (rx_irq < 0) { + dev_err(dev, "failed to get rx0 irq\n"); + return rx_irq; + } + + tx_irq = platform_get_irq_byname(pdev, "tx"); + if (tx_irq < 0) { + dev_err(dev, "failed to get tx irq\n"); + return tx_irq; + } + + sce_irq = platform_get_irq_byname(pdev, "sce"); + if (sce_irq < 0) { + dev_err(dev, "failed to get sce irq\n"); + return sce_irq; + } + + ndev = alloc_candev(sizeof(struct bxcan_priv), BXCAN_TX_MB_NUM); + if (!ndev) { + dev_err(dev, "alloc_candev() failed\n"); + return -ENOMEM; + } + + priv = netdev_priv(ndev); + platform_set_drvdata(pdev, ndev); + SET_NETDEV_DEV(ndev, dev); + ndev->netdev_ops = &bxcan_netdev_ops; + ndev->irq = rx_irq; + ndev->flags |= IFF_ECHO; + + priv->dev = dev; + priv->ndev = ndev; + priv->regs = regs; + priv->gcan = gcan; + priv->clk = clk; + priv->tx_irq = tx_irq; + priv->sce_irq = sce_irq; + priv->master = master; + priv->can.clock.freq = clk_get_rate(clk); + spin_lock_init(&priv->rmw_lock); + priv->tx_head = 0; + priv->tx_tail = 0; + priv->can.bittiming_const = &bxcan_bittiming_const; + priv->can.do_set_mode = bxcan_do_set_mode; + priv->can.do_get_berr_counter = bxcan_get_berr_counter; + priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | + CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING; + + priv->offload.mailbox_read = bxcan_mailbox_read; + err = can_rx_offload_add_fifo(ndev, &priv->offload, BXCAN_NAPI_WEIGHT); + if (err) { + dev_err(dev, "failed to add FIFO rx_offload\n"); + goto out_free_candev; + } + + err = clk_prepare_enable(priv->clk); + if (err) { + dev_err(dev, "failed to enable clock\n"); + goto out_can_rx_offload_del; + } + + err = register_candev(ndev); + if (err) { + dev_err(dev, "failed to register netdev\n"); + goto out_clk_disable_unprepare; + } + + dev_info(dev, "clk: %d Hz, IRQs: %d, %d, %d\n", priv->can.clock.freq, + tx_irq, rx_irq, sce_irq); + return 0; + +out_clk_disable_unprepare: + clk_disable_unprepare(priv->clk); +out_can_rx_offload_del: + can_rx_offload_del(&priv->offload); +out_free_candev: + free_candev(ndev); + return err; +} + +static int bxcan_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct bxcan_priv *priv = netdev_priv(ndev); + + unregister_candev(ndev); + clk_disable_unprepare(priv->clk); + can_rx_offload_del(&priv->offload); + free_candev(ndev); + return 0; +} + +static int __maybe_unused bxcan_suspend(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct bxcan_priv *priv = netdev_priv(ndev); + + if (!netif_running(ndev)) + return 0; + + netif_stop_queue(ndev); + netif_device_detach(ndev); + + bxcan_enter_sleep_mode(priv); + priv->can.state = CAN_STATE_SLEEPING; + clk_disable_unprepare(priv->clk); + return 0; +} + +static int __maybe_unused bxcan_resume(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct bxcan_priv *priv = netdev_priv(ndev); + + if (!netif_running(ndev)) + return 0; + + clk_prepare_enable(priv->clk); + bxcan_leave_sleep_mode(priv); + priv->can.state = CAN_STATE_ERROR_ACTIVE; + + netif_device_attach(ndev); + netif_start_queue(ndev); + return 0; +} + +static SIMPLE_DEV_PM_OPS(bxcan_pm_ops, bxcan_suspend, bxcan_resume); + +static const struct of_device_id bxcan_of_match[] = { + {.compatible = "st,stm32f4-bxcan"}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, bxcan_of_match); + +static struct platform_driver bxcan_driver = { + .driver = { + .name = KBUILD_MODNAME, + .pm = &bxcan_pm_ops, + .of_match_table = bxcan_of_match, + }, + .probe = bxcan_probe, + .remove = bxcan_remove, +}; + +module_platform_driver(bxcan_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("STMicroelectronics Basic Extended CAN controller driver"); +MODULE_LICENSE("GPL");