From patchwork Sun Nov 13 15:59:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 19377 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1734271wru; Sun, 13 Nov 2022 07:59:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf6UaffQ3pgMQ8FBWUPEgyZ1w0NjPvFeXfX26jZyJ7aXFqFS00lpHVsZrr+VwlvCwDH+3OS8 X-Received: by 2002:aa7:de92:0:b0:467:8fb6:d11 with SMTP id j18-20020aa7de92000000b004678fb60d11mr5073641edv.421.1668355175720; Sun, 13 Nov 2022 07:59:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668355175; cv=none; d=google.com; s=arc-20160816; b=rO6LZKGtuYzL0YgG8KGycrPK9WcjN9sDvhKau5t670kRTGKtn08YOS1hncoj2S8gKx rTuM71xA3u/MIqX6yos+bhQYcTy56GtbqrUUtykblxWFzIbqmS84BIAJMujZkmylJ6LF 08Oay7nMkY7OR5FV2jlOTB2j3jXndaY8IXSr7fWADhGm5LJsVXCoeH2mDHyp8dZrDL9Q 2lsNBmUlTfUMl1NUz1UYanNIw4OUsaR5axTCn5Pmq8u3EzSiJ4ah4b44EHmumoangDbe 5rExZonUlc2CTXrryySPO61djrm56THmGKFJuxeeluU9Cy2Q/eaHoXw0drVB/KmO8SsY tdbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :dmarc-filter:delivered-to; bh=p2o0fgBVmPKwrc0Oz9SNodHU9eWxmE1jmkgPJp/lXl8=; b=fGShgbqsqAEIFK1FELXjdw/1zEcDvs5vwm+1ETdK7udlOlFNXdIMG9P6i5f1dmBRF3 YLXpO3Iae+fl2zDDO/deSVDIlmOfnscX3PUDUNbXfqR9gJ3bkpoFWm6qAotIs3hEWLiK hNkxDSLK8mmxDszDFWVWGsKoQYRzvkBRX9bg3KOBSXlaGZEvBOUVeTaGZyn/Yrw1WDv7 M3KSEkUpWAoOmskgrucN08Rpo2MGJ0goHmoqdb5S3OoPbnJ8deUd1IsgPjIRijDAB4e4 bKGjq7fL6X5ac+uDQFGE5ACrLF03TGB8dRWn9kUoR72QRAjhHPl/pIsrwMUPU+5dxcQU V1mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=TdZkVn2+; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sb3-20020a170906edc300b007aa5e6c4b5bsi5788675ejb.164.2022.11.13.07.59.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 07:59:35 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=TdZkVn2+; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 881A5383469A for ; Sun, 13 Nov 2022 15:59:33 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id 284813858280 for ; Sun, 13 Nov 2022 15:59:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 284813858280 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x62a.google.com with SMTP id n12so22870014eja.11 for ; Sun, 13 Nov 2022 07:59:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=p2o0fgBVmPKwrc0Oz9SNodHU9eWxmE1jmkgPJp/lXl8=; b=TdZkVn2+wqwh9iSpUyyUOoBEYlVgKvGlBtogaiEKfF1+eyKH/u0XYcSQxjsGSztcFP CcMyyF95Lmzzb7FX73aP8eigjgFZWGDwkYBdpOs18d+ywL42TBFzjZ0Q0a5ZRwBYORZc NDdLrWMs5ajFiEDHVZK+rMT/SKN95Lbo3tFpLimSo6bifNlUEkn8HwXQhSrT+0v1U+63 Aq/C1ojACGRxr5IiRG2XdnSQce24TLm+OEux8cXLDVqjOY5mycC3npN5P56B1at4/6ko PFfUAW1O+V9z+V1GFb/Tcg7DgOs7VhIfrAiNQZQRraBnTK98cIgSBGBtWFfyTx1oNMAH /7ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=p2o0fgBVmPKwrc0Oz9SNodHU9eWxmE1jmkgPJp/lXl8=; b=Ks2mTgXu+m0SJ0MDQDMVz0KTvM3XtfF7Y8klC7mgpWEihZOfehwb/tYzQYpBJAuR0W 3SdE1W5qckOBekAlXNHPn3JK1qdrdmkSzifzWR79iKehsJMle18AVXryUsnuc08mY3Au Pr/fHx79cavN02Sm4CHWFUY6eZVFo6IgfXAq9c96bZs6c8RCk3kWjId90tXkqy/m2NgM XujazNOamzQLN1LN01/QDimNT+7d7ZNIcjGsyGxz/ogo0lVzGTROq2unCPBvH8Nf4IlJ WqMnT9blHnGfgy9S2g6ELcJv3O6tBR20iFEM5HSiHWAu86nGzGMjKI89wTlnisMZouP+ y1Iw== X-Gm-Message-State: ANoB5pnx0xI66Y9e7l+T5IYQ7Xb1nAHnkaayyfn/YsjsF7Wu2mbvM+kx wtfxIa5AQpCwUKsEMJkJtI1J+a/8nwNhGniB X-Received: by 2002:a17:906:2305:b0:78e:975:f0b4 with SMTP id l5-20020a170906230500b0078e0975f0b4mr7807217eja.641.1668355165608; Sun, 13 Nov 2022 07:59:25 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id l9-20020a1709060cc900b0078ddb518a90sm3097952ejh.223.2022.11.13.07.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 07:59:25 -0800 (PST) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 1/2] RISC-V: Add T-Head Fmv vendor extension Date: Sun, 13 Nov 2022 16:59:20 +0100 Message-Id: <20221113155921.1445808-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749397196583423882?= X-GMAIL-MSGID: =?utf-8?q?1749397196583423882?= From: Christoph Müllner This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/NEWS | 6 +++--- gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-fmv.d | 11 +++++++++++ gas/testsuite/gas/riscv/x-thead-fmv.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 8 files changed, 40 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/riscv/x-thead-fmv.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmv.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 300ccf49534..a1e42064ee0 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1239,6 +1239,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadfmv", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2419,6 +2420,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadcondmov"); case INSN_CLASS_XTHEADFMEMIDX: return riscv_subset_supports (rps, "xtheadfmemidx"); + case INSN_CLASS_XTHEADFMV: + return riscv_subset_supports (rps, "xtheadfmv"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADMEMIDX: @@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadcondmov"; case INSN_CLASS_XTHEADFMEMIDX: return "xtheadfmemidx"; + case INSN_CLASS_XTHEADFMV: + return "xtheadfmv"; case INSN_CLASS_XTHEADMAC: return "xtheadmac"; case INSN_CLASS_XTHEADMEMIDX: diff --git a/gas/NEWS b/gas/NEWS index 86731348e3e..1c2da4ed97b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -26,9 +26,9 @@ for --enable-compressed-debug-sections. * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs, - XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadMemIdx, XTheadMemPair, - XTheadMac, and XTheadSync) from version 2.0 of the T-Head ISA manual, which - are implemented in the Allwinner D1. + XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx, + XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head + ISA manual, which are implemented in the Allwinner D1. * Add support for the RISC-V Zawrs extension, version 1.0-rc4. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index cc63760cb80..f2a69d8b950 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -734,6 +734,11 @@ The XTheadFMemIdx extension provides floating-point memory operations. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadFmv +The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d new file mode 100644 index 00000000000..f2bbe010beb --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_xtheadfmv +#source: x-thead-fmv.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 +[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s new file mode 100644 index 00000000000..250ba8358ae --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s @@ -0,0 +1,3 @@ +target: + th.fmv.hw.x a0, fa1 + th.fmv.x.hw a1, fa0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e40592159cd..d7d9dbc83f6 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2208,6 +2208,11 @@ #define MASK_TH_FSURD 0xf800707f #define MATCH_TH_FSURW 0x5000700b #define MASK_TH_FSURW 0xf800707f +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +#define MATCH_TH_FMV_HW_X 0x6000100b +#define MASK_TH_FMV_HW_X 0xfff0707f +#define MATCH_TH_FMV_X_HW 0x5000100b +#define MASK_TH_FMV_X_HW 0xfff0707f /* Vendor-specific (T-Head) XTheadMac instructions. */ #define MATCH_TH_MULA 0x2000100b #define MASK_TH_MULA 0xfe00707f @@ -3122,6 +3127,9 @@ DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD) DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW) DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD) DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X) +DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW) /* Vendor-specific (T-Head) XTheadMac instructions. */ DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dddabfdd415..f90cf97ceb2 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -416,6 +416,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, + INSN_CLASS_XTHEADFMV, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 599486fdf03..dfd508b0e71 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1931,6 +1931,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, +{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, From patchwork Sun Nov 13 15:59:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 19378 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1734308wru; Sun, 13 Nov 2022 07:59:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf6dkpe7osLS+D6tnp451pZPZfWJtEf44kYt3CJldDHziR/MlxIBMDR2dGDcTHRbVwi/byxV X-Received: by 2002:aa7:c983:0:b0:461:c6e8:452e with SMTP id c3-20020aa7c983000000b00461c6e8452emr8282650edt.298.1668355180416; Sun, 13 Nov 2022 07:59:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668355180; cv=none; d=google.com; s=arc-20160816; b=Bp+S6YO8va8NB8kdnt5Nt/KXP+se/+WVPvQmbWfQkF6FqTDHnnMRpTZxm+c6vuFezn Mg/GSPVx74RY7R4vRpF3aIkaDFUMACIUzsdCrBzwwbsxPBL4iTstXlo8TvNmD035daiE hnXIkkk8yfKMB4facKGAU6X7QukYOQuWl3voFEG+TwZoQhXcqqJOeisWkT4K/Q2i5iMl UIvMRCIpwqIAJZHTcp2s7b7AsrIIvrSLiwrYwAreLUOIVOlVXZlrCUj5KYzuEJGWsc/k h7cQvPac/Hm1FD3Ox6dArp9VmHh0aCccqKGMVFvhF1+MzP9SZPn0ZMZ4KRiBc8qxd5TP XwjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=kPCzMjUaXz1MtArcgAyEaGg68DDt5GFawXWh1fn4HtQ=; b=c5kcD2eDmhLgvmK2+LaM50BxEcvoY0Md6ePyIZmrzRY0Ovuw0FLoWXlw5foiJq9PNY pRQI3W/Hzox0XjYxI7xmnD5n7BaQE8R8N+pYV7TQJc3r18VPQgEXBRADC/0X4XumfgkC 2UDd+HO+CgOBDRPM+trHMUPPenqufVHwYMDbPa8HwSAgfM/jmtUpRVN8ZK9Noa9shcEI JEXxEMY8QnsbSw1oGyPig02zIliIm3P3Pusv5T0CdPFUzPJ6Mbz/SqTeuIsJhsQEEyXK oFrmtgfPcG5/iSVv0IjTPBvCdsdMp42UXkwgNpwXpQ8DLld80c0NMSSSwgtsvYKrtywy VYmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=j3x+5VaM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y15-20020a170906470f00b00783e7d72fc0si6030915ejq.272.2022.11.13.07.59.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 07:59:40 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=j3x+5VaM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E2B4F3846469 for ; Sun, 13 Nov 2022 15:59:35 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 75AD33858291 for ; Sun, 13 Nov 2022 15:59:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 75AD33858291 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x534.google.com with SMTP id 21so14017532edv.3 for ; Sun, 13 Nov 2022 07:59:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kPCzMjUaXz1MtArcgAyEaGg68DDt5GFawXWh1fn4HtQ=; b=j3x+5VaMC92JqPyXW+xHwbCEZqlk+Sp8rqKzecJMixc4jiibWKZUqU34QtmjObHHcK LQngktqJCK0CuFq1UBSuTavZjxP/eLsRnwbAfzE3dM7H2yfLve76Ir3TQMM0Tb/ieju5 olRDoKPVRUgn5nJd186VEr/HpzXjZhQMzvB7c+ieK7/yrmsTEsxTLGyNOmoBCutHgT+r HbCJtyTaQVeR1MDfsUM+LgDdDQ8VizMk52n7hJivFtlJWPCQsuaXjtcwDqfsdq3XlltS 60mUWMZEP+LqLhMiPosiw3YFFhzbFCDa8aRW+tvP70iKkIhK8zJtJycXpbS2Z//DylQc g2YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kPCzMjUaXz1MtArcgAyEaGg68DDt5GFawXWh1fn4HtQ=; b=UfSKcikjauS8uFViscQaPFHyMMeutdXcCr49lx0zmEkI1B/nEHkZe3PLFaJRJQTfJ9 3orzUn4S67wTY4XQ20xYDUcXFcL0t4bzJEJcOm1IuTnkD8iDnfUkI9ItZQ3JOZAkkbny 7+hm9AF2QUfM1pg/lYSCjLZfCFydX941S4H2SolT5dQHHS3PSznqrzrunsoFdouqFwGz YazihvJwEVmLA0azo2TTGjIvUIN4r5cqtnzSVcS3ihbG8BYfDU8twZyjNkh0udf3Uaqm 1FaJo5IuUIReEJ8H57owyiaor+5Gxu0LPk91EkcBrcWS3xS31MUlVQwXC505ET0wDFup OrFg== X-Gm-Message-State: ANoB5pll6t5vqY/svNWqxx8KtBJ4WKWww1QO1VYP+NSQf2TzsMv34sZb 4ewYsjaJWg7g+uozBD/nx1XUyKYgauckPex8 X-Received: by 2002:a05:6402:519:b0:467:6847:1ea7 with SMTP id m25-20020a056402051900b0046768471ea7mr7567273edv.237.1668355167882; Sun, 13 Nov 2022 07:59:27 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id l9-20020a1709060cc900b0078ddb518a90sm3097952ejh.223.2022.11.13.07.59.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 07:59:27 -0800 (PST) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 2/2] RISC-V: Add T-Head Int vendor extension Date: Sun, 13 Nov 2022 16:59:21 +0100 Message-Id: <20221113155921.1445808-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113155921.1445808-1-christoph.muellner@vrull.eu> References: <20221113155921.1445808-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749397201642376139?= X-GMAIL-MSGID: =?utf-8?q?1749397201642376139?= From: Christoph Müllner This patch adds the XTheadInt extension, which provides interrupt stack management instructions. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/NEWS | 2 +- gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-int.d | 11 +++++++++++ gas/testsuite/gas/riscv/x-thead-int.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 8 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/x-thead-int.d create mode 100644 gas/testsuite/gas/riscv/x-thead-int.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index a1e42064ee0..cfec9a6996c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1240,6 +1240,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadfmv", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadint", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2422,6 +2423,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadfmemidx"); case INSN_CLASS_XTHEADFMV: return riscv_subset_supports (rps, "xtheadfmv"); + case INSN_CLASS_XTHEADINT: + return riscv_subset_supports (rps, "xtheadint"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADMEMIDX: @@ -2578,6 +2581,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadfmemidx"; case INSN_CLASS_XTHEADFMV: return "xtheadfmv"; + case INSN_CLASS_XTHEADINT: + return "xtheadint"; case INSN_CLASS_XTHEADMAC: return "xtheadmac"; case INSN_CLASS_XTHEADMEMIDX: diff --git a/gas/NEWS b/gas/NEWS index 1c2da4ed97b..934871d26df 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -26,7 +26,7 @@ for --enable-compressed-debug-sections. * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs, - XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx, + XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadInt, XTheadMemIdx, XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head ISA manual, which are implemented in the Allwinner D1. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index f2a69d8b950..d61e8e47fa4 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -739,6 +739,11 @@ The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precisi It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. +@item XTheadInt +The XTheadInt extension provides access to ISR stack management instructions. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. diff --git a/gas/testsuite/gas/riscv/x-thead-int.d b/gas/testsuite/gas/riscv/x-thead-int.d new file mode 100644 index 00000000000..23a82a2c809 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-int.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_xtheadint +#source: x-thead-int.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+0040000b[ ]+th.ipush +[ ]+[0-9a-f]+:[ ]+0050000b[ ]+th.ipop diff --git a/gas/testsuite/gas/riscv/x-thead-int.s b/gas/testsuite/gas/riscv/x-thead-int.s new file mode 100644 index 00000000000..23d867423d4 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-int.s @@ -0,0 +1,3 @@ +target: + th.ipush + th.ipop diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index d7d9dbc83f6..f36b06dcd6b 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2213,6 +2213,11 @@ #define MASK_TH_FMV_HW_X 0xfff0707f #define MATCH_TH_FMV_X_HW 0x5000100b #define MASK_TH_FMV_X_HW 0xfff0707f +/* Vendor-specific (T-Head) XTheadInt instructions. */ +#define MATCH_TH_IPOP 0x0050000b +#define MASK_TH_IPOP 0xffffffff +#define MATCH_TH_IPUSH 0x0040000b +#define MASK_TH_IPUSH 0xffffffff /* Vendor-specific (T-Head) XTheadMac instructions. */ #define MATCH_TH_MULA 0x2000100b #define MASK_TH_MULA 0xfe00707f @@ -3130,6 +3135,9 @@ DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) /* Vendor-specific (T-Head) XTheadFmv instructions. */ DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X) DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW) +/* Vendor-specific (T-Head) XTheadInt instructions. */ +DECLARE_INSN(th_ipop, MATCH_TH_IPOP, MASK_TH_IPOP) +DECLARE_INSN(th_ipush, MATCH_TH_IPUSH, MASK_TH_IPUSH) /* Vendor-specific (T-Head) XTheadMac instructions. */ DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f90cf97ceb2..c3cbde600cb 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -417,6 +417,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADFMV, + INSN_CLASS_XTHEADINT, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index dfd508b0e71..0e691544f9b 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1935,6 +1935,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadInt instructions. */ +{"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, MASK_TH_IPOP, match_opcode, 0}, +{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0},