From patchwork Mon Jan 8 08:49:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 185853 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp903962dyq; Mon, 8 Jan 2024 01:05:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IEZdpJf14um0qrZkFpCvVeN9x8y6MsZlhu6lNW+u6B0zfvf+d7x4xvwpxfQ7vQgTlXaz535 X-Received: by 2002:a05:622a:12:b0:429:7dc6:4785 with SMTP id x18-20020a05622a001200b004297dc64785mr5085018qtw.60.1704704700126; Mon, 08 Jan 2024 01:05:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704704700; cv=none; d=google.com; s=arc-20160816; b=UugSC2sbHO6OihtJCo2qsh6UAdqnFXzjO/AgMDw9Xr6AdHWZnIwpo5RNhHZYniHIh/ vR+yCKEwJOCH4Wi8Z3tyFW4qXYi0nshpuK+nthijDU5whzFpMxejKsU4NselEjx+8GNT 53zt1nTD1EzASIe22k+7XxBu6+qoYbPS0zTzyrCGcxnT+kIoovhsTBd0c/z6G5qyoD1B sNp+s0pNFCTf1W6nFhsEsTC35yqH+Ghl+MRzPAGFT+VXJah4yqwpoVtonIXufyrgZuzs WzHRZyFzwad9nLHKDXLcFMUBSeVzHwJf7DyBv58Ezsi2lyJ+hwtefgqqfCY2NQLtzsoF LxOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=akNdEaX30HzkHKP9IaufaAprUiB8tYROpt6AP/lowi0=; fh=mWDe8CjyAdhhjLFVNrKsiT00acIg4QHc0YGM2tZgom8=; b=SzKul35tcEi5RcMyQS2tOARaKRhno77z/UUMkTBTGqdWlL9uD4NQiUiWKk2UH2JqPr 1SDBeaW6duqnAGJSZ94vGkHFXDjWifAi3nI0ke/RpHSTTAQ4WRnE/33aQjqZDrkgMKod kYuKw7VFgrhWW1phTAQU4S7AFTKOabFXG/aM2TLL4KjsCxrPauhLmQj70n55DbbHM3yC wH+UmZ3B56I9b5hFOqNg26/LGfzRzPPWs/Y/gSZimCYuDRejSeEFM0hkA3GVzVL21Zdd IBuUfJ9RTSg/gKiFOGZlPmD1u555DvBq+hbQ8NXC2dE4nqr2GU8GZpnEw9o3o9S0y7ZM 10EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=K4BsnmzL; spf=pass (google.com: domain of linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id n13-20020a05622a040d00b0042979913212si6567577qtx.454.2024.01.08.01.05.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 01:05:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=K4BsnmzL; spf=pass (google.com: domain of linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 44D731C22B17 for ; Mon, 8 Jan 2024 08:59:32 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A17F413FF9; Mon, 8 Jan 2024 08:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="K4BsnmzL" X-Original-To: linux-kernel@vger.kernel.org Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DDA0E543; Mon, 8 Jan 2024 08:58:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A1246C00F6; Mon, 8 Jan 2024 09:51:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1704703877; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=akNdEaX30HzkHKP9IaufaAprUiB8tYROpt6AP/lowi0=; b=K4BsnmzL+Kuq5/Qqu0wqe9rMKbqqu1F81mBa60iTXsSP2dLjqr1aWoEkd7BGz+EWvZiUts 7EKCFBGLq+qnAUcEVoeiOds+dFAToqV07+u26TLGK0IweTryL0ZsfXskWAG66mOB5qsmzz jwFMBG35c7Q4bhzMknigiPVicy7fDD5c8BC8Xe4uN7gnTAAhOQ6I+pfYO8EFa/ZHLGk4xM rgDVv3KndMnMGmE8awsSuGeGzyrSBZkHMGDbchqO560Z3VzjfWFvpKvhfwsW31c8NgJZVq LK5wWCHdjb7r+/Tbjw7fBWzAp/ImYUuSZPmEmtDSbHB9DwwGgzIixdBJpKoBig== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v4 04/12] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board Date: Mon, 8 Jan 2024 09:49:01 +0100 Message-ID: <20240108084945.75356-5-frieder@fris.de> In-Reply-To: <20240108084945.75356-1-frieder@fris.de> References: <20240108084945.75356-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787512435710610821 X-GMAIL-MSGID: 1787512435710610821 From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index 5fd2e45258b11..ee93db11c0d06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -292,19 +292,19 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; From patchwork Mon Jan 8 08:49:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 185846 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp899252dyq; Mon, 8 Jan 2024 00:51:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IGbUpi32K0idstRRUNVNaG7NfmCqbfLalTU+lqd0tdWTosLddOqBd8m1jDU4hmzmUyu3Nvq X-Received: by 2002:a05:6870:1692:b0:203:88b1:31ce with SMTP id j18-20020a056870169200b0020388b131cemr908867oae.117.1704703905640; Mon, 08 Jan 2024 00:51:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704703905; cv=none; d=google.com; s=arc-20160816; b=XwIUAgAnu49gkJzhea8lxOVZjySYvHxPEabegvJBjqtDTedNR3uFhmX3znosUj4WdU e3a26dmObuVniCccPGVKCCAeWYEp5V/dzuKh5Hh92tgaMkwa9kOCjbHFJUDbR7Dqdx81 ecrP/4k0TDZdHmnY2/lH4KZpW5y+O/XCVnxGvXmB0wdREcSMpGisuB9V5QslNDzHmQ61 VYT2lwe1CnRZig+ZFA5yrQOQrozvJ0AV6QQ7UPuLNfkM3d8S7Idk9ud1dly1iUcNYurD p5YA7rj+M+pT4pRSCKencJweUp4ks6a3yjg7KmFgL2LcNo51PO58IJXMyihpXnUhLjKc su+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=tMSX8hysbUP88C2UKn2uKuZ0nkUjhmVSfTTqVo0O4Rk=; fh=5WBVB9KggvEUZrfL2cFjcxt7hrbLV0CECJcyvKKi3zA=; b=uYco6/uj5KhbJVu/J7l2T5xkJuImOOaf2eFWMuv0hZrCAp0ynsQTzIwJp/LiRo5PJ1 RE6aWWYkvjzMLX7HS/K+KtQPRqGi7eOHe3Y+9/BB+jiIXp4zkOTdXVP5PclyEPq+ocQV ctvAe80jmUq5Hl2MuR9o3kNv9icrrv2LvtYGeA4fevDSPYMv/tdo3Y2owsbeBDaSIrtT 1xO3rqo63M52V6GTsfifPZsG6f1B9YPAFcWsA27FCAf4S3Dxy2RxeaaBgvcr8lueA85g 3ZqRP/Vq+LXB5f74KkbCLIrS/P4hMDz3G/m1u89Y3aHp2MjOD7+MkkCYDDeUL8Kvmvak lksw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=PatAFwUB; spf=pass (google.com: domain of linux-kernel+bounces-19204-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19204-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id 23-20020a631057000000b005ce021fec42si5792741pgq.589.2024.01.08.00.51.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 00:51:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19204-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=PatAFwUB; spf=pass (google.com: domain of linux-kernel+bounces-19204-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19204-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 59C33282839 for ; Mon, 8 Jan 2024 08:51:44 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 59E1211199; Mon, 8 Jan 2024 08:51:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="PatAFwUB" X-Original-To: linux-kernel@vger.kernel.org Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C64AC13C; Mon, 8 Jan 2024 08:51:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 97E9BC00F8; Mon, 8 Jan 2024 09:51:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1704703878; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=tMSX8hysbUP88C2UKn2uKuZ0nkUjhmVSfTTqVo0O4Rk=; b=PatAFwUBLRjjvvpinFB2Y5qfNyhMEPQTgUeyLsILD+IekdyVmKRAMfJQoRa9R5K0vqIzG5 FFToKWzRRTpHINrht7RgI4W4o4n6+q9VznVtagrA+JP+nCsXDMzEd9OPZgxfIGDgGjlR4e UAyHqPR/oTTrN7kQky0lw/N//x3vlwcrDw+0Ni7zNLHlxEtuVj5vKYuu12maqG+DMvWUfv 3P/WbLRNLe9tUrb/p4GVVII5Y9ZyahpXgnNBiSj2SDfwgfQkijQtIFsaPnjO073eMyORsO cWpwZdyVx20GA5MFi4RFO70DjwvL0z3qACQUkv1Ypwecg4mBHC9kjpxJetEgcA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v4 05/12] arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL OSM-S board Date: Mon, 8 Jan 2024 09:49:02 +0100 Message-ID: <20240108084945.75356-6-frieder@fris.de> In-Reply-To: <20240108084945.75356-1-frieder@fris.de> References: <20240108084945.75356-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787511602591042348 X-GMAIL-MSGID: 1787511602591042348 From: Frieder Schrempf Some signals have external pullup resistors on the board and don't need the internal ones to be enabled. Due to silicon errata ERR050080 let's disable the internal pull resistors whererever possible and prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 1dd03ef0a7835..d9fa0deea7002 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -337,40 +337,40 @@ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; From patchwork Mon Jan 8 08:49:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 185847 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp899304dyq; Mon, 8 Jan 2024 00:52:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IGUbdsT5TgSg7pmsClTHleEqPEow18LKokChwKoQC/doNv83pjJaRvbaEUvpJwISZgW/o+t X-Received: by 2002:a17:906:4f8f:b0:a28:9546:f92a with SMTP id o15-20020a1709064f8f00b00a289546f92amr2956035eju.67.1704703920836; Mon, 08 Jan 2024 00:52:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704703920; cv=none; d=google.com; s=arc-20160816; b=Wm7eQFuznMeOr3NOtZWP/QcIA7QtmyJxdEI2BKaU+eV8/IE2owZBR1p6oJTIIaYg4T uc/bhlZXu4fTNx5rOaWMC66/QrFmyeQ+fBRiaQabyWC0+e4S3BrUlgxK/nYsnxJsYjhC J7h/2REZQDJj2+T6YLnKn3ExElhITQ2go6++RBBtraKROca3pfWHxKCeC5ggrNYXET1j FMMXRSQGXvr7se+hJEpAWT02RRif30OCoSC+NiZQtcdu3jYpX4SOq9adzTho6o+iACEt Sq4pOmasRGCyMRx0RmoWNIY1DMfBvQldTaUX/E2Z7ZDBB/jlI0/APDFaRiLalWiwpITf o5uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hAu4/xuLsSrHwTANNA7s3QmXGy5YS+glepKpDYXmA5o=; fh=mWDe8CjyAdhhjLFVNrKsiT00acIg4QHc0YGM2tZgom8=; b=YKeZIdCJe/rOe78Q0Q16SErxvuo1x7okbDwUP7h25+4RwtInNJI6d6ujh48Z8aKj2a C65SsfkHlzsoNVUyvPYtCzU/8IkY4ip5BHjTtdXn7VSzRa3JWUsp1Wklq/CT/VuzSkXw yxRKileS6qsyiqI6NOxDDeNf9X+8Dbyid1n0fjdOsApeHnW+ZFUdGNRb7LWpECzkNBod JH22LlBEP0LNwEI/tyJhNLWC24ze7edbeALYcSOm1BW9vvlirjb5vE99aecfGW0hhx1k bf9W5U63VouX/CWakZftGgt03Ui7TYX+8tucy3l2LRIYP0WUNBkbA6tqsymXY08PaG9G QRTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=HY7aW8CR; spf=pass (google.com: domain of linux-kernel+bounces-19205-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19205-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id kh13-20020a170906f80d00b00a28fb24aae2si2802223ejb.922.2024.01.08.00.52.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 00:52:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19205-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=HY7aW8CR; spf=pass (google.com: domain of linux-kernel+bounces-19205-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19205-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 2C2E61F220DD for ; Mon, 8 Jan 2024 08:52:00 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 93677125C1; Mon, 8 Jan 2024 08:51:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="HY7aW8CR" X-Original-To: linux-kernel@vger.kernel.org Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64368C128; Mon, 8 Jan 2024 08:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E1E1CC00FC; Mon, 8 Jan 2024 09:51:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1704703880; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=hAu4/xuLsSrHwTANNA7s3QmXGy5YS+glepKpDYXmA5o=; b=HY7aW8CR8LLjsp2yGutQpI5YdALu3v4tLFR0MwdOMHuHjDH8FOSF+Smre+gSif4ce5tFF2 cKvrpleBMbOLr8ttZC4ENnKLeu9m0Ttk0sg+sR2Hal6MQKapuB5UsVDdq6KsnbON2DDvfj 6oVnhZfNQQsXZNR1gw8rroB1EH3L0pKH3PxX71fa+PiqCETV2Sbv4YFHxyHOSnBiuNrmCx G89WZLXtP7AohZNRKWW05MCObfPDG4Hk2L4ope57SswrD5aaKfRohklcbVKCkIOwpmzI2U sRdjZgyyEoBvPZT5peKj2DcgahLrOQdorsL9H0+z4MY/Cr9XapDvLA5kIx/kbQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v4 06/12] arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board Date: Mon, 8 Jan 2024 09:49:03 +0100 Message-ID: <20240108084945.75356-7-frieder@fris.de> In-Reply-To: <20240108084945.75356-1-frieder@fris.de> References: <20240108084945.75356-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787511618662861517 X-GMAIL-MSGID: 1787511618662861517 From: Frieder Schrempf Some signals have external pullup resistors on the board and don't need the internal ones to be enabled. Due to silicon errata ERR050080 let's disable the internal pull resistors whererever possible and prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index ee93db11c0d06..aab8e24216501 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -316,40 +316,40 @@ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; From patchwork Mon Jan 8 08:49:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 185848 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp899342dyq; Mon, 8 Jan 2024 00:52:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IG+a27W69B6y3Sj8fhlzRvsQO8j80iiKk/zJOcMXu6lukZnp3HoA3V/2jamB04JZeGRu+tr X-Received: by 2002:a05:6214:19ec:b0:66c:fe0f:7cdd with SMTP id q12-20020a05621419ec00b0066cfe0f7cddmr5735591qvc.14.1704703927393; Mon, 08 Jan 2024 00:52:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704703927; cv=none; d=google.com; s=arc-20160816; b=bZT3s6f50/5/Dm9XVcsKBZhnnQbe16RkJ+qywHXdd8DyR1c1S1DxbGyrPb4/ceKeFw +ah826ucERSZGVDB69UITSIB1bC//URHR9I098fnnDFki2MdtxGYLPxOBVZjOiN18sxA Tj58QSGSP+96YCFWK7mrNcLHfzmbnbxGaZHCiKJQTyYZbaTlG67R3qhs1qeLRp6TsycN yudMHUY2hMRamm6UOiLJp0wigGwgZCOI2sQgny20N0ob3MuMFdeJKsjTOmGxiak/Ig2M v3spUZMoCsAS8dLBxlR4GTjPhtESWttHvJOiu9hLurIIF8iNI3+HZtvBE1RgW4hkaVYr 5Ryw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=wTGxRgaKGKupnoXw4GHvrCi9OifBL1yEtA/OEf2ONgk=; fh=5WBVB9KggvEUZrfL2cFjcxt7hrbLV0CECJcyvKKi3zA=; b=TUoZbZt+3KF9UGHtoM3jP4aj8PsIHP7SPCUlA0B+LBP5ToM8jlzoLGvGgpJ0ni9IRz cXHogz7FGEkdq+zKPwjmGuojIDV5LpMLITU+Q7oCfaMpODOPvDSiyG+c/iweLuneeQyK gnlLYa+2Ahic2lxPGMWh/4NKypWHvDJa/IKFcXmFzmo5CF8AOfM1CBvsDjwp+FoQ9/nH Nh8frWfmkOr+gwp4KNUblwtrYTA38K5d6KydLdlnvs7ITjDXo/Rzf5UMcPr4eR5jBIn8 pUqheqfOXIKREkuy0BK0gSaboK68WkioiqFJEI7mnhUZKL1Rq8IXTVmuLoIWsLkoROJT 8xzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b="YxQKjH/w"; spf=pass (google.com: domain of linux-kernel+bounces-19206-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19206-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id g9-20020a0ce4c9000000b0067f0ab12cdasi7509586qvm.524.2024.01.08.00.52.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 00:52:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19206-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b="YxQKjH/w"; spf=pass (google.com: domain of linux-kernel+bounces-19206-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19206-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id DD9AE1C21623 for ; Mon, 8 Jan 2024 08:52:06 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3264C12B93; Mon, 8 Jan 2024 08:51:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="YxQKjH/w" X-Original-To: linux-kernel@vger.kernel.org Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9099BC139; Mon, 8 Jan 2024 08:51:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 60457C00FD; Mon, 8 Jan 2024 09:51:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1704703881; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=wTGxRgaKGKupnoXw4GHvrCi9OifBL1yEtA/OEf2ONgk=; b=YxQKjH/wpgwcdXsUkO/TcVLG4sxIwawChI6yB7ocQMoCdimv9qzCcFeWqF5ufrioOWmGJ4 YUlgjjPQowkegz5fWuPvJw8fJY8MUHEBW7jRZaJsPLNYN537i1dXi0nM2TjnSPhf+OcWjT dpC8SFT4qYwyHbgF/G9oOessHC1SQL6GNUTRfzA78i58/8T8/j+wDTu7D7l/4a84TVd30g 6Jy6uPGUQUMD/g0/u7lt2RRWGqRVjqpt54b21qejdW1EA4Hgcwuvm4mB0LAwH2iGhDidPz klcsHxYnc2y4WL1pVUYcskKhKHvMpB+Rk5SPdkAxkTUkzOZaW7tmmpbqoHoQAQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v4 07/12] arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module Date: Mon, 8 Jan 2024 09:49:04 +0100 Message-ID: <20240108084945.75356-8-frieder@fris.de> In-Reply-To: <20240108084945.75356-1-frieder@fris.de> References: <20240108084945.75356-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787511625768383169 X-GMAIL-MSGID: 1787511625768383169 From: Frieder Schrempf The level of the interrupt signal is active low instead. Fix this. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 3e7db968f7e64..60abcb636cedf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -210,7 +210,7 @@ rv3028: rtc@52 { reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; - interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; trickle-diode-disable; }; }; From patchwork Mon Jan 8 08:49:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 185860 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp905859dyq; Mon, 8 Jan 2024 01:10:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IE961MrXrWhbDilcNLJQPYzWZMejitd/t576T0pEX4U/Iq0KJRVKIArJR/CPEVE4scKTHth X-Received: by 2002:a17:902:d4cc:b0:1d5:36a9:10da with SMTP id o12-20020a170902d4cc00b001d536a910damr391685plg.57.1704705006237; Mon, 08 Jan 2024 01:10:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704705006; cv=none; d=google.com; s=arc-20160816; b=lU2BtCQfDNB4sO1u3Ggcqgpm2OJaHRCrGAGdZVExD3WKFXgn2dNRs8C/7qJfmecbHx sZjzKjf+dYrOHoUgoBlM5zuT9we9KyBEsNNQD2n1LOEwLkkjNhcbDNVdXkBZSEPxNaUg GN8JvapNn2Hc9jO1DC3d04rw9c3goHlo+0hmZfcoCnFpMBOX3IiAmQpgSKItZThjAvCl zJAh5V+VHXpxT02kYzzlZbxOKdxAI7GiA5RP3vnesEbQDwu/qvNlSALFQ6Wp/Ma13WB4 CwUvS//AcmFAtJKeWyer463Om6/dnMhd3Z2W4cjcWTSaZ0wetMr/cmj/Zp1Q8xJESdNr UHpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=LzCepDPihJFEKeRie8QIRkXeAXlAu8NPaswOAfzNp8c=; fh=ltYwvILgD5pj0Rly1blr/5KGxhpSp2Y+0x4fOITKRXI=; b=puD4gV/Saidx/i9q0Z+oBl49U9SvlBHFOWTDv6arQZwpEVtSL0CMO+e3iwqK0Dz5Pc NY6diWXX7v1tYYORbZXZLTa/h3wFN/H1Fia82898dC5LpM59hdIf+EXdzio4NRb40Qwy g8Wcz0GCa1cX9aYAzqfQSnq5NWdmXmRL8x+5xvLdQF/PoIIJBxhfD+ZzV8R18Y6ilCNy UISNr83M0F+RflRWpbAOGQJ57TFwN91CJRrk3dX24Gxgef12TxqIeGq2oIfZCBWiYFBl BF8l8EkAwArEMcEqvGJ2n1oJkZYv2eAwygyLCgJgkNVKaDoCapDCl3sVwSJUZcM0JJSq O3qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=HMYXzrTi; spf=pass (google.com: domain of linux-kernel+bounces-19211-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19211-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id i10-20020a17090332ca00b001d46f84575asi5837649plr.444.2024.01.08.01.10.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 01:10:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19211-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=HMYXzrTi; spf=pass (google.com: domain of linux-kernel+bounces-19211-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19211-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 542A4283799 for ; Mon, 8 Jan 2024 08:53:08 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 129D914A8D; Mon, 8 Jan 2024 08:51:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="HMYXzrTi" X-Original-To: linux-kernel@vger.kernel.org Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD0A614281; Mon, 8 Jan 2024 08:51:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DDA22C00CE; Mon, 8 Jan 2024 09:51:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1704703890; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=LzCepDPihJFEKeRie8QIRkXeAXlAu8NPaswOAfzNp8c=; b=HMYXzrTi0GpvKhJRRuA2q+ynQJOiMEop1uLwy9t+2vkFu4nn13EKLqO2xpUAKth9MrEfru Z70DbqorjtFu0QulGRfiJw/AdEbGr/pIc0RM9urq9HEU0ky0LEGbSyEltbnDtoL6nM+ZIi yYndKzwKFMv82iWKt49CLVfXsXjaBIxq+CvTXZ3OA2tREPJcoAoYCdBjy6weA/+WjFVTN0 KEmAeJfkwysboe59q5Adi/Zn4vKHL7yq1QFYaj4KxRov+XyMS50/buFCaMtW5ksuESy6aA Hd5jdx/+dr5bhGG6G6UkGwwFNEPJr6PqG998fflUYg4ey1H22Xj8nTTqw1ocWA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v4 12/12] arm64: dts: imx8mm-kontron: Refactor devicetree for OSM-S module and board Date: Mon, 8 Jan 2024 09:49:09 +0100 Message-ID: <20240108084945.75356-13-frieder@fris.de> In-Reply-To: <20240108084945.75356-1-frieder@fris.de> References: <20240108084945.75356-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787512756955884937 X-GMAIL-MSGID: 1787512756955884937 From: Frieder Schrempf The OSM spec defines dedicated functions for all pads of the SoM. Therefore we can assume that carrier board designs stick to these definitions and extend the SoM devicetree include with matching default nodes and pinmux settings. This way we can reduce the overhead and redundancy in the carrier board devicetrees while still sticking to the policy of separating board and module description. Even if the carrier board design deviates slightly from the spec it can define its own pinmux definitions and use them as necessary or even disable unused nodes from the SoM devicetree. Signed-off-by: Frieder Schrempf --- Changes for v3: * Address Shawn's review comments (thanks!) Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 269 +++------ .../dts/freescale/imx8mm-kontron-osm-s.dtsi | 552 +++++++++++++++++- 2 files changed, 616 insertions(+), 205 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 12f786a72fbd5..efadfdff00af1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -25,8 +25,6 @@ osc_can: clock-osc-can { leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; led1 { label = "led1"; @@ -52,24 +50,12 @@ pwm-beeper { reg_rst_eth2: regulator-rst-eth2 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth2>; gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name = "rst-usb-eth2"; }; - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_vbus>; - gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb1-vbus"; - }; - reg_vdd_5v: regulator-5v { compatible = "regulator-fixed"; regulator-always-on; @@ -80,9 +66,6 @@ reg_vdd_5v: regulator-5v { }; &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; can@0 { @@ -103,9 +86,6 @@ can@0 { }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; eeram@0 { @@ -117,7 +97,7 @@ eeram@0 { &fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; + pinctrl-0 = <&pinctrl_enet_rgmii>; phy-connection-type = "rgmii-id"; phy-handle = <ðphy>; status = "okay"; @@ -136,27 +116,59 @@ ethphy: ethernet-phy@0 { }; }; +/* + * Rename SoM signals according to board usage: + * GPIO_B_0 -> DIO1_OUT + * GPIO_B_1 -> DIO2_OUT + */ &gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", - "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT", + "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; }; -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>; - gpio-line-names = "", "", "dio4-in", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; +/* + * Rename SoM signals according to board usage: + * GPIO_B_2 -> DIO3_OUT + * GPIO_B_3 -> DIO4_OUT + */ +&gpio3 { + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT", + "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +/* + * Rename SoM signals according to board usage: + * GPIO_B_4 -> DIO1_IN + * GPIO_B_5 -> DIO2_IN + * GPIO_B_6 -> DIO3_IN + * GPIO_B_7 -> DIO4_IN + */ +&gpio4 { + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN", + "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; }; &i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; usb-hub@2c { @@ -169,27 +181,28 @@ usb-hub@2c { }; }; -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - &pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; +®_usb2_vbus { + status = "disabled"; +}; + +®_usdhc2_vcc { + status = "disabled"; +}; + +®_usdhc3_vcc { + status = "disabled"; +}; + &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; uart-has-rtscts; status = "okay"; }; &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; linux,rs485-enabled-at-boot-time; uart-has-rtscts; status = "okay"; @@ -197,8 +210,6 @@ &uart2 { &usbotg1 { dr_mode = "otg"; - disable-over-current; - vbus-supply = <®_usb1_vbus>; status = "okay"; }; @@ -209,6 +220,9 @@ &usbotg2 { #size-cells = <0>; status = "okay"; + /* VBUS is controlled by the hub */ + /delete-property/ vbus-supply; + usb1@1 { compatible = "usb424,2514"; reg = <1>; @@ -224,171 +238,20 @@ usbnet: ethernet@1 { }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_nvcc_sd>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { pinctrl_can: cangrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* PHY RST */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - >; - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_reg_usb1_vbus: regusb1vbusgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ >; }; - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + pinctrl_usb_hub: usbhubgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 6b9058fc53332..663ae52b48526 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Kontron Electronics GmbH */ +#include #include #include "imx8mm.dtsi" @@ -28,6 +29,73 @@ memory@40000000 { chosen { stdout-path = &uart3; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB1"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_vbus>; + enable-active-high; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB2"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_A"; + }; + + reg_usdhc3_vcc: regulator-usdhc3-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; + enable-active-high; + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_B"; + }; }; &A53_0 { @@ -96,6 +164,79 @@ partition@1f0000 { }; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0", + "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "SDIO_A_WP"; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2", + "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6", + "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&gpio5 { + gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2", + "PWM_1", "PWM_0", "", "", + "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)", + "SPI_A_SCK", "SPI_A_CS0#", "", "", + "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA", + "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX", + "UART_C_RX", "UART_C_TX"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -222,12 +363,69 @@ rv3028: rtc@52 { }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + vbus-supply = <®_usb1_vbus>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + vbus-supply = <®_usb2_vbus>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -240,6 +438,26 @@ &usdhc1 { status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + vmmc-supply = <®_usdhc3_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -248,6 +466,12 @@ &wdog1 { }; &iomuxc { + pinctrl_csi_mck: csimckgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */ + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 @@ -257,6 +481,106 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */ + >; + }; + + pinctrl_ecspi2_gpio: ecspi2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_enet_rmii: enetrmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 @@ -264,22 +588,149 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */ + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */ + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */ + >; + }; + + pinctrl_reg_usb2_vbus: regusb2vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */ + >; + }; + pinctrl_rtc: rtcgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */ + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */ + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */ + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */ + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */ + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */ + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */ + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */ + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */ >; }; @@ -334,6 +785,103 @@ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6