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[61.216.141.121]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a65c200b00288628acf6dsm5376875pjs.14.2024.01.07.22.15.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 07 Jan 2024 22:15:56 -0800 (PST) Message-ID: <05750a1e-8f51-4109-9342-3b0b9670cbd2@gmail.com> Date: Mon, 8 Jan 2024 14:15:54 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches , Kyrylo Tkachov , Richard Earnshaw Cc: "Jason.Wu@anshingtek.com.tw" From: Chung-Ju Wu Subject: [PATCH 1/2] arm: Add cortex-m52 core X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787501855094901112 X-GMAIL-MSGID: 1787501855094901112 Hi, Recently, Arm announced the Cortex-M52, delivering increased performance in DSP and ML along with a range of other features and benefits. For the completeness of Arm ecosystem, we hope that cortex-m52 support could be available in gcc-14. Attached is the patch to support cortex-m52 cpu with MVE and PACBTI enabled in GCC. Bootstrapped and tested on arm-none-eabi. Is it OK for trunk? Regards, jasonwucj From d0856b516c5d270a852f3edd9df5dadccde5b94e Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Wed, 6 Dec 2023 15:49:58 +0800 Subject: [PATCH 1/2] arm: Add support for Arm Cortex-M52 CPU. This patch adds the -mcpu support for the Arm Cortex-M52 CPU which is an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mcpu=cortex-m52 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp. The cde feature is supported by specifying +cdecpN (e.g. -mcpu=cortex-m52+cdecp), where N is the coprocessor number 0 to 7. Also following options are provided to disable default features. +nomve.fp (disables MVE Floating point) +nomve (disables MVE Integer and MVE Floating point) +nodsp (disables dsp, MVE Integer and MVE Floating point) +nopacbti (disables pacbti) +nofp (disables floating point and MVE floating point) Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in (cortex-m52): New cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. --- gcc/config/arm/arm-cpus.in | 21 +++++++++++++++++++++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 6 +++--- 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 6fa7e315ef0..451b15fe9f9 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1641,6 +1641,27 @@ begin cpu cortex-m35p costs v7m end cpu cortex-m35p +begin cpu cortex-m52 + cname cortexm52 + tune flags LDSCHED + architecture armv8.1-m.main+pacbti+mve.fp+fp.dp + option nopacbti remove pacbti + option nomve.fp remove mve_float + option nomve remove mve mve_float + option nofp remove ALL_FP mve_float + option nodsp remove MVE mve_float + option cdecp0 add cdecp0 + option cdecp1 add cdecp1 + option cdecp2 add cdecp2 + option cdecp3 add cdecp3 + option cdecp4 add cdecp4 + option cdecp5 add cdecp5 + option cdecp6 add cdecp6 + option cdecp7 add cdecp7 + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu cortex-m52 + begin cpu cortex-m55 cname cortexm55 tune flags LDSCHED diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 9d6ae875ede..d3eb9a97739 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) EnumValue Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) +EnumValue +Enum(processor_type) String(cortex-m52) Value( TARGET_CPU_cortexm52) + EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 7318f03b97e..6a631d82966 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,7 +49,7 @@ cortexa710,cortexx1,cortexx1c, neoversen1,cortexa75cortexa55,cortexa76cortexa55, neoversev1,neoversen2,cortexm23, - cortexm33,cortexm35p,cortexm55, - starmc1,cortexm85,cortexr52, - cortexr52plus" + cortexm33,cortexm35p,cortexm52, + cortexm55,starmc1,cortexm85, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) From patchwork Mon Jan 8 06:16:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Ju Wu X-Patchwork-Id: 185816 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp854136dyq; Sun, 7 Jan 2024 22:17:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IE5DHQMMzygsuFgCbCmm9Qb5Ahlz3nPfnosBzr3K24Feja/nLVDRgZPD+dMboG+Df3O45ty X-Received: by 2002:a05:620a:4452:b0:783:2495:12d9 with SMTP id w18-20020a05620a445200b00783249512d9mr855272qkp.104.1704694665835; Sun, 07 Jan 2024 22:17:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704694665; cv=pass; d=google.com; s=arc-20160816; b=v77dkjxix8V4roVFpcZfK9R6su2H5h2mTIo/vCEm3TtoGdVVoGKBucbIPygZUxc3N3 WrOT4O5xMpzc7j7ea2/4fSYhXGeL5AmS6wYWXP7sc8u5RRFfrxHLoKqKCqKfV2GQ5W7W X338GB3wgc2YhcB0NsUSTu7M1IEFn2v7kbUmPNwuJZbXeK3uPzo/cRWju7GI51us/I/I dXeY1P7oSwEFDt5bvsF6deaunX0P+UsWFm0RSG9m29pdgjNDAJXJ49QbwNCwFN/Od+rg W9xFPJDdDjbnpGGn2m6xpdDfRSMeCYqY9BPDIfP/G6LwuH84h1rrthbjQaX++wszDW/z lUEg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:from:cc:to :content-language:user-agent:mime-version:date:message-id :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=JEk1YzgaxsL/pBgQwyNQ7zzLgB2BUGclRogyyEL1tFk=; fh=3rcYLoxHvZNRgmHc3E0fvza0fQgcSXSAerEc8vpXcEc=; b=Dm//SpHJSifS9h6F0L3at+77se3KhMm33Mjz4w5xSXqVa3w4rXuCpCwUsr7v7/WxEY 7TI1RabYIC6AYdBcar9T0kTLOo0moaow1cr/7toD9uV0h0/3s2Usa75S1RiHNTo+qI5V W7uvFRGxtiESNSQhq5EMUX6Gr15YY1FHLxoaIg/xOle0OySsC2JLaUPFm7/rUpKrVi0d LG3WVj0L0V5vH03mte2jqHYFhvYNO6dTzfW5/d9n+ECirOXpxCYTWI3X20e23EkdpnBf RHfRXKlLDovjWyw5w8f1KQ7dXSXGlBMmOgVBsx91ihAP9Qna+ATiRFU0HLYVdCm2pkcN uU+w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=LHeROw+H; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from server2.sourceware.org (server2.sourceware.org. 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[61.216.141.121]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a65c200b00288628acf6dsm5376875pjs.14.2024.01.07.22.16.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 07 Jan 2024 22:16:38 -0800 (PST) Message-ID: <0c5c7a33-93c9-46ad-85f3-b6f4bb3d5ddd@gmail.com> Date: Mon, 8 Jan 2024 14:16:37 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches , Kyrylo Tkachov , Richard Earnshaw Cc: "Jason.Wu@anshingtek.com.tw" From: Chung-Ju Wu Subject: [PATCH 2/2] arm: Add cortex-m52 doc X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787501914326549178 X-GMAIL-MSGID: 1787501914326549178 Hi, This is the patch to add cortex-m52 in the Arm-related options sections of the gcc invoke.texi documentation. Is it OK for trunk? Regards, jasonwucj From b7ce3d499d4bf087ec54a5f834876c9108d46c3d Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 7 Dec 2023 11:26:25 +0800 Subject: [PATCH 2/2] arm: Add Arm Cortex-M52 CPU documentation. Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * doc/invoke.texi: Update docs. --- gcc/doc/invoke.texi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d71583853f0..bdbe0074cb4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23094,7 +23094,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus}, @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3}, @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33}, -@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1}, +@samp{cortex-m35p}, @samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1}, @samp{cortex-x1c}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, @@ -23160,34 +23160,34 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}, -@samp{cortex-m55} and @samp{cortex-m85}. Also disable the M-Profile Vector -Extension (MVE) integer and single precision floating-point instructions on -@samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. +Also disable the M-Profile Vector Extension (MVE) integer and +single precision floating-point instructions on +@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. @item +nopacbti Disable the Pointer Authentication and Branch Target Identification Extension -on @samp{cortex-m85}. +on @samp{cortex-m52} and @samp{cortex-m85}. @item +nomve Disable the M-Profile Vector Extension (MVE) integer and single precision -floating-point instructions on @samp{cortex-m55} and @samp{cortex-m85}. +floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. @item +nomve.fp Disable the M-Profile Vector Extension (MVE) single precision floating-point -instructions on @samp{cortex-m55} and @samp{cortex-m85}. +instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. @item +cdecp0, +cdecp1, ... , +cdecp7 Enable the Custom Datapath Extension (CDE) on selected coprocessors according -to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}. +to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52} and @samp{cortex-m55}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p} @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}, -@samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, @@ -23530,9 +23530,9 @@ Development Tools Engineering Specification", which can be found on Mitigate against a potential security issue with the @code{VLLDM} instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option @option{-mcpu=} is used with -@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55}, @code{cortex-m85} -or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} can be used -to disable the mitigation. +@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m52}, @code{cortex-m55}, +@code{cortex-m85} or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} +can be used to disable the mitigation. @opindex mstack-protector-guard @opindex mstack-protector-guard-offset