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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h3-20020a05622a170300b004297ea60b58si1552781qtk.270.2024.01.06.00.55.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 00:55:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5C15F3858403 for ; Sat, 6 Jan 2024 08:55:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 3823B3858D20 for ; Sat, 6 Jan 2024 08:54:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3823B3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3823B3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531271; cv=none; b=Bibo47SJuX6a5g8/w3KCS+8xC4I0XsnGHiiEHt66BOdvz1UoQZ9zTr3xlW0yzSQNNNfv7eL1zOl8WpuDHUY0hZwUnq5uEoXcqz+bKGXMwhds8H6kNUbowlsCk5fzzVQmDBKjEARcOokkXw6wCn9a8nfY74fDZYnBvh0R2bWXKZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531271; c=relaxed/simple; bh=gWG32fh9ttsNyVOAFJ6Y2MX2kDyebNULfVTBoYPmAUE=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Te6wN/QfXUPMYWqiWKBXbSNPx26Svi/Fv9uoP96Uc1zd5MEWYasHH+q9BKQoxK3lz3njehzYy+BhGxEh5V3XJQN5yXUMgc8pOhXGojZCpsb1kfX0BWzWSifmsR7Sw0VBvUls7phQfkaX2IGF6zH9inM0s6OgfIn3BmSTMcymbRY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rM2Rk-0004CK-LZ for gcc-patches@gcc.gnu.org; Sat, 06 Jan 2024 03:54:28 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxXbs5FZlloZgCAA--.851S3; Sat, 06 Jan 2024 16:54:17 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxK9w2FZllcWgEAA--.11725S2; Sat, 06 Jan 2024 16:54:15 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations. Date: Sat, 6 Jan 2024 16:54:07 +0800 Message-Id: <20240106085409.25985-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxK9w2FZllcWgEAA--.11725S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxuFyDtryDuw1DAr15GryxtFc_yoW3CFyUpr WkC3W8GrWUXrZ2g34vkFW2qa15Kr17AFWjvF9Ygr9IkryUW34UJ340kryaqayUCw4Fqr1U Xa1xtw1Uu3y5K3gCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAF wI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7XTmDUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787330646032185859 X-GMAIL-MSGID: 1787330646032185859 There are two mode iterators defined in the loongarch.md: (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) and (define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) Replace the mode in the bit arithmetic from GPR to X. Since the bitwise operation instruction does not distinguish between 64-bit, 32-bit, etc., it is necessary to perform symbolic expansion if the bitwise operation is less than 64 bits. The original definition would have generated a lot of redundant symbolic extension instructions. This problem is optimized with reference to the implementation of RISCV. Add this patch spec2017 500.perlbench performance improvement by 1.8% gcc/ChangeLog: * config/loongarch/loongarch.md (one_cmpl2): Replace GPR with X. (*nor3): Likewise. (nor3): Likewise. (*negsi2_extended): New template. (*si3_internal): Likewise. (*one_cmplsi2_internal): Likewise. (*norsi3_internal): Likewise. (*nsi_internal): Likewise. (bytepick_w__extend): Modify this template according to the modified bit operation to make the optimization work. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend-bitwise.c: New test. --- gcc/config/loongarch/loongarch.md | 93 ++++++++++++++----- .../loongarch/sign-extend-bitwise.c | 21 +++++ 2 files changed, 90 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d1f5b94f5d6..436b9a93235 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -736,7 +736,7 @@ (define_insn "sub3" (define_insn "sub3" [(set (match_operand:GPR 0 "register_operand" "=r") - (minus:GPR (match_operand:GPR 1 "register_operand" "rJ") + (minus:GPR (match_operand:GPR 1 "register_operand" "r") (match_operand:GPR 2 "register_operand" "r")))] "" "sub.\t%0,%z1,%2" @@ -1412,13 +1412,13 @@ (define_insn "neg2" [(set_attr "alu_type" "sub") (set_attr "mode" "")]) -(define_insn "one_cmpl2" - [(set (match_operand:GPR 0 "register_operand" "=r") - (not:GPR (match_operand:GPR 1 "register_operand" "r")))] - "" - "nor\t%0,%.,%1" - [(set_attr "alu_type" "not") - (set_attr "mode" "")]) +(define_insn "*negsi2_extended" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] + "TARGET_64BIT" + "sub.w\t%0,%.,%1" + [(set_attr "alu_type" "sub") + (set_attr "mode" "SI")]) (define_insn "neg2" [(set (match_operand:ANYF 0 "register_operand" "=f") @@ -1438,14 +1438,39 @@ (define_insn "neg2" ;; (define_insn "3" - [(set (match_operand:GPR 0 "register_operand" "=r,r") - (any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r") - (match_operand:GPR 2 "uns_arith_operand" "r,K")))] + [(set (match_operand:X 0 "register_operand" "=r,r") + (any_bitwise:X (match_operand:X 1 "register_operand" "%r,r") + (match_operand:X 2 "uns_arith_operand" "r,K")))] "" "%i2\t%0,%1,%2" [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "*si3_internal" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "uns_arith_operand" " r,K")))] + "TARGET_64BIT" + "%i2\t%0,%1,%2" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) + +(define_insn "one_cmpl2" + [(set (match_operand:X 0 "register_operand" "=r") + (not:X (match_operand:X 1 "register_operand" "r")))] + "" + "nor\t%0,%.,%1" + [(set_attr "alu_type" "not") + (set_attr "mode" "")]) + +(define_insn "*one_cmplsi2_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (not:SI (match_operand:SI 1 "register_operand" " r")))] + "TARGET_64BIT" + "nor\t%0,%.,%1" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) + (define_insn "and3_extended" [(set (match_operand:GPR 0 "register_operand" "=r") (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "r") @@ -1561,25 +1586,43 @@ (define_insn "*iorhi3" [(set_attr "type" "logical") (set_attr "mode" "HI")]) -(define_insn "*nor3" - [(set (match_operand:GPR 0 "register_operand" "=r") - (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "%r")) - (not:GPR (match_operand:GPR 2 "register_operand" "r"))))] +(define_insn "nor3" + [(set (match_operand:X 0 "register_operand" "=r") + (and:X (not:X (match_operand:X 1 "register_operand" "%r")) + (not:X (match_operand:X 2 "register_operand" "r"))))] "" "nor\t%0,%1,%2" [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "*norsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (and:SI (not:SI (match_operand:SI 1 "register_operand" "%r")) + (not:SI (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_64BIT" + "nor\t%0,%1,%2" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) + (define_insn "n" - [(set (match_operand:GPR 0 "register_operand" "=r") - (neg_bitwise:GPR - (not:GPR (match_operand:GPR 1 "register_operand" "r")) - (match_operand:GPR 2 "register_operand" "r")))] + [(set (match_operand:X 0 "register_operand" "=r") + (neg_bitwise:X + (not:X (match_operand:X 1 "register_operand" "r")) + (match_operand:X 2 "register_operand" "r")))] "" "n\t%0,%2,%1" [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "*nsi_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg_bitwise:SI + (not:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_64BIT" + "n\t%0,%2,%1" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) ;; ;; .................... @@ -3167,7 +3210,6 @@ (define_expand "condjump" (label_ref (match_operand 1)) (pc)))]) - ;; ;; .................... @@ -3967,10 +4009,13 @@ (define_insn "bytepick_w_" (define_insn "bytepick_w__extend" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI - (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r") - (const_int )) - (ashift (match_operand:SI 2 "register_operand" "r") - (const_int bytepick_w_ashift_amount)))))] + (subreg:SI + (ior:DI (subreg:DI (lshiftrt + (match_operand:SI 1 "register_operand" "r") + (const_int )) 0) + (subreg:DI (ashift + (match_operand:SI 2 "register_operand" "r") + (const_int bytepick_w_ashift_amount)) 0)) 0)))] "TARGET_64BIT" "bytepick.w\t%0,%1,%2," [(set_attr "mode" "SI")]) diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c new file mode 100644 index 00000000000..5753ef69db2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -O2" } */ +/* { dg-final { scan-assembler-not "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" } } */ + +struct pmop +{ + unsigned int op_pmflags; + unsigned int op_pmpermflags; +}; +unsigned int PL_hints; + +struct pmop *pmop; +void +Perl_newPMOP (int type, int flags) +{ + if (PL_hints & 0x00100000) + pmop->op_pmpermflags |= 0x0001; + if (PL_hints & 0x00000004) + pmop->op_pmpermflags |= 0x0800; + pmop->op_pmflags = pmop->op_pmpermflags; +} From patchwork Sat Jan 6 08:54:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenglulu X-Patchwork-Id: 185620 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp14794dyq; Sat, 6 Jan 2024 00:55:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IGibGmceZ1KOOzZsn3ySswHoT2C+LeezKV5ZXFgVkvUf9TXEgfE/S/td285/ETUxpiQuwXY X-Received: by 2002:ac8:7f8a:0:b0:428:3108:154d with SMTP id z10-20020ac87f8a000000b004283108154dmr969941qtj.123.1704531331416; Sat, 06 Jan 2024 00:55:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704531331; cv=pass; d=google.com; s=arc-20160816; b=V7yGwQTBf5zjIYFyuqI6EdBPfRej2jnm9Ubf9fLAVNpWrA+YlxVuRSu7SlkJXdwPzp I00tSlHNpE8mBjDfTn3RFfzFYbPipKwigHkmceKuJtyw0QcOqEHZy1r/kawFtLZzWD+z EDoKUIXjnmIb5F6T4EAqJDsO+99bTFook8R0z3CsEVAk9R8iHw+ALNqiCbg/Q7kEbRsQ R1uM/YJrF1Jfx8y4BezGhXw8XaYxr6KaGwIZVlX99WEslJVUM0CduY7xpGJ4CZBzdE84 TXebGOJhZQfwgZACDuRWzsj7ukrX3rebIX1ZE712hEcLJwulZPikqewLtlganHuvxzeX UcqA== ARC-Message-Signature: i=2; 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[8.43.85.97]) by mx.google.com with ESMTPS id j6-20020ac85c46000000b0042836b8f03bsi3589253qtj.374.2024.01.06.00.55.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 00:55:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1E1463858D1E for ; Sat, 6 Jan 2024 08:55:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 830FF3858D1E for ; Sat, 6 Jan 2024 08:54:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 830FF3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 830FF3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531270; cv=none; b=PHZtshOtEynJVTGJPx6tBnd32+KCBzPuPxv9jPVAm5Ze9kSsohjCyekjh2yTrSzxoUhIYLkZ3Ty90IhLSnsFY0I+XaE8Q17JRnTZa5cErK6fxqRomkmLLR5g3QLiexoE04KbM9M+1MeFHjwgkI445UVBk5TRHwTcXFQiCrBHGlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531270; c=relaxed/simple; bh=PvhrQaWJogbbmojSSr0+gQ7/trP0sSDB7dHoUwwl3KA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=S8zeRwxsGUY25Cn0lYMcWrsQoOki4kNr+roT7xkGtzDl09iF04RAoMVmeCgO0ZNTI0NDFn0ECJYMgVYJc4C2cVBJ2tznHxYxIxlTA/L7T+mFZnnqHQvoxorEtn8OV3rbF+JTJQENEu6vtlNUbcV4ISDKy7X4OtTVIGQOWiolntE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Axzeg_FZllpJgCAA--.824S3; Sat, 06 Jan 2024 16:54:23 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxK9w2FZllcWgEAA--.11725S3; Sat, 06 Jan 2024 16:54:20 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, liwei Subject: [PATCH 2/3] LoongArch: Redundant sign extension elimination optimization. Date: Sat, 6 Jan 2024 16:54:08 +0800 Message-Id: <20240106085409.25985-2-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240106085409.25985-1-chenglulu@loongson.cn> References: <20240106085409.25985-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxK9w2FZllcWgEAA--.11725S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3XryDtr1rZFWkuw17Cr1UXFc_yoW3GFyxpr ZrCw12gr48Jwn3K340ka4UJr45Krn7JrWavF93u3srCryxX3srXa1Fyr9IqFy5Xa1Fqry5 XFs3Z3WUWa17K3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAF wI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7tx6UUUUU X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787330645158091909 X-GMAIL-MSGID: 1787330645158091909 From: liwei We found that the current combine optimization pass in gcc cannot handle the following redundant sign extension situations: (insn 77 76 78 5 (set (reg:SI 143) (plus:SI (subreg/s/u:SI (reg/v:DI 104 [ len ]) 0) (const_int 1 [0x1]))) {addsi3} (expr_list:REG_DEAD (reg/v:DI 104 [ len ]) (nil))) (insn 78 77 82 5 (set (reg/v:DI 104 [ len ]) (sign_extend:DI (reg:SI 143))) {extendsidi2} (nil)) Because reg:SI 143 is not died or set in insn 78, no replacement merge will be performed for the insn sequence. We adjusted the add template to eliminate redundant sign extensions during the expand pass. gcc/ChangeLog: * config/loongarch/loongarch.md (add3): Removed. (*addsi3): New. (addsi3): New. (adddi3): New. (*addsi3_extended): Removed. (addsi3_extended): New. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend.c: Moved to... * gcc.target/loongarch/sign-extend-1.c: ...here. * gcc.target/loongarch/sign-extend-2.c: New test. --- gcc/config/loongarch/loongarch.md | 93 ++++++++++++++++--- .../{sign-extend.c => sign-extend-1.c} | 0 .../gcc.target/loongarch/sign-extend-2.c | 59 ++++++++++++ 3 files changed, 137 insertions(+), 15 deletions(-) rename gcc/testsuite/gcc.target/loongarch/{sign-extend.c => sign-extend-1.c} (100%) create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-2.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 436b9a93235..17ec401f535 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -657,15 +657,15 @@ (define_insn "add3" [(set_attr "type" "fadd") (set_attr "mode" "")]) -(define_insn_and_split "add3" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r,r") - (plus:GPR (match_operand:GPR 1 "register_operand" "r,r,r,r,r,r,r") - (match_operand:GPR 2 "plus__operand" +(define_insn_and_split "*addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") + (plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r,r,r") + (match_operand:SI 2 "plus_si_operand" "r,I,La,Lb,Lc,Ld,Le")))] "" "@ - add.\t%0,%1,%2 - addi.\t%0,%1,%2 + add.w\t%0,%1,%2 + addi.w\t%0,%1,%2 # * operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \ return \"addu16i.d\t%0,%1,%2\"; @@ -674,25 +674,88 @@ (define_insn_and_split "add3" #" "CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \ && !ADDU16I_OPERAND (INTVAL (operands[2]))" - [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) - (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] + [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] { - loongarch_split_plus_constant (&operands[2], mode); + loongarch_split_plus_constant (&operands[2], SImode); } [(set_attr "alu_type" "add") - (set_attr "mode" "") + (set_attr "mode" "SI") (set_attr "insn_count" "1,1,2,1,2,2,2") (set (attr "enabled") (cond - [(match_test "mode != DImode && which_alternative == 4") + [(match_test "which_alternative == 4") (const_string "no") - (match_test "mode != DImode && which_alternative == 5") - (const_string "no") - (match_test "mode != SImode && which_alternative == 6") + (match_test "which_alternative == 5") + (const_string "no")] + (const_string "yes")))]) + +(define_expand "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") + (plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r") + (match_operand:SI 2 "plus_si_operand" "r,I,La,Le,Lb")))] + "" +{ + if (TARGET_64BIT) + { + if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) + && ADDU16I_OPERAND (INTVAL (operands[2]))) + { + rtx t1 = gen_reg_rtx (DImode); + rtx t2 = gen_reg_rtx (DImode); + rtx t3 = gen_reg_rtx (DImode); + emit_insn (gen_extend_insn (t1, operands[1], DImode, SImode, 0)); + t2 = operands[2]; + emit_insn (gen_adddi3 (t3, t1, t2)); + t3 = gen_lowpart (SImode, t3); + emit_move_insn (operands[0], t3); + DONE; + } + else + { + rtx t = gen_reg_rtx (DImode); + emit_insn (gen_addsi3_extended (t, operands[1], operands[2])); + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (operands[0], t); + DONE; + } + } +}) + +(define_insn_and_split "adddi3" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r") + (plus:DI (match_operand:DI 1 "register_operand" "r,r,r,r,r,r,r") + (match_operand:DI 2 "plus_di_operand" + "r,I,La,Lb,Lc,Ld,Le")))] + "" + "@ + add.d\t%0,%1,%2 + addi.d\t%0,%1,%2 + # + * operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \ + return \"addu16i.d\t%0,%1,%2\"; + # + # + #" + "CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \ + && !ADDU16I_OPERAND (INTVAL (operands[2]))" + [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] + { + loongarch_split_plus_constant (&operands[2], DImode); + } + [(set_attr "alu_type" "add") + (set_attr "mode" "DI") + (set_attr "insn_count" "1,1,2,1,2,2,2") + (set (attr "enabled") + (cond + [(match_test "which_alternative == 6") (const_string "no")] (const_string "yes")))]) -(define_insn_and_split "*addsi3_extended" +(define_insn_and_split "addsi3_extended" [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r") diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-1.c similarity index 100% rename from gcc/testsuite/gcc.target/loongarch/sign-extend.c rename to gcc/testsuite/gcc.target/loongarch/sign-extend-1.c diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c new file mode 100644 index 00000000000..a45dde4f73f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -O2" } */ +/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */ + +#include +#define my_min(x, y) ((x) < (y) ? (x) : (y)) + +void +bt_skip_func (const uint32_t len_limit, const uint32_t pos, + const uint8_t *const cur, uint32_t cur_match, + uint32_t *const son, const uint32_t cyclic_pos, + const uint32_t cyclic_size) +{ + uint32_t *ptr0 = son + (cyclic_pos << 1) + 1; + uint32_t *ptr1 = son + (cyclic_pos << 1); + + uint32_t len0 = 0; + uint32_t len1 = 0; + + while (1) + { + const uint32_t delta = pos - cur_match; + uint32_t *pair + = son + + ((cyclic_pos - delta + (delta > cyclic_pos ? cyclic_size : 0)) + << 1); + const uint8_t *pb = cur - delta; + uint32_t len = my_min (len0, len1); + + if (pb[len] == cur[len]) + { + while (++len != len_limit) + if (pb[len] != cur[len]) + break; + + if (len == len_limit) + { + *ptr1 = pair[0]; + *ptr0 = pair[1]; + return; + } + } + + if (pb[len] < cur[len]) + { + *ptr1 = cur_match; + ptr1 = pair + 1; + cur_match = *ptr1; + len1 = len; + } + else + { + *ptr0 = cur_match; + ptr0 = pair; + cur_match = *ptr0; + len0 = len; + } + } +} From patchwork Sat Jan 6 08:54:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenglulu X-Patchwork-Id: 185622 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp14813dyq; Sat, 6 Jan 2024 00:55:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IFAADHTXBYaDuov977NvuQjx5OEQG32MfitvUTt77oKwIwRjwVJhBbJgQsS1eEV0Zyyau45 X-Received: by 2002:a05:620a:10b4:b0:781:15ef:69d7 with SMTP id h20-20020a05620a10b400b0078115ef69d7mr801329qkk.74.1704531334244; Sat, 06 Jan 2024 00:55:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704531334; cv=pass; d=google.com; s=arc-20160816; b=h/RRuIn28noITt3EG9D+sxse0tlBstKqwymb3t0WuISwuADQ0oXp0nCUXuo0K5JEz8 9BQQ105gM4Rh15lk2isvped3xBuNvD6UCngJLlYoFCnjkpmrS5s3ztoIqh6K8seQV7tq NeXOUkXZA7czKCNiaoSbUUNENSg2pEZtTAsRiaQvtZmM2yorC/pFXRqPr4FZHKsvavJj 7IJq3S/ETKrCyCG4FdwILgkQgvv/sT+MnzmcrZ8OmbvfYo/EAPNYrBTKv2Hwdja/mFLJ BnFjkH2YGJlljnBswxwTpnHNBr/PXOaSpouq/dX34lfNan+qSS21NhQl8DHokrinRtUL fDqA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=Q7aWuO3Y2b3K3PnacGruPV9lQLbKVdyInDViyVwAaOU=; fh=VnTXG5Jo7DuQ1l+4wGnQIXMF5AJakZMe8j3+f/oPO4o=; b=SrxHrCahfWIhEBC7F3zlzX40+4VK8zg/oYdrZ+rlDrPaGg0mqmSf02LA/QTpOm9zff FbjqAYJidsFs+r2EdEWMJ1Z0/D27YDqkBHA1Aa69jYaIC613O3nfi0i05Vvm9KW22lIL kFZx2Uf7J9tcmnHuMXdA1aPDTFN0CoI1bawPAvazeTgjlW/ZXuZ5gkXy4LeReOGqAnUV uQcHzE5acpku3up6ql3m7pJRz8QNNNX30EnTO0SFACd9m80tOWvt6Sx95XC4pJ2uN3eB 0z0coDhknEPRDPebqdN7vAP/xSdLynP9l9qdQ5ZoFhxGZTif/ULQCWK5eddqzmc6mPYs h0KQ== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h3-20020a37c443000000b00781ebb79d6bsi3332031qkm.169.2024.01.06.00.55.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 00:55:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E5879385829D for ; Sat, 6 Jan 2024 08:55:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id B30803858D32 for ; Sat, 6 Jan 2024 08:54:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B30803858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B30803858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531277; cv=none; b=MP2iCn5063WqOLCjPos7BoXuGcWTOL6SedVAelLrLENeItV5aqtxhWDStaS/WxEPXRQ5LAyHjDlWK1do40zl+YUSfjDk9lpagrGm8bqrfw2Anvx5vctlt2MxnZAk5R6w8OiyMPs9kHm5Mg+/bFMmrnlYrIFvepsepqic/geYkQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531277; c=relaxed/simple; bh=w5JZRkB5Rp6J1PdiIZo6bZ0SGuL1WReQYoYbMmYktY0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Cj0R8ya4T+uuNArkhrbxXHwQ2z4jTx8MvjT94ySdg/9YACZ8b63CjyYZ2rcEkD2pFfDiXkwwhtg333H3uLLTvPPEaNoFZXD6PPIvk87AnmAd7RpwlegbXnBfKrBpmoSdfEUaLVBB1ab7uUQwDMFmGyEn6jqtS0KIffwFqVyWj7E= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rM2Ro-0004CX-Af for gcc-patches@gcc.gnu.org; Sat, 06 Jan 2024 03:54:30 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxWepBFZllppgCAA--.861S3; Sat, 06 Jan 2024 16:54:25 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxK9w2FZllcWgEAA--.11725S4; Sat, 06 Jan 2024 16:54:24 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, liwei Subject: [PATCH 3/3] LoongArch: Redundant sign extension elimination optimization 2. Date: Sat, 6 Jan 2024 16:54:09 +0800 Message-Id: <20240106085409.25985-3-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240106085409.25985-1-chenglulu@loongson.cn> References: <20240106085409.25985-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxK9w2FZllcWgEAA--.11725S4 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW7Cw15Zr48Zr13Ary8Xr4xuFX_yoW8AFy7p3 9ruwnrtr48GF97JF1vq34rGr13GrnrG39Iv3ZxJryIkw47JryjvF1rtFZIqF45tayFqrWS qr1ru3W5X3WjgwbCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUv2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAF wI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI1I0E14v26r1Y6r17MI8I3I0E5I8C rVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtw CIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x02 67AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr 0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8QJ 57UUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787330648406658841 X-GMAIL-MSGID: 1787330648406658841 From: liwei Eliminate the redundant sign extension that exists after the conditional move when the target register is SImode. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Adjust. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend-2.c: Adjust. --- gcc/config/loongarch/loongarch.cc | 2 ++ gcc/testsuite/gcc.target/loongarch/sign-extend-2.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index ec376a7228a..4b757b30b64 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -5371,6 +5371,8 @@ loongarch_expand_conditional_move (rtx *operands) rtx temp3 = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (temp3, gen_rtx_IOR (mode, temp, temp2))); temp3 = gen_lowpart (GET_MODE (operands[0]), temp3); + SUBREG_PROMOTED_VAR_P (temp3) = 1; + SUBREG_PROMOTED_SET (temp3, SRP_SIGNED); loongarch_emit_move (operands[0], temp3); } else diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c index a45dde4f73f..428535cb8e3 100644 --- a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mabi=lp64d -O2" } */ -/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */ +/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 0 } } */ #include #define my_min(x, y) ((x) < (y) ? (x) : (y))