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[8.43.85.97]) by mx.google.com with ESMTPS id e23-20020a0cb457000000b0067a360ada6esi926248qvf.255.2024.01.04.19.46.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 19:46:15 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D6576385700F for ; Fri, 5 Jan 2024 03:46:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id B18243858D32 for ; Fri, 5 Jan 2024 03:44:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B18243858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B18243858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426256; cv=none; b=rrDdpTjtLycbwckL9qDByu7Z3KJtONSZbBuq7sxjQV2mYtKLs1PbQpeus4li4M3DqaX2gopHfaRgS1gr4cW5GxzrsgP+10TKSIqkCgeGW5oDh8E9cvMDYN/8sEZ8WoOkl7hvCncO3p1eHnlYPP37ijwcYL4WURC4PTJnV9NOyEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426256; c=relaxed/simple; bh=JU3lfga7g48ZFCjk06Krin97pQy8F0eMaX74Xrivvu8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=It3Mupe9zA3O8pLBBC5zcpEKXoyze8Drfuvo2UMDCsgvT/CAKCJQRzleylOrFqqL/ijoBK9DkFDeR8mo3tyzbumt8H6W0tOnKtnaIivNEfYILHIXh54OtDq6JHf6fIHMMiqLDJKmAEBChE8JJ2aCfEcSEAy0KSzDBx4rURKH1zQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rLb7x-0003Nw-1y for gcc-patches@gcc.gnu.org; Thu, 04 Jan 2024 22:44:12 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8Bx3+sDe5dlSy0CAA--.8221S3; Fri, 05 Jan 2024 11:44:03 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxut3vepdlO8oCAA--.7318S5; Fri, 05 Jan 2024 11:44:02 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, chenxiaolong Subject: [PATCH v2 1/7] LoongArch: testsuite:Added support for vector object detection. Date: Fri, 5 Jan 2024 11:43:23 +0800 Message-Id: <20240105034329.21117-2-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S5 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgEzAAAsE X-Coremail-Antispam: 1Uk129KBj9fXoWfXryrKr13Xw17uFWUur4kuFX_yoW5Ar1kKo WYgFWY9r4Iq3yftryFkw17KryUWrn7Xrs5XFy7CrsrCF9rXFWrAay3Wr1vvFy7Jay3XFWk JFZ2gF4kCFyxtF47l-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYb7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UNvtZUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220591299695792 X-GMAIL-MSGID: 1787220591299695792 In the GCC of LoongArch architecture, the detection function of common vectorization test cases is enabled. The following detection procedure is added to the target-supports.exp file: 1.check_effective_target_scalar_all_fma 2.check_effective_target_vect_int 3.check_effective_target_vect_intfloat_cvt 4.check_effective_target_vect_doubleint_cvt 5.check_effective_target_vect_intdouble_cvt 6.check_effective_target_vect_uintfloat_cvt 7.check_effective_target_vect_floatint_cvt 8.check_effective_target_vect_floatuint_cvt 9.check_effective_target_vect_shift 10.check_effective_target_vect_var_shift 11.check_effective_target_whole_vector_shift 12.check_effective_target_vect_bswap 13.check_effective_target_vect_bool_cmp 14.check_effective_target_vect_char_add 15.check_effective_target_vect_shift_char 16.check_effective_target_vect_long 17.check_effective_target_vect_float 18.check_effective_target_vect_double 19.check_effective_target_vect_long_long 20.check_effective_target_vect_perm 21.check_effective_target_vect_perm_byte 22.check_effective_target_vect_perm_short 23.check_effective_target_vect_widen_sum_hi_to_si 24.check_effective_target_vect_widen_sum_qi_to_hi 25.check_effective_target_vect_widen_sum_qi_to_hi 26.check_effective_target_vect_widen_mult_qi_to_hi 27.check_effective_target_vect_widen_mult_hi_to_si 28.check_effective_target_vect_widen_mult_qi_to_hi_pattern 29.check_effective_target_vect_widen_mult_hi_to_si_pattern 30.check_effective_target_vect_widen_mult_si_to_di_pattern 31.check_effective_target_vect_sdot_qi 32.check_effective_target_vect_udot_qi 33.check_effective_target_vect_sdot_hi 34.check_effective_target_vect_udot_hi 35.check_effective_target_vect_usad_char 36.check_effective_target_vect_avg_qi 37.check_effective_target_vect_pack_trunc 38.check_effective_target_vect_unpack 39.check_effective_target_vect_hw_misalign 40.check_effective_target_vect_gather_load_ifn 40.check_effective_target_vect_condition 42.check_effective_target_vect_cond_mixed 43.check_effective_target_vect_char_mult 44.check_effective_target_vect_short_mult 45.check_effective_target_vect_int_mult 46.check_effective_target_vect_long_mult 47.check_effective_target_vect_int_mod 48.check_effective_target_vect_extract_even_odd 49.check_effective_target_vect_interleave 50.check_effective_target_vect_call_copysignf 51.check_effective_target_vect_call_sqrtf 52.check_effective_target_vect_call_lrint 53.check_effective_target_vect_call_btrunc 54.check_effective_target_vect_call_btruncf 55.check_effective_target_vect_call_ceil 56.check_effective_target_vect_call_ceilf 57.check_effective_target_vect_call_floor 58.check_effective_target_vect_call_floorf 59.check_effective_target_vect_call_lceil 60.check_effective_target_vect_call_lfloor 61.check_effective_target_vect_logical_reduc 62.check_effective_target_section_anchors 63.check_vect_support_and_set_flags 64.check_effective_target_vect_max_reduc 65.check_effective_target_loongarch_sx 66.check_effective_target_loongarch_sx_hw gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add LoongArch to the list of supported targets. --- gcc/testsuite/lib/target-supports.exp | 217 +++++++++++++++++++------- 1 file changed, 162 insertions(+), 55 deletions(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 167e630f5a5..9addf35ade4 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3815,7 +3815,11 @@ proc add_options_for_bfloat16 { flags } { # (fma, fms, fnma, and fnms) for both float and double. proc check_effective_target_scalar_all_fma { } { - return [istarget aarch64*-*-*] + if { [istarget aarch64*-*-*] + || [istarget loongarch*-*-*]} { + return 1 + } + return 0 } # Return 1 if the target supports compiling fixed-point, @@ -4051,6 +4055,8 @@ proc check_effective_target_vect_int { } { && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -4218,7 +4224,9 @@ proc check_effective_target_vect_intfloat_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports signed double->int conversion @@ -4239,7 +4247,9 @@ proc check_effective_target_vect_doubleint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports signed int->double conversion @@ -4260,7 +4270,9 @@ proc check_effective_target_vect_intdouble_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } #Return 1 if we're supporting __int128 for target, 0 otherwise. @@ -4293,7 +4305,9 @@ proc check_effective_target_vect_uintfloat_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -4312,7 +4326,9 @@ proc check_effective_target_vect_floatint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports unsigned float->int conversion @@ -4329,7 +4345,9 @@ proc check_effective_target_vect_floatuint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector integer char -> long long extend optab @@ -4338,7 +4356,9 @@ proc check_effective_target_vect_floatuint_cvt { } { proc check_effective_target_vect_ext_char_longlong { } { return [check_cached_effective_target_indexed vect_ext_char_longlong { expr { ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if peeling for alignment might be profitable on the target @@ -7462,7 +7482,9 @@ proc check_effective_target_vect_shift { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware vector shift by register operation. @@ -7474,6 +7496,8 @@ proc check_effective_target_vect_var_shift { } { || [istarget aarch64*-*-*] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -7490,7 +7514,9 @@ proc check_effective_target_whole_vector_shift { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) } { + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) } { set answer 1 } else { set answer 0 @@ -7507,6 +7533,7 @@ proc check_effective_target_vect_bswap { } { expr { ([istarget aarch64*-*-*] || [is-effective-target arm_neon] || [istarget amdgcn-*-*]) + || [istarget loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] } @@ -7520,7 +7547,9 @@ proc check_effective_target_vect_bool_cmp { } { || [istarget aarch64*-*-*] || [is-effective-target arm_neon] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports addition of char vectors for at least @@ -7543,6 +7572,8 @@ proc check_effective_target_vect_char_add { } { && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -7559,7 +7590,9 @@ proc check_effective_target_vect_shift_char { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware vectors of long, 0 otherwise. @@ -7580,7 +7613,9 @@ proc check_effective_target_vect_long { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) } { + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) } { set answer 1 } else { set answer 0 @@ -7610,7 +7645,9 @@ proc check_effective_target_vect_float { } { && [check_effective_target_s390_vxe]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware vectors of float without @@ -7641,7 +7678,9 @@ proc check_effective_target_vect_double { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v])} }] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports conditional addition, subtraction, @@ -7669,7 +7708,9 @@ proc check_effective_target_vect_long_long { } { && [check_effective_target_has_arch_pwr8]) || [istarget aarch64*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v])}}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx])}}] } @@ -7724,7 +7765,9 @@ proc check_effective_target_vect_perm { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if, for some VF: @@ -7819,7 +7862,9 @@ proc check_effective_target_vect_perm_byte { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports SLP permutation of 3 vectors when each @@ -7850,7 +7895,9 @@ proc check_effective_target_vect_perm_short { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports SLP permutation of 3 vectors when each @@ -7898,6 +7945,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { } { expr { [check_effective_target_vect_unpack] || [istarget powerpc*-*-*] || [istarget ia64-*-*] + || [istarget loongarch*-*-*] || [istarget riscv*-*-*] }}] } @@ -7913,7 +7961,8 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { expr { [check_effective_target_vect_unpack] || [is-effective-target arm_neon] || [istarget ia64-*-*] - || [istarget riscv*-*-*] }}] + || [istarget riscv*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target plus current options supports a vector @@ -7924,6 +7973,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { proc check_effective_target_vect_widen_sum_qi_to_si { } { return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si { expr { [istarget powerpc*-*-*] + || [istarget loongarch*-*-*] || [istarget riscv*-*-*] }}] } @@ -7944,6 +7994,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } { || ([istarget aarch64*-*-*] && ![check_effective_target_aarch64_sve]) || [is-effective-target arm_neon] + || [is-effective-target loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx])) || [istarget amdgcn-*-*] }}] @@ -7968,6 +8019,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } { && ![check_effective_target_aarch64_sve]) || [istarget i?86-*-*] || [istarget x86_64-*-*] || [is-effective-target arm_neon] + || [is-effective-target loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx])) || [istarget amdgcn-*-*] }}] @@ -7985,6 +8037,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } { && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) + || [istarget loongarch*-*-*] || [istarget amdgcn-*-*] }}] } @@ -7997,6 +8050,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } { return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern { expr { [istarget powerpc*-*-*] || [istarget ia64-*-*] + || [istarget loongarch*-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) @@ -8014,6 +8068,7 @@ proc check_effective_target_vect_widen_mult_si_to_di_pattern { } { return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern { expr { [istarget ia64-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] + || [istarget loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] } @@ -8041,7 +8096,9 @@ proc check_effective_target_vect_sdot_qi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8058,7 +8115,9 @@ proc check_effective_target_vect_udot_qi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8087,7 +8146,9 @@ proc check_effective_target_vect_sdot_hi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8101,7 +8162,9 @@ proc check_effective_target_vect_udot_hi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8118,7 +8181,9 @@ proc check_effective_target_vect_usad_char { } { || ([istarget powerpc*-*-*] && [check_p9vector_hw_available]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports both signed @@ -8128,7 +8193,9 @@ proc check_effective_target_vect_avg_qi {} { return [expr { ([istarget aarch64*-*-*] && ![check_effective_target_aarch64_sve1_only]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }] } # Return 1 if the target plus current options supports both signed @@ -8167,7 +8234,9 @@ proc check_effective_target_vect_pack_trunc { } { && [check_effective_target_s390_vx]) || [istarget amdgcn*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8189,7 +8258,9 @@ proc check_effective_target_vect_unpack { } { && [check_effective_target_s390_vx]) || [istarget amdgcn*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options does not guarantee @@ -8230,7 +8301,8 @@ proc check_effective_target_vect_hw_misalign { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || ([istarget riscv*-*-*]) } { + || ([istarget riscv*-*-*]) + || ([istarget loongarch*-*-*]) } { return 1 } if { [istarget arm*-*-*] @@ -8849,7 +8921,8 @@ proc check_effective_target_vect_gather_load_ifn { } { proc check_effective_target_vect_scatter_store { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v] + || [check_effective_target_loongarch_sx] }] } # Return 1 if the target supports vector conditional operations, 0 otherwise. @@ -8868,7 +8941,9 @@ proc check_effective_target_vect_condition { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector conditional operations where @@ -8887,7 +8962,9 @@ proc check_effective_target_vect_cond_mixed { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector char multiplication, 0 otherwise. @@ -8905,7 +8982,9 @@ proc check_effective_target_vect_char_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector short multiplication, 0 otherwise. @@ -8924,7 +9003,9 @@ proc check_effective_target_vect_short_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector int multiplication, 0 otherwise. @@ -8942,7 +9023,9 @@ proc check_effective_target_vect_int_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports 64 bit hardware vector @@ -8961,7 +9044,9 @@ proc check_effective_target_vect_long_mult { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) } { + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) } { set answer 1 } else { set answer 0 @@ -8999,7 +9084,9 @@ proc check_effective_target_vect_extract_even_odd { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector interleaving, 0 otherwise. @@ -9017,7 +9104,9 @@ proc check_effective_target_vect_interleave { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } foreach N {2 3 4 5 6 7 8} { @@ -9142,7 +9231,9 @@ proc check_effective_target_vect_call_copysignf { } { || [istarget aarch64*-*-*] || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware square root instructions. @@ -9181,7 +9272,9 @@ proc check_effective_target_vect_call_sqrtf { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector lrint calls. @@ -9190,7 +9283,8 @@ proc check_effective_target_vect_call_lrint { } { set et_vect_call_lrint 0 if { (([istarget i?86-*-*] || [istarget x86_64-*-*]) && [check_effective_target_ilp32]) - || [istarget amdgcn-*-*] } { + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] } { set et_vect_call_lrint 1 } @@ -9203,7 +9297,8 @@ proc check_effective_target_vect_call_lrint { } { proc check_effective_target_vect_call_btrunc { } { return [check_cached_effective_target_indexed vect_call_btrunc { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector btruncf calls. @@ -9211,7 +9306,8 @@ proc check_effective_target_vect_call_btrunc { } { proc check_effective_target_vect_call_btruncf { } { return [check_cached_effective_target_indexed vect_call_btruncf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector ceil calls. @@ -9219,7 +9315,8 @@ proc check_effective_target_vect_call_btruncf { } { proc check_effective_target_vect_call_ceil { } { return [check_cached_effective_target_indexed vect_call_ceil { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector ceilf calls. @@ -9227,7 +9324,8 @@ proc check_effective_target_vect_call_ceil { } { proc check_effective_target_vect_call_ceilf { } { return [check_cached_effective_target_indexed vect_call_ceilf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector floor calls. @@ -9235,7 +9333,8 @@ proc check_effective_target_vect_call_ceilf { } { proc check_effective_target_vect_call_floor { } { return [check_cached_effective_target_indexed vect_call_floor { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector floorf calls. @@ -9243,21 +9342,24 @@ proc check_effective_target_vect_call_floor { } { proc check_effective_target_vect_call_floorf { } { return [check_cached_effective_target_indexed vect_call_floorf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector lceil calls. proc check_effective_target_vect_call_lceil { } { return [check_cached_effective_target_indexed vect_call_lceil { - expr { [istarget aarch64*-*-*] }}] + expr { [istarget aarch64*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector lfloor calls. proc check_effective_target_vect_call_lfloor { } { return [check_cached_effective_target_indexed vect_call_lfloor { - expr { [istarget aarch64*-*-*] }}] + expr { [istarget aarch64*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector nearbyint calls. @@ -9294,6 +9396,7 @@ proc check_effective_target_vect_logical_reduc { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn-*-*] || [check_effective_target_riscv_v] + || [check_effective_target_loongarch_sx] || [istarget i?86-*-*] || [istarget x86_64-*-*]}] } @@ -9311,7 +9414,8 @@ proc check_effective_target_section_anchors { } { return [check_cached_effective_target section_anchors { expr { [istarget powerpc*-*-*] || [istarget arm*-*-*] - || [istarget aarch64*-*-*] }}] + || [istarget aarch64*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports atomic operations on "int_128" values. @@ -11623,8 +11727,10 @@ proc check_vect_support_and_set_flags { } { set dg-do-what-default compile } } elseif [istarget loongarch*-*-*] { - lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlasx" - if [check_effective_target_loongarch_asx_hw] { + # Set the default vectorization option to "-mlsx" due to the problem + # of non-aligned memory access when using 256-bit vectorization. + lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx" + if [check_effective_target_loongarch_sx_hw] { set dg-do-what-default run } else { set dg-do-what-default compile @@ -12190,7 +12296,8 @@ proc check_effective_target_builtin_eh_return { } { proc check_effective_target_vect_max_reduc { } { if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] - || [check_effective_target_riscv_v] } { + || [check_effective_target_riscv_v] + || [check_effective_target_loongarch_sx] } { return 1 } return 0 @@ -13205,7 +13312,7 @@ proc check_effective_target_loongarch_sx { } { #if !defined(__loongarch_sx) #error "LSX not defined" #endif - }] + } "-mlsx"] } proc check_effective_target_loongarch_sx_hw { } { @@ -13225,7 +13332,7 @@ proc check_effective_target_loongarch_asx { } { #if !defined(__loongarch_asx) #error "LASX not defined" #endif - }] + } "-mlasx"] } proc check_effective_target_loongarch_asx_hw { } { From patchwork Fri Jan 5 03:43:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 185208 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6007579dyb; Thu, 4 Jan 2024 19:45:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IEozxVIUDBANHeHlsPPGNYbddXga+J62hgXcZWKzxS3tfwzhT0k1a2ycx+bApI94Bgadfq9 X-Received: by 2002:a05:622a:50b:b0:428:39a1:ff70 with SMTP id l11-20020a05622a050b00b0042839a1ff70mr2110076qtx.25.1704426328854; Thu, 04 Jan 2024 19:45:28 -0800 (PST) Received: from server2.sourceware.org (server2.sourceware.org. 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Date: Fri, 5 Jan 2024 11:43:24 +0800 Message-Id: <20240105034329.21117-3-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S6 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgEzgAAsG X-Coremail-Antispam: 1Uk129KBj93XoW7Zr45Cr1rWFW3XF1kuw4xZrc_yoW8Aryrp3 Z3CrZayr48XF1UW3WDWF9rX3Z5Xan7GrZ8urZ7uw47GFyktr9IvFW0yr47tw13JFW0vrya qw4Y9F18u3ZavrXCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8wNVDUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220542432827421 X-GMAIL-MSGID: 1787220542432827421 Before modifying the test behavior of the program, dg-do is set to assemble in vect-bic-bitmask-{12,23}.c. However, when the binutils library does not support the vector instruction set, it will FAIL to recognize the vector instruction and fail item will appear in the assembly stage. So set the program's dg-do to compile. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bic-bitmask-12.c: Change the default setting of assembly to compile. * gcc.dg/vect/vect-bic-bitmask-23.c: Dito. --- gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c index 36ec5a8b19b..213e4c2a418 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c @@ -1,5 +1,5 @@ /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ -/* { dg-do assemble } */ +/* { dg-do compile } */ /* { dg-additional-options "-O3 -fdump-tree-dce -w" } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c index 5b4c3b6e19b..5dceb4bbcb6 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c @@ -1,5 +1,5 @@ /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ -/* { dg-do assemble } */ +/* { dg-do compile } */ /* { dg-additional-options "-O1 -fdump-tree-dce -w" } */ #include From patchwork Fri Jan 5 03:43:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 185211 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6007874dyb; Thu, 4 Jan 2024 19:46:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IEsjNk7jVXFgYW4cT657f8nshk03CZqts45kwHFB7/8lJv/uM7kbl+d9QVCVxVVLPr0t+Nk X-Received: by 2002:a05:622a:15d1:b0:428:318d:eede with SMTP id d17-20020a05622a15d100b00428318deedemr1976856qty.76.1704426395883; Thu, 04 Jan 2024 19:46:35 -0800 (PST) Received: from server2.sourceware.org (server2.sourceware.org. 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Date: Fri, 5 Jan 2024 11:43:25 +0800 Message-Id: <20240105034329.21117-4-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S7 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgE0QAAsZ X-Coremail-Antispam: 1Uk129KBj93XoW7KFWfZF4DGF1xZr4UZrWftFc_yoW8XrW7p3 Z7CrySyw10gF1UWFnFvF95XF1Fg3Z7JrZF9ry2gwsFkFyxJr9Fva40yr42qr13JFW2vF1f u3y8uw1ru3WYqrbCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8QJ57UUUUU== X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220612349130136 X-GMAIL-MSGID: 1787220612349130136 gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-82.c: Add the LoongArch architecture to the object detection framework. * gcc.dg/vect/vect-83.c: Dito. --- gcc/testsuite/gcc.dg/vect/vect-82.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-83.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-82.c b/gcc/testsuite/gcc.dg/vect/vect-82.c index 4b2d5a8a464..5c761e92a3a 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-82.c +++ b/gcc/testsuite/gcc.dg/vect/vect-82.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */ +/* { dg-skip-if "powerpc/loongarch and integer vectorization only" { ! { { powerpc*-*-* || loongarch*-*-* } && vect_int } } } */ /* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/vect-83.c b/gcc/testsuite/gcc.dg/vect/vect-83.c index 1a173daa140..7fe1b050cee 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-83.c +++ b/gcc/testsuite/gcc.dg/vect/vect-83.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */ +/* { dg-skip-if "powerpc/loongarch and integer vectorization only" { ! { { powerpc*-*-* || loongarch*-*-* } && vect_int } } } */ /* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */ #include From patchwork Fri Jan 5 03:43:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 185212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6008098dyb; Thu, 4 Jan 2024 19:47:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/ritV8r+TEdkuPzTVJjmErOTbXNnDEzqi4JLVBAuETNKD0MJV0Sd9XZprSIQm20UnoF2/ X-Received: by 2002:a05:622a:550:b0:427:a420:b1f with SMTP id m16-20020a05622a055000b00427a4200b1fmr1992393qtx.13.1704426449497; Thu, 04 Jan 2024 19:47:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704426449; cv=pass; d=google.com; s=arc-20160816; b=1CeOrwYQpMGafpOp0TTCT+5OPMbF1xDOvO29umji8ayIwMD7+jLrvNGfSvj0LTiTze 6OxrjxYU+0ZRLLAxRGG1/NWSS92vL3l8Ujd0A4IU/UEr2k8y1jghikLP0xXihFIswRW6 xYL8lN2jTOxB3eOeBUsNShxoyMsmpTv6aa2qZWErKweyTvPHhrmTwgHTuHUhKVeldJuQ +9nFKw2SP03yVuWzlHQ7qhNiBM33YACZC7UyivLU0kd5NZoBer+hEclrurljt84aLN3f 3qQnpk7FtDpxpFW1Mz/dg8T9n4DMg8VW1G5ctCEKBOeLEa0okj8CXD+YEXch3wxiCfmK O0PA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=45oXKLoF0N4RVWUpdhAJfVgFnIBCqwnCFskkhzXwa+A=; fh=FZUwle8+72fCZy+/zioADwckSVaPYtJTkTncWlIM74g=; b=xVDzEu7RKFcONBPi/V5lWHQdY4gLOtiTmusbrBPWGRmVKwRpSiZs6KkOxHUfLpBivD BhCTvWU3Ckw58LbnPI40ZJEwC8yHhvMHEAQ0WLKE9s5WjAlkUQvmu740f3Bfp1uwTPza knNXxw533ouaPVxG1MAL+ND8F/cWvViTRr7cbb/gU0dNgXAQ+43X4l3N2H8V9KpKbc3+ DXbFTLYTppf6Fl/aN+jb5VA1UB89SCBPHD3zr2I9ZNo3SFU8ipt7/4gvBavwpPX0PW3H UcTHO4VcXZiniBWQ08umVHFzXCXYxejEzgUja9ZjVJtMNS23BWpU+iCgB+TigMBw4Pps DeRQ== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id x19-20020ac85f13000000b0042809a4ac2fsi997124qta.790.2024.01.04.19.47.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 19:47:29 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 260CC3857BA0 for ; Fri, 5 Jan 2024 03:47:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 0D18D3857C6B for ; Fri, 5 Jan 2024 03:44:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D18D3857C6B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0D18D3857C6B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426267; cv=none; b=S5YsGNc72yJtivWK5ENvULElYspnnyBrT/93fKhXEM9ugtoE+hM9GFHV8yN5RDlJikPY8NJm8077WrJrBfkIuOkztEb0rf7Sul9n2X99zXknlZ3jV4dJArdwwGtHPNC7BfMQPnZNzrM7vIXvrl/epwCwRADpBISswg+o35mW7A0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426267; c=relaxed/simple; bh=w7jarlGDpAJeRHSjgbgPrxBFSHGtJDJBy9hgalLCqJQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PQ0xXX0GLUDI0QbIIpoKNANQ626W52zVsRi5zt5Hr4gQ5oYlGZi27/g26v4+Y/6BsXc5aUU2M40LpvPgDGpZSMr65ZFP1Ai8Bo/hx1PZzW1PPfYzQ3VR23ZQuW3TX/hEkBFMHVgCUt8K6JDLItf2kZ8ZMmSzxk3aXxyxzXRJTnA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8DxeeoVe5dlWi0CAA--.4034S3; Fri, 05 Jan 2024 11:44:21 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxut3vepdlO8oCAA--.7318S8; Fri, 05 Jan 2024 11:44:21 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, chenxiaolong Subject: [PATCH v2 4/7] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90. Date: Fri, 5 Jan 2024 11:43:26 +0800 Message-Id: <20240105034329.21117-5-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S8 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgE0wAAsb X-Coremail-Antispam: 1Uk129KBj93XoW7Zr1xZF48XFW8WrW8WF13KFX_yoW8ZF4xp3 sxZa45KFn8JF1Iyw1kJFs5Ww48WrZFgFyruFWfGw4UCanxta4fXr4xKFW7Jryjka1fXr4a qF4UZFyxZFyqy3gCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07josjUUUUUU= X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220669054905106 X-GMAIL-MSGID: 1787220669054905106 On the LoongArch architecture, an error was found in the bind_c_array_params_2.f90 file because there was no proper assembly code for the regular expression detection function call, such as bl %plt(myBindC). gcc/testsuite/ChangeLog: * gfortran.dg/bind_c_array_params_2.f90: Add code test rules to support testing of the loongArch architecture. --- gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 index 0825efc7a2f..aa6a37b4850 100644 --- a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 +++ b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 @@ -2,6 +2,7 @@ ! { dg-options "-std=f2008ts -fdump-tree-original" } ! { dg-additional-options "-mno-explicit-relocs" { target alpha*-*-* } } ! { dg-additional-options "-mno-relax-pic-calls" { target mips*-*-* } } +! { dg-additional-options "-fplt -mcmodel=normal" { target loongarch*-*-* } } ! ! Check that assumed-shape variables are correctly passed to BIND(C) ! as defined in TS 29913 @@ -16,7 +17,8 @@ integer :: aa(4,4) call test(aa) end -! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* powerpc-ibm-aix* *-*-ming* } } } } } +! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* powerpc-ibm-aix* *-*-ming* loongarch*-*-* } } } } } +! { dg-final { scan-assembler-times "bl\t%plt\\(myBindC\\)" 1 { target loongarch*-*-* } } } ! { dg-final { scan-assembler-times "myBindC,%r2" 1 { target { hppa*-*-* } } } } ! { dg-final { scan-assembler-times "call\tmyBindC" 1 { target { *-*-cygwin* *-*-ming* } } } } ! { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,myBindC" 1 { target { s390*-*-* } } } } From patchwork Fri Jan 5 03:43:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 185213 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6008288dyb; Thu, 4 Jan 2024 19:48:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IF1o2t/38bSaPkyM/qhOY+r0swhvpCFu3SlLO0VOnRzMb/Aohr9k0jfQfHotu68sizjRCw3 X-Received: by 2002:ac8:594a:0:b0:428:34d9:d81 with SMTP id 10-20020ac8594a000000b0042834d90d81mr1540074qtz.123.1704426505596; Thu, 04 Jan 2024 19:48:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704426505; cv=pass; d=google.com; s=arc-20160816; b=cnJ3pIPIxtcFZIxNBHNNfkbHK6qP8Ug+NonLRjiEHZpBqLqHuxOY9QOvtLiCdkRHhw KFM23GiRL8pAkt3ZXTmdSTZftab0flQqk32zyPEWHoHnvvWnYNkq1OrugJiWX/UL0Fss q68I1vWd+77ybIeVT3RW+U09C1e5MYRgxFaaKSYmkSu0IsZdmux0RklCJ5jCZbtAXBsS k5otWag3840zmmz/yI5yZTg0MVjr1JMP4kQ5A1T3jJZzB6qZ7SkzLTFr9Rum842Q6VmO VF1qVaN+P2a83e0f9zbVPzPryYv4DyuctsrwRsMjU37okvFmT1OqC+P9JFjTPEnlBUcs 7WPw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=ELiNIYbnmwCWyZCzkRSq82FdWgObgpB7T15tIs+Lbpc=; fh=FZUwle8+72fCZy+/zioADwckSVaPYtJTkTncWlIM74g=; b=Q+nJ41FeOdgdGlSVcqMxsdTUTQhK09bK+KlK9LJ93ik9CRdsQaif6NHH2CIssYf5zF 4RxoSuvu+kCKU74SRjKuN+pLIjfGU8Dzsz0yoYvyLdD+qj9xHzQyIgzY0HIZ/J9rGYKC yiyUg04P3zKV8NdH/COIhDVgYV04iU1PtcD7KSPyTGozuTd1DW3ROpdJaEMQanYMw+pw NgP87E3dUr5HhaKtUjOTZ9/5lEQHRLAlPEQZmbV1A+KS/LvyUdcDTwYFGKnva398wFT1 ac3qrChtfSm1ogKF9i3XnLdHwjPUnJkfu0tEq0lgNf+NmV6jE4zJdQXjFsnRL/LFwx5w X9dg== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q15-20020a05622a030f00b00423707e09fasi1046900qtw.651.2024.01.04.19.48.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 19:48:25 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4DCFC3858D32 for ; Fri, 5 Jan 2024 03:48:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 2D3DB3857C77 for ; Fri, 5 Jan 2024 03:44:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2D3DB3857C77 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2D3DB3857C77 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426268; cv=none; b=tjaFu5WADw0Se+9wlidXCo1TMLLWoZrMmVEPoOB88MLIVyFoD0Xy3J8pBH4z0lNNIdrNsbI/hecoDB/R6Mr86NKIwfLFhlrwJS7AAueCF3SxFZnue2/G9jTv1fxzuKWxyX/iNyHpGFtg68QaPrrjuo7RnTV/OMbYv2e97SpxotY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426268; c=relaxed/simple; bh=S5oI5ffKZGrddcMhSETKjVyX+QVhPwS4XYS/MRQlykM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=dkzcCb3YMjLFubcteEgVGZ4HV75zVJe9YPGxWZ+j4kHxU1YcbSn2iP41T+i6YmaEIacAvE8arxzFQNVOCjcgobT+7wZVChNuti+doErMVgVTon8SOPfN7qHW1HK440YJGfd0DmxcNsl3s7IViaiMQHS6zn/qYLYQ2MkZd/Lt93U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8BxHOsYe5dlXC0CAA--.8182S3; Fri, 05 Jan 2024 11:44:24 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxut3vepdlO8oCAA--.7318S9; Fri, 05 Jan 2024 11:44:23 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, chenxiaolong Subject: [PATCH v2 5/7] LoongArch: testsuite:Delete the default run behavior in pr60510.f. Date: Fri, 5 Jan 2024 11:43:27 +0800 Message-Id: <20240105034329.21117-6-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S9 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgE1QAAsd X-Coremail-Antispam: 1Uk129KBj9xXoW7GryxuF18Ar4DWF4rZF47trc_yoWDGrcEva ykZF4fCw4UAws5Jw17GwnrKryvqa95X3yfGF48Kw1xtanYqws0qrn7CFyxAFy5CFnxJFW7 KryfJF4Sy3sFgosvyTuYvTs0mTUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvT s0mT0YCTnIWjqI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUI cSsGvfJTRUUUb7AYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20x vaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV W8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAF wI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU84xRDUUUUU== X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220727622730740 X-GMAIL-MSGID: 1787220727622730740 When binutils does not support vector instruction sets, the test program fails because it does not recognize vectorization at the assembly stage. Therefore, the default run behavior of the program is deleted, so that the behavior of the program depends on whether the software supports vectorization. gcc/testsuite/ChangeLog: * gfortran.dg/vect/pr60510.f: Delete the default behavior of the program. --- gcc/testsuite/gfortran.dg/vect/pr60510.f | 1 - 1 file changed, 1 deletion(-) diff --git a/gcc/testsuite/gfortran.dg/vect/pr60510.f b/gcc/testsuite/gfortran.dg/vect/pr60510.f index 6cae82acece..d4fd42a664a 100644 --- a/gcc/testsuite/gfortran.dg/vect/pr60510.f +++ b/gcc/testsuite/gfortran.dg/vect/pr60510.f @@ -1,4 +1,3 @@ -! { dg-do run } ! { dg-require-effective-target vect_double } ! { dg-require-effective-target vect_intdouble_cvt } ! { dg-additional-options "-fno-inline -ffast-math" } From patchwork Fri Jan 5 03:43:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 185214 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6008581dyb; Thu, 4 Jan 2024 19:49:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IFLU3jLYxFxFb1N1a/j9/dkD/O2+n/W7ati44vwbxEam4/KOwzphixwapqj6EZiGJWzTMh/ X-Received: by 2002:ad4:5948:0:b0:680:a521:d86 with SMTP id eo8-20020ad45948000000b00680a5210d86mr2736026qvb.47.1704426580686; Thu, 04 Jan 2024 19:49:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704426580; cv=pass; d=google.com; s=arc-20160816; b=J127O22e6hig1e8sKGOVzDXU+hBVjAnnKx7ojadAIj8NZdsQKm0WwsFtKmdzWQ+rwJ tDC4YRwBT8j1hb7wnr+av8iNciebXdKEv7SPLvPs8FFIPzcK/vRuAGbmJGHybcUGL6rW h2gGrFzd5ZiC80Kob3BCVaBWkJBH5Aspnwp9uiu6k9AhwVy1rAtXG0uokozvyk0bS1tN EeEc5cVQVEwbS2kpywO/Gs8nTMz9Lcd4d9tBHC4DpwTzPSr+1K9YMbzCI4w0b+7Gg0y0 gWSfy+GGwoKNlIwN77VYnBZAjfuUz40oz2BmoZaKiqXvQCOgIRWwKL5kfH6LSdRqx4Y6 nUQA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=r5gxeODRIeQLNnqzOGFIzoFNSyirSWFrl0GjQ9xEH4U=; fh=FZUwle8+72fCZy+/zioADwckSVaPYtJTkTncWlIM74g=; b=pYVfKNVoUHw3UtYrom+kyvfTmmwv+dq75qIzKSb2COBSv+nRrBxtCv3mrfhSwsLM6e RoDKtQhB7tdRzEIlkrTKB1f29OVv8g2QDYJxeDxkCdKB/DU8T/LP48bNBeRRUVBQF/aN MEAvzfgGW/Fuq/uftMUS+pz63tNgPl/DvjjHIerRsv23ywvPkVSVzDouBRLUa0H6zyiX QE8uec/94GIX+/YAQ99iPJxO7Pz90ZbZc1DXEe0rBBbwUL99GpKL600ccmzoY5hlMYi6 /HcHGn1WFZuZgf+q+ldDYwiDTl9O3ZXtr5y1QdZg3Eq5WIcCtH/QDRZxhMBc2t0Rn6bN T6bw== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id s25-20020a0cb319000000b00680c838d0fdsi1002363qve.169.2024.01.04.19.49.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 19:49:40 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65D423857C64 for ; Fri, 5 Jan 2024 03:49:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 29A5D3857C5C for ; Fri, 5 Jan 2024 03:44:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 29A5D3857C5C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 29A5D3857C5C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426274; cv=none; b=ZbYeM3w1rrBGOob2FWLw7ufV/lxCSIifE413b1wloVc/K8K8IpfDXjeGnHxcQt3ozoal+jeinoGMZX6Md+IqPTPJVroIWrWJEf70uMtfpXZFTWjmmwE8xXEs2S+S8QC6cVjAHJaFIZ4T+9W414LEFk8jRXubKtbyYqO0amGH9js= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704426274; c=relaxed/simple; bh=NYKeGmUhZn+zUUTWTF7EiMLcxuCVaGhPiBy+/ZOWzFQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=IFtYcWTabU/G9YNGgKWAjblXVI6AJHvWSFBmiEmh3Lgt2wj4PXluW674rQE4hjeHJHOAZ6/OinuvA6QJv1Gl5eb8U0Wa+02o3zhTknWNHtl0ScVIkCup7lANdwx+pRnnf9GdEdLMnlDCIAM541vUrOkYFLLJGQwh3WSTSQ/Zk3I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rLb8H-0003PN-Tc for gcc-patches@gcc.gnu.org; Thu, 04 Jan 2024 22:44:31 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8Cxaeoae5dlYS0CAA--.3993S3; Fri, 05 Jan 2024 11:44:26 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxut3vepdlO8oCAA--.7318S10; Fri, 05 Jan 2024 11:44:25 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, chenxiaolong Subject: [PATCH v2 6/7] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option. Date: Fri, 5 Jan 2024 11:43:28 +0800 Message-Id: <20240105034329.21117-7-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S10 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgE1wAAsf X-Coremail-Antispam: 1Uk129KBj93XoWxKrW8Aw4fuw4fJw48Gw1xZwc_yoW3Xr1Dpa nxCrySkr1rWF1DurnruFZ3Z3Z3G3ZrWrZ09ryfKw4IkFy3KrnFvw18trW7JF13AFWF9r1f Zw48ur1ru3WYvwbCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 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SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220806156312268 X-GMAIL-MSGID: 1787220806156312268 In the LoongArch architecture, the reason for not adding the 128-bit vector-width-*hi* instruction template in the GCC back end is that it causes program performance loss, so we can only add the "-mlasx" compilation option to use 256-bit vectorization functions in test files. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-pattern-1.c: If you are testing on the LoongArch architecture, you need to add the "-mlasx" compilation option to generate vectorized code. * gcc.dg/vect/slp-widen-mult-half.c: Dito. * gcc.dg/vect/vect-widen-mult-const-s16.c: Dito. * gcc.dg/vect/vect-widen-mult-const-u16.c: Dito. * gcc.dg/vect/vect-widen-mult-half-u8.c: Dito. * gcc.dg/vect/vect-widen-mult-half.c: Dito. * gcc.dg/vect/vect-widen-mult-u16.c: Dito. * gcc.dg/vect/vect-widen-mult-u8-s16-s32.c: Dito. * gcc.dg/vect/vect-widen-mult-u8-u32.c: Dito. * gcc.dg/vect/vect-widen-mult-u8.c: Dito. --- gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c | 1 + gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c | 1 + 10 files changed, 10 insertions(+) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c index a3ff0f5b3da..5ae99225273 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c @@ -1,4 +1,5 @@ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c index 72811eb852e..b69ade33886 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c +++ b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c index dfbb2171c00..53c9b84ca01 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c @@ -2,6 +2,7 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c index c2ad58f69e7..e9db8285b66 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c @@ -2,6 +2,7 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c index bfdcbaa09fb..607f3178f90 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c @@ -2,6 +2,7 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c index e46b0cc3135..cd13d826937 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c index 14411ef43ed..258d253f401 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c index f40def5dddf..3baafca7b54 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c index 63866390835..bcfbe198a3f 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c @@ -1,5 +1,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c index 78ad74b5d49..e3bf13b14fa 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c @@ -1,5 +1,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include #include "tree-vect.h" From patchwork Fri Jan 5 03:43:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 185209 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6007705dyb; Thu, 4 Jan 2024 19:45:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IHoqgw+SiBP/6e8Z/KwoZ6Dw332MN7hQkpsPfawvdWxP11zgCvfSQmXXsdmuOMRdCoPz0gw X-Received: by 2002:a05:622a:246:b0:429:76cc:902b with SMTP id c6-20020a05622a024600b0042976cc902bmr706531qtx.7.1704426355801; Thu, 04 Jan 2024 19:45:55 -0800 (PST) Received: from server2.sourceware.org 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Date: Fri, 5 Jan 2024 11:43:29 +0800 Message-Id: <20240105034329.21117-8-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240105034329.21117-1-chenxiaolong@loongson.cn> References: <20240105034329.21117-1-chenxiaolong@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxut3vepdlO8oCAA--.7318S11 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAHBWWXVSgE2QAAsR X-Coremail-Antispam: 1Uk129KBj93XoWxGrW8Cr1xZrWxXrW7Cr45Arc_yoW5uF4Upa 17WrZxKr1rGF1kGr1xXrn2qw1SqanrKrW5uFnayr42v3Z3JF92qayktr47XFy3JFW7WFyf Zw4q93WUu3WqyagCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07j8CztUUUUU= X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787220570847802825 X-GMAIL-MSGID: 1787220570847802825 On the LoongArch architecture, the above four test cases need to be waived during testing. There are two situations: 1. The function of fma-{3,6}.c test is to find the value of c-a*b, but on the LoongArch architecture, the function of the existing fnmsub instruction is to find the value of -(a*b - c); 2. The function of fma-{4,7}.c test is to find the value of -(a*b)-c, but on the LoongArch architecture, the function of the existing fnmadd instruction is to find the value of -(a*b + c); Through the analysis of the above two cases, there will be positive and negative zero inequality. gcc/testsuite/ChangeLog * gcc.dg/fma-3.c: The intermediate file corresponding to the function does not produce the corresponding FNMA symbol, so the test rules should be skipped when testing. * gcc.dg/fma-4.c: The intermediate file corresponding to the function does not produce the corresponding FNMS symbol, so skip the test rules when testing. * gcc.dg/fma-6.c: The cause is the same as fma-3.c. * gcc.dg/fma-7.c: The cause is the same as fma-4.c --- gcc/testsuite/gcc.dg/fma-3.c | 2 +- gcc/testsuite/gcc.dg/fma-4.c | 2 +- gcc/testsuite/gcc.dg/fma-6.c | 2 +- gcc/testsuite/gcc.dg/fma-7.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.dg/fma-3.c b/gcc/testsuite/gcc.dg/fma-3.c index 699aa2c9530..6649b54b6f9 100644 --- a/gcc/testsuite/gcc.dg/fma-3.c +++ b/gcc/testsuite/gcc.dg/fma-3.c @@ -12,4 +12,4 @@ f2 (double a, double b, double c) return c - a * b; } -/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 2 "widening_mul" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 2 "widening_mul" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/fma-4.c b/gcc/testsuite/gcc.dg/fma-4.c index bff928f1fac..f1701c1961a 100644 --- a/gcc/testsuite/gcc.dg/fma-4.c +++ b/gcc/testsuite/gcc.dg/fma-4.c @@ -12,4 +12,4 @@ f2 (double a, double b, double c) return -(a * b) - c; } -/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 2 "widening_mul" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 2 "widening_mul" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/fma-6.c b/gcc/testsuite/gcc.dg/fma-6.c index 87258cec4a2..9e49b62b6de 100644 --- a/gcc/testsuite/gcc.dg/fma-6.c +++ b/gcc/testsuite/gcc.dg/fma-6.c @@ -64,4 +64,4 @@ f10 (double a, double b, double c) return -__builtin_fma (a, b, -c); } -/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 14 "optimized" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 14 "optimized" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/fma-7.c b/gcc/testsuite/gcc.dg/fma-7.c index f409cc8ee3c..86aacad7b90 100644 --- a/gcc/testsuite/gcc.dg/fma-7.c +++ b/gcc/testsuite/gcc.dg/fma-7.c @@ -64,4 +64,4 @@ f10 (double a, double b, double c) return -__builtin_fma (a, b, c); } -/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 14 "optimized" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 14 "optimized" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */