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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:14 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Conor Dooley , Krzysztof Kozlowski , Lee Jones , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 1/8] dt-bindings: mfd: stm32f7: Add binding definition for DSI Date: Thu, 4 Jan 2024 09:41:41 +0100 Message-ID: <20240104084206.721824-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148677150030795 X-GMAIL-MSGID: 1787148677150030795 Add binding definition for MIPI DSI Host controller. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v2) Changes in v2: - Add Acked-by tag of Conor Dooley include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index 8d73a9c51e2b..a4e4f9271395 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -108,6 +108,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) From patchwork Thu Jan 4 08:41:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 184936 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp5487535dyb; Thu, 4 Jan 2024 00:42:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IF176AGUriddQ2Xmqh9RRRHjx2J45MBdX2NalNJKEb/vib3ZtxCtzoYpv4884eGrY9LA5wv X-Received: by 2002:a05:6830:159:b0:6dc:7b37:232b with SMTP id j25-20020a056830015900b006dc7b37232bmr364301otp.24.1704357776846; Thu, 04 Jan 2024 00:42:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704357776; cv=none; d=google.com; s=arc-20160816; b=Dl0hcxHfmz6TqGWX2W9COBA+WGapXrkkfhXsyPEkkbn572xTtqKuV10rhBmRV+dQne MxhfyRCJ3QJTadlDz4O81cSEOVzVSr5g9eSLOJN04rnQLOrZFL10gnP5D3QNoID5DiN9 iFvILRtDiSX2THOvA8X0e0mXWlcqhyTw+SSYTvRJyT/22wmppRl2XfKrWs0ZItyKXlKV Tlt6rSnW5PuS8rwLQfKw9SfP5piEthywmaWgMQersT/DrII+DrQKUROyWtf5aBFQmle6 oUr09eSGkKN85QEunenQ0K4cQSP+BJg4MaX/OWg/hXWubZO2ucaRSyljS24AbEWqNIBs +RNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mmQnQzOW0HVCglZmRdERbSkiK/7LfpA/GFNr/QR6hMQ=; fh=vtNV/F+F7Ia7aRobr1lDLcPdFj/lrCkZfthyTDWv03U=; b=OzDH85GwU+eigvVOanBVvmEEb0yN6bF9PrrMsk/BXPh2uzgxMG65PyCP/mPdrP7O6F f0bRvM8l6q98a+XwlmugcqamS1RfsgN+c7OBNvs4mWdzPklZej4QwM9t4/DIsPf2xAUt gD+3wsJYFyPvO3KtRdtvgJdKTi/eG6mfRZ4UCPGJkb+91ulaejX48RgUZFhziH0Znqzl kF6NPXSdJTTm/XZH5qOSoWSj/NKrmBSxMT1nnZRAopirO4zPEDQ7YlhXaJZ5G7mHpd/I 2EyV8SwJA/8WB6CmqOymwyb+koU9LQPpSGNNhpNHxth+QZF7snLUfPMJ+52XMhXnYeIk VRzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RDncaYam; spf=pass (google.com: domain of linux-kernel+bounces-16378-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-16378-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:15 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 2/8] ARM: dts: stm32: add DSI support on stm32f769 Date: Thu, 4 Jan 2024 09:41:42 +0100 Message-ID: <20240104084206.721824-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148659810860208 X-GMAIL-MSGID: 1787148659810860208 Add support for MIPI DSI Host controller. Since MIPI DSI is not available on stm32f746, the patch adds the "stm32f769.dtsi" file containing the dsi node inside. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/st/stm32f769.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm32f769.dtsi new file mode 100644 index 000000000000..e09184f7079c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f746.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + interrupts = <98>; + clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + reset-names = "apb"; + status = "disabled"; + }; + }; +}; From patchwork Thu Jan 4 08:41:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 184938 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp5487650dyb; Thu, 4 Jan 2024 00:43:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IFZvWGSt3oSOR0hcInRnWKRwDHoMjdyF+5i9DGckLdRJuiuqVny12CN881LsE/ShuZdFxa3 X-Received: by 2002:a05:6214:20c9:b0:67f:8807:6151 with SMTP id 9-20020a05621420c900b0067f88076151mr271627qve.95.1704357795161; Thu, 04 Jan 2024 00:43:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704357795; cv=none; d=google.com; s=arc-20160816; b=j4cOlU24eIIpkMgXZwVvWqd5EJSWfB+8s0MJU3x7gaWPlfsmruNWQ2GkuU5pnNGF2v rc4VF+BTrIelJ6+0WRYQ5YDf+jxSz/n0vHUM3HzJ2OIahhk7cXjzDcfKl06D+g5BKTnQ lDV/FhwzGlrt0sAmMnGlEZmOGV5lhXxn1eF7D9yz6FEYXaL1oKBiksYF1SinfScIbKMi hOJNiTHrxQPPuPmIrrUuJflpIBNn2lucEF8Nqm1NUo+xI47gUFo9fnWGpIx6jUL0AhPF BjUX0G8vtS0cLoVtoqhCHuzBDB56oHBKJdEjmTyiKfOoMVWdVyGEVbk62YvXhOH2zyKG pKIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/mPDNXnb7QOonc0RYCjpM23Kv+HuP4dW7ug+KwP2qeg=; fh=vtNV/F+F7Ia7aRobr1lDLcPdFj/lrCkZfthyTDWv03U=; b=oi6YhulSRa72WaYs+h5h36MnpVx3CGuBQ3lIUXSUZQtGzjXrC0DD0RGnNPn0xFIrFm tkJKD9CzVO5bMYPgSsS8lcqCHVlsIpl2ra79uqNEqXoeuZa+jpSdV/BEu1KAD+B8Y7Me VaWonruyGCKbruIh+2ZI4GUAyF+rKNBXW5aVKnomACzo0KtlELLJyRfqmnCrmDV12v0g 6U3f/VtWTZolXvUldiIms2DzhQksBS69DVhiXqchX1gQKWyJVvknEHFsJcgmWjxJbkrM rYAeb8DU3nAQmE9ZPGgIiwD1P4Ll3Jhaxgfjg7qo1Vb4fmC+FOFn5EzfSLgExa3yRsVy g5kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dj6Wrnhb; spf=pass (google.com: domain of linux-kernel+bounces-16380-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-16380-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:16 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 3/8] ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco Date: Thu, 4 Jan 2024 09:41:43 +0100 Message-ID: <20240104084206.721824-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148679497280284 X-GMAIL-MSGID: 1787148679497280284 In the schematics of document UM2033, the power supply for the micro SD card is the same 3v3 voltage that is used to power other devices on the board. By generalizing the name of the voltage regulator, it can be referenced by other nodes in the device tree without creating misunderstandings. This patch is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/st/stm32f769-disco.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 5d12ae25b327..8632bd866272 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -92,9 +92,9 @@ usbotg_hs_phy: usb-phy { clock-names = "main_clk"; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc_3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -128,7 +128,7 @@ &rtc { &sdio2 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; pinctrl-names = "default", "opendrain", "sleep"; From patchwork Thu Jan 4 08:41:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 184939 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp5487724dyb; Thu, 4 Jan 2024 00:43:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IGqKLzJmCV10gThiTMh1Crm0f+yY9wRnJ32uIfybX5VIXMQP6FWlaOljaIAMS34SJ6DR6xK X-Received: by 2002:a50:ed99:0:b0:556:ebeb:74cf with SMTP id h25-20020a50ed99000000b00556ebeb74cfmr179415edr.25.1704357809967; Thu, 04 Jan 2024 00:43:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704357809; cv=none; d=google.com; s=arc-20160816; b=DPo8E7rOT2aSCwddFh1pydz0YOjS4eL+OO+rK+tnSdPlJhgRYaNxddRAwcPRkqcbat YVBse1KEgXfSBeDL6ES9gBcTVYWOp8HxN1BhGkq9P+LRZXzQJQsA6wpFdCnOZQOab2Fj Z/HnGBtINA5GdixvKSbT2bq0Dzj/wDcwImqh+K00yX6/iW8lxfeO6iB461DacjAgJBCR SHaqXkTZlm93Kc4GGGkKVu4SdhoLZQ7PtntLJyxisZHacamI0GaliBUOu8rmcnac4Rj7 91aa+gJ071rgZ5DBtL8RttUqF5sMbcgQcqva0BLfp0FzaWaoshfMLAQOYNGksM01CDHp kLhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=c6lTYGwOZkH/q3mVT10Wfxgf2APvMbHICMTqCuHaYlQ=; fh=vtNV/F+F7Ia7aRobr1lDLcPdFj/lrCkZfthyTDWv03U=; b=c5cCkOu8P1r+LRkwaS56EgsdyzSbIGcWM8tUfIi3AKdw3LDgDZUOqDasgMd4gKO/i5 kqXuSDomDmuLAxeU/HZy5GthrxT0TUAnJ5a+oH4SJZEZtKjiC9Or+f9nFCP7ofrBr+5q q0NmNhW12GGx6xo8g9fg04YQVb7PFF4mq424FqH40ji0Hgkw48hkwiYR2wNqrDvRNvhx PDhgPR8bEbUj/Hj66+H9h/CKsC19boqu7hzz4BeaaMKEyRBqxeVUc9ylnqhAe9XT7P3C V26yRc4kTfeaWn9pfvBIXJRhLqgLlSr8nk71EcY4dbwmSOMvPZDNBs7i8DJhzBe5ls24 JxsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=fH5zyrUY; spf=pass (google.com: domain of linux-kernel+bounces-16381-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-16381-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:18 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 4/8] ARM: dts: stm32: add display support on stm32f769-disco Date: Thu, 4 Jan 2024 09:41:44 +0100 Message-ID: <20240104084206.721824-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148694801509922 X-GMAIL-MSGID: 1787148694801509922 The patch adds display support on the stm32f769-disco board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/st/stm32f769-disco.dts | 72 +++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 8632bd866272..d1eb5f9c78bf 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -41,7 +41,7 @@ */ /dts-v1/; -#include "stm32f746.dtsi" +#include "stm32f769.dtsi" #include "stm32f769-pinctrl.dtsi" #include #include @@ -60,6 +60,19 @@ memory@c0000000 { reg = <0xC0000000 0x1000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,dma { + compatible = "shared-dma-pool"; + linux,dma-default; + no-map; + size = <0x100000>; + }; + }; + aliases { serial0 = &usart1; }; @@ -85,6 +98,13 @@ button-0 { }; }; + panel_backlight: panel-backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 14 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -114,6 +134,46 @@ &clk_hse { clock-frequency = <25000000>; }; +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel0: panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>; + power-supply = <&vcc_3v3>; + backlight = <&panel_backlight>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -122,6 +182,16 @@ &i2c1 { status = "okay"; }; +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + remote-endpoint = <&dsi_in>; + }; + }; +}; + &rtc { status = "okay"; }; From patchwork Thu Jan 4 08:41:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 184940 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp5487780dyb; Thu, 4 Jan 2024 00:43:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IGjQkEbb4vZQgljnzXEtrk9L6R598oy5sZjrjcQd3+s3YwOm6VTV9W395kEXX3jeBXQPf72 X-Received: by 2002:a17:902:900a:b0:1d4:a24c:4be0 with SMTP id a10-20020a170902900a00b001d4a24c4be0mr195779plp.133.1704357822129; Thu, 04 Jan 2024 00:43:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704357822; cv=none; d=google.com; s=arc-20160816; b=SKwsc9E6PTFf4CGBqXzpNSM5BFRS9EK3cyXsLQsGSFbEMCfhYSYhJ49uWhME0lOSij VbtKjNK1GFb2ToQIRmsSsYtsQIi51htDfq1Z5iOjVR+PFTEWOwPGdVxfJ0Wjg0+T/zmt 6tsOmcnPMmvfETPHo69VZTc5YBdbPvfSQSO4K/yLu4eWr0vrkoMAaQIIZxyvBpqLnLEj /v2qFfSAUAl6wMiPK/gMYiJryVFajUbFv1P/zLOVfOtUntiOdFS7l++dKQUbc9j4P8ze bw8lqh5DTghPybfGv4CTNYOnkiE7NhjOACzjlFsE68vSfVAy1hAkYw3OqUpFJos+rqTo 5yJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=sXGsllobW7FM1Bh/GFVmgfSyiJn/KRbyHxvKaq5XBd4=; fh=wPQP9HjC4b2j9fFVtoaE3tgh1QSkOqWUU7J9OsHbAwI=; b=fbzckmIz2+RXSH0gg4hlIILyFuD1U368+js2SWWQBmlFgB4tEdSq2YwTuc5EVPbi9d PgfhN6/ldKnY3doQ24HMyuqTss4lXteBIhwDcwG01X2S6CsoepyOx9w+Igq0NZKjoygi lxh5IKagr49XTgcrKvrP2cWJPzHFrqMqjEccDe6hx33S/ZLyfETC7dQW0aPBGMk7jWQi pabFu+bV7OFGOlMDOgLne3rl5d9OYqFnRNlzK3GZRl/G+kwdR6crP6NmG/JAC0iCP89M 3t3b2I7O8E5PFKVEXoPjaI6IQxgkLVmfwWuoVGK1V4jjt3MaNJVmAPiahoyqGhKnapnm Fw5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=KAsc15QE; spf=pass (google.com: domain of linux-kernel+bounces-16382-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-16382-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:19 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Daniel Vetter , David Airlie , Jessica Zhang , Krzysztof Kozlowski , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Rob Herring , Sam Ravnborg , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v4 5/8] dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK Date: Thu, 4 Jan 2024 09:41:45 +0100 Message-ID: <20240104084206.721824-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148707666953344 X-GMAIL-MSGID: 1787148707666953344 The patch adds the FRIDA FRD400B25025-A-CTK panel, which belongs to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij --- Changes in v4: - Put the "enum" list in alphabetical order Changes in v3: - Use "enum" to have less code changed Changes in v2: - Add a dash in front of each "items:" .../devicetree/bindings/display/panel/novatek,nt35510.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml index bc92928c805b..a4afaff483b7 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: items: - - const: hydis,hva40wv1 + - enum: + - frida,frd400b25025 + - hydis,hva40wv1 - const: novatek,nt35510 description: This indicates the panel manufacturer of the panel that is in turn using the NT35510 panel driver. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:21 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Andre Przywara , Conor Dooley , Gregory CLEMENT , Krzysztof Kozlowski , =?utf-8?q?Leonard_?= =?utf-8?q?G=C3=B6hrs?= , Maxime Coquelin , Rob Herring , Sean Nyekjaer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 6/8] ARM: dts: add stm32f769-disco-mb1225-revb03-mb1166-reva09 Date: Thu, 4 Jan 2024 09:41:46 +0100 Message-ID: <20240104084206.721824-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148725187613843 X-GMAIL-MSGID: 1787148725187613843 As reported in the section 8.3 (i. e. Board revision history) of document UM2033 (i. e. Discovery kit with STM32F769NI MCU) these are the changes related to the board revisions addressed by the patch: - Board MB1225 revision B-03: - Memory MICRON MT48LC4M32B2B5-6A replaced by ISSI IS42S32400F-6BL - Board MB1166 revision A-09: - LCD FRIDA FRD397B25009-D-CTK replaced by FRIDA FRD400B25025-A-CTK The patch only adds the DTS support for the new display which belongs to to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Change the status of panel_backlight node to "disabled" - Delete backlight property from panel0 node. arch/arm/boot/dts/st/Makefile | 1 + ...2f769-disco-mb1225-revb03-mb1166-reva09.dts | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 7892ad69b441..390dbd300a57 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32f469-disco.dtb \ stm32f746-disco.dtb \ stm32f769-disco.dtb \ + stm32f769-disco-mb1225-revb03-mb1166-reva09.dts \ stm32429i-eval.dtb \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ diff --git a/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts b/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts new file mode 100644 index 000000000000..014cac192375 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f769-disco.dts" + +&panel_backlight { + status = "disabled"; +}; + +&panel0 { + compatible = "frida,frd400b25025", "novatek,nt35510"; + vddi-supply = <&vcc_3v3>; + vdd-supply = <&vcc_3v3>; + /delete-property/backlight; + /delete-property/power-supply; +}; From patchwork Thu Jan 4 08:41:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 184942 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp5487876dyb; Thu, 4 Jan 2024 00:44:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IGGkwM+D6ucLagxX9VwmwVX2bmvStec3YGBMnDrrEnaAwTxE6V4fbv5c9W73CHi92m8m1DX X-Received: by 2002:a05:620a:379d:b0:77e:fba3:3e70 with SMTP id pi29-20020a05620a379d00b0077efba33e70mr202489qkn.57.1704357847542; Thu, 04 Jan 2024 00:44:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704357847; cv=none; d=google.com; s=arc-20160816; b=tIMqz9ZkkZ+UnJjvhUwmtCXxTKoBSjxnyfd4JZ05Q8H5o2pOpNaXUD2JdOKr6fXbCb KW1n8QlNsEJqhgtya2O4jbxQ4vPsbW0b9r9MVuiT3vPeQhR6uLhAS99RM/e2uNskV//9 9pVZTOBq4EaeldsFAu3jxfUoyVOM9xGkh10BiA7xypXSV/3TqbroYm3FwwJORRzSAxAv 8p9kvAm7tlQa4vSSKfisolAq1dsZXXKHkNRbEtyyzF9b2hmQtrsRpZzkXo2YjNFqp6f/ 7tDmYkMTDRKpT77nKhhGRcz/dymIP6XiZx3Hxe3UznrJRBL3yKjkzAifdNU4suZUbxFL MmDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mFqXTGTlYTvcm2/UHRhYI2FZvx1qxWqmcpgcCxysnrA=; fh=LxW2lm9EXaAAWVYvTkRHJEwtDqo5+5rTSh+cuVdTysw=; b=s61aEqnJucxXJ4wC4fTQsmqWPY/VRfA4qg35/2vGLLTAErvCNl+11azig9CB5oZnst cciOpayX9POuLk3xr6J243iiI4hAds5bwub5mTrg0oK5tkN3pclXaaG8ZGPI80nhvfav /814inW+fPm72YE13aPVke5EG6tFLqpri8HIaUpqZSJkOTTUn5KITt67ZqrVi93/EcLe 5beZHX6rx/sg9Wot/GXTDuNLh+nLz3ZNyHfGe/ygXQBeBDaZ1fLpiPkvEonIe4iQljh9 vJIQDlgeBcOR27Ci+KZwoYBjZHA8pqp4sXBZen0GpLUNoA0qiIhLxyiaA6Z+oUp5VWHu PM4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Yi+YaoiG; spf=pass (google.com: domain of linux-kernel+bounces-16384-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-16384-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:22 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v4 7/8] drm/panel: nt35510: move hardwired parameters to configuration Date: Thu, 4 Jan 2024 09:41:47 +0100 Message-ID: <20240104084206.721824-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148733952673319 X-GMAIL-MSGID: 1787148733952673319 This patch, preparatory for future developments, move the hardwired parameters to configuration data to allow the addition of new NT35510-based panels. Signed-off-by: Dario Binacchi Reviewed-by: Linus Walleij Tested-by: Linus Walleij --- (no changes since v2) Changes in v2: - Re-write the patch [7/8] "drm/panel: nt35510: refactor panel initialization" in the same style as the original driver in order to maintain the same structure. drivers/gpu/drm/panel/panel-novatek-nt35510.c | 140 ++++++++++++++---- 1 file changed, 115 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/drm/panel/panel-novatek-nt35510.c index d6dceb858008..ce8969f48286 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -171,6 +171,10 @@ struct nt35510_config { * timing in the display controller. */ const struct drm_display_mode mode; + /** + * @mode_flags: DSI operation mode related flags + */ + unsigned long mode_flags; /** * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V * in 0.1V steps the default is 0x05 which means 6.0V @@ -273,6 +277,100 @@ struct nt35510_config { * same layout of bytes as @vgp. */ u8 vgn[NT35510_P1_VGN_LEN]; + /** + * @dopctr: setting optional control for display + * ERR bits 0..1 in the first byte is the ERR pin output signal setting. + * 0 = Disable, ERR pin output low + * 1 = ERR pin output CRC error only + * 2 = ERR pin output ECC error only + * 3 = ERR pin output CRC and ECC error + * The default is 0. + * N565 bit 2 in the first byte is the 16-bit/pixel format selection. + * 0 = R[4:0] + G[5:3] & G[2:0] + B[4:0] + * 1 = G[2:0] + R[4:0] & B[4:0] + G[5:3] + * The default is 0. + * DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error + * reporting. + * 0 = reporting when error + * 1 = not reporting when error + * DSIM bit 4 in the first byte is the video mode data type enable + * 0 = Video mode data type disable + * 1 = Video mode data type enable + * The default is 0. + * DSIG bit 5 int the first byte is the generic r/w data type enable + * 0 = Generic r/w disable + * 1 = Generic r/w enable + * The default is 0. + * DSITE bit 6 in the first byte is TE line enable + * 0 = TE line is disabled + * 1 = TE line is enabled + * The default is 0. + * RAMKP bit 7 in the first byte is the frame memory keep/loss in + * sleep-in mode + * 0 = contents loss in sleep-in + * 1 = contents keep in sleep-in + * The default is 0. + * CRL bit 1 in the second byte is the source driver data shift + * direction selection. This bit is XOR operation with bit RSMX + * of 3600h command. + * 0 (RMSX = 0) = S1 -> S1440 + * 0 (RMSX = 1) = S1440 -> S1 + * 1 (RMSX = 0) = S1440 -> S1 + * 1 (RMSX = 1) = S1 -> S1440 + * The default is 0. + * CTB bit 2 in the second byte is the vertical scanning direction + * selection for gate control signals. This bit is XOR operation + * with bit ML of 3600h command. + * 0 (ML = 0) = Forward (top -> bottom) + * 0 (ML = 1) = Reverse (bottom -> top) + * 1 (ML = 0) = Reverse (bottom -> top) + * 1 (ML = 1) = Forward (top -> bottom) + * The default is 0. + * CRGB bit 3 in the second byte is RGB-BGR order selection. This + * bit is XOR operation with bit RGB of 3600h command. + * 0 (RGB = 0) = RGB/Normal + * 0 (RGB = 1) = BGR/RB swap + * 1 (RGB = 0) = BGR/RB swap + * 1 (RGB = 1) = RGB/Normal + * The default is 0. + * TE_PWR_SEL bit 4 in the second byte is the TE output voltage + * level selection (only valid when DSTB_SEL = 0 or DSTB_SEL = 1, + * VSEL = High and VDDI = 1.665~3.3V). + * 0 = TE output voltage level is VDDI + * 1 = TE output voltage level is VDDA + * The default is 0. + */ + u8 dopctr[NT35510_P0_DOPCTR_LEN]; + /** + * @madctl: Memory data access control + * RSMY bit 0 is flip vertical. Flips the display image top to down. + * RSMX bit 1 is flip horizontal. Flips the display image left to right. + * MH bit 2 is the horizontal refresh order. + * RGB bit 3 is the RGB-BGR order. + * 0 = RGB color sequence + * 1 = BGR color sequence + * ML bit 4 is the vertical refresh order. + * MV bit 5 is the row/column exchange. + * MX bit 6 is the column address order. + * MY bit 7 is the row address order. + */ + u8 madctl; + /** + * @sdhdtctr: source output data hold time + * 0x00..0x3F = 0..31.5us in steps of 0.5us + * The default is 0x05 = 2.5us. + */ + u8 sdhdtctr; + /** + * @gseqctr: EQ control for gate signals + * GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps + * of 0.5us. + * The default is 0x07 = 3.5us + * GREQ_XX[7:4]: time setting of EQ step for rising edge in steps + * of 0.5us. + * The default is 0x07 = 3.5us + */ + u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; /** * @sdeqctr: Source driver control settings, first byte is * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and @@ -536,46 +634,28 @@ static int nt35510_setup_display(struct nt35510 *nt) { struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); const struct nt35510_config *conf = nt->conf; - u8 dopctr[NT35510_P0_DOPCTR_LEN]; - u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN]; - /* FIXME: set up any rotation (assume none for now) */ - u8 addr_mode = NT35510_ROTATE_0_SETTING; - u8 val; int ret; - /* Enable TE, EoTP and RGB pixel format */ - dopctr[0] = NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | - NT35510_DOPCTR_0_N565; - dopctr[1] = NT35510_DOPCTR_1_CTB; ret = nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR, NT35510_P0_DOPCTR_LEN, - dopctr); + conf->dopctr); if (ret) return ret; - ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode, - sizeof(addr_mode)); + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl, + sizeof(conf->madctl)); if (ret < 0) return ret; - /* - * Source data hold time, default 0x05 = 2.5us - * 0x00..0x3F = 0 .. 31.5us in steps of 0.5us - * 0x0A = 5us - */ - val = 0x0A; - ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val, - sizeof(val)); + ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &conf->sdhdtctr, + sizeof(conf->sdhdtctr)); if (ret < 0) return ret; - /* EQ control for gate signals, 0x00 = 0 us */ - gseqctr[0] = 0x00; - gseqctr[1] = 0x00; ret = nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR, NT35510_P0_GSEQCTR_LEN, - gseqctr); + conf->gseqctr); if (ret) return ret; @@ -896,7 +976,6 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) */ dsi->hs_rate = 349440000; dsi->lp_rate = 9600000; - dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS; /* * Every new incarnation of this display must have a unique @@ -908,6 +987,8 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) return -ENODEV; } + dsi->mode_flags = nt->conf->mode_flags; + nt->supplies[0].supply = "vdd"; /* 2.3-4.8 V */ nt->supplies[1].supply = "vddi"; /* 1.65-3.3V */ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies), @@ -1030,6 +1111,7 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .vtotal = 800 + 2 + 0 + 5, /* VBP = 5 */ .flags = 0, }, + .mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS, /* 0x09: AVDD = 5.6V */ .avdd = { 0x09, 0x09, 0x09 }, /* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */ @@ -1050,6 +1132,14 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .vgp = { 0x00, 0xA3, 0x00 }, /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */ .vgn = { 0x00, 0xA3, 0x00 }, + /* Enable TE, EoTP and RGB pixel format */ + .dopctr = { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | + NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB }, + .madctl = NT35510_ROTATE_180_SETTING, + /* 0x0A: SDT = 5 us */ + .sdhdtctr = 0x0A, + /* EQ control for gate signals, 0x00 = 0 us */ + .gseqctr = { 0x00, 0x00 }, /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */ .sdeqctr = { 0x01, 0x05, 0x05, 0x05 }, /* SDVPCTR: Normal operation off color during v porch */ From patchwork Thu Jan 4 08:41:48 2024 Content-Type: text/plain; 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:24 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v4 8/8] drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK Date: Thu, 4 Jan 2024 09:41:48 +0100 Message-ID: <20240104084206.721824-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787148744713518595 X-GMAIL-MSGID: 1787148744713518595 The initialization commands are taken from the STMicroelectronics driver found at [1]. To ensure backward compatibility, flags have been added to enable gamma correction setting and display control. In other cases, registers have been set to their default values according to the specifications found in the datasheet. [1] https://github.com/STMicroelectronics/STM32CubeF7/blob/master/Drivers/BSP/Components/nt35510/ Signed-off-by: Dario Binacchi Reviewed-by: Linus Walleij --- (no changes since v2) Changes in v2: - Re-write the patch [8/8] "drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK" in the same style as the original driver. drivers/gpu/drm/panel/panel-novatek-nt35510.c | 282 ++++++++++++++++-- 1 file changed, 251 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/drm/panel/panel-novatek-nt35510.c index ce8969f48286..c85dd0d0829d 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -36,6 +36,9 @@ #include #include +#define NT35510_CMD_CORRECT_GAMMA BIT(0) +#define NT35510_CMD_CONTROL_DISPLAY BIT(1) + #define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */ #define MCS_CMD_READ_ID1 0xDA #define MCS_CMD_READ_ID2 0xDB @@ -112,18 +115,33 @@ /* AVDD and AVEE setting 3 bytes */ #define NT35510_P1_AVDD_LEN 3 #define NT35510_P1_AVEE_LEN 3 +#define NT35510_P1_VCL_LEN 3 #define NT35510_P1_VGH_LEN 3 #define NT35510_P1_VGL_LEN 3 #define NT35510_P1_VGP_LEN 3 #define NT35510_P1_VGN_LEN 3 +#define NT35510_P1_VCMOFF_LEN 2 /* BT1CTR thru BT5CTR setting 3 bytes */ #define NT35510_P1_BT1CTR_LEN 3 #define NT35510_P1_BT2CTR_LEN 3 +#define NT35510_P1_BT3CTR_LEN 3 #define NT35510_P1_BT4CTR_LEN 3 #define NT35510_P1_BT5CTR_LEN 3 /* 52 gamma parameters times two per color: positive and negative */ #define NT35510_P1_GAMMA_LEN 52 +#define NT35510_WRCTRLD_BCTRL BIT(5) +#define NT35510_WRCTRLD_A BIT(4) +#define NT35510_WRCTRLD_DD BIT(3) +#define NT35510_WRCTRLD_BL BIT(2) +#define NT35510_WRCTRLD_DB BIT(1) +#define NT35510_WRCTRLD_G BIT(0) + +#define NT35510_WRCABC_OFF 0 +#define NT35510_WRCABC_UI_MODE 1 +#define NT35510_WRCABC_STILL_MODE 2 +#define NT35510_WRCABC_MOVING_MODE 3 + /** * struct nt35510_config - the display-specific NT35510 configuration * @@ -175,6 +193,10 @@ struct nt35510_config { * @mode_flags: DSI operation mode related flags */ unsigned long mode_flags; + /** + * @cmds: enable DSI commands + */ + u32 cmds; /** * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V * in 0.1V steps the default is 0x05 which means 6.0V @@ -224,6 +246,25 @@ struct nt35510_config { * The defaults are 4 and 3 yielding 0x34 */ u8 bt2ctr[NT35510_P1_BT2CTR_LEN]; + /** + * @vcl: setting for VCL ranging from 0x00 = -2.5V to 0x11 = -4.0V + * in 1V steps, the default is 0x00 which means -2.5V + */ + u8 vcl[NT35510_P1_VCL_LEN]; + /** + * @bt3ctr: setting for boost power control for the VCL step-up + * circuit (3) + * bits 0..2 in the lower nibble controls CLCK, the booster clock + * frequency, the values are the same as for PCK in @bt1ctr. + * bits 4..5 in the upper nibble controls BTCL, the boosting + * amplification for the step-up circuit. + * 0 = Disable + * 1 = -0.5 x VDDB + * 2 = -1 x VDDB + * 3 = -2 x VDDB + * The defaults are 4 and 2 yielding 0x24 + */ + u8 bt3ctr[NT35510_P1_BT3CTR_LEN]; /** * @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V * in 1V steps, the default is 0x08 which means 15V @@ -277,6 +318,19 @@ struct nt35510_config { * same layout of bytes as @vgp. */ u8 vgn[NT35510_P1_VGN_LEN]; + /** + * @vcmoff: setting the DC VCOM offset voltage + * The first byte contains bit 8 of VCM in bit 0 and VCMOFFSEL in bit 4. + * The second byte contains bits 0..7 of VCM. + * VCMOFFSEL the common voltage offset mode. + * VCMOFFSEL 0x00 = VCOM .. 0x01 Gamma. + * The default is 0x00. + * VCM the VCOM output voltage (VCMOFFSEL = 0) or the internal register + * offset for gamma voltage (VCMOFFSEL = 1). + * VCM 0x00 = 0V/0 .. 0x118 = 3.5V/280 in steps of 12.5mV/1step + * The default is 0x00 = 0V/0. + */ + u8 vcmoff[NT35510_P1_VCMOFF_LEN]; /** * @dopctr: setting optional control for display * ERR bits 0..1 in the first byte is the ERR pin output signal setting. @@ -441,6 +495,43 @@ struct nt35510_config { * @gamma_corr_neg_b: Blue gamma correction parameters, negative */ u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN]; + /** + * @wrdisbv: write display brightness + * 0x00 value means the lowest brightness and 0xff value means + * the highest brightness. + * The default is 0x00. + */ + u8 wrdisbv; + /** + * @wrctrld: write control display + * G bit 0 selects gamma curve: 0 = Manual, 1 = Automatic + * DB bit 1 selects display brightness: 0 = Manual, 1 = Automatic + * BL bit 2 controls backlight control: 0 = Off, 1 = On + * DD bit 3 controls display dimming: 0 = Off, 1 = On + * A bit 4 controls LABC block: 0 = Off, 1 = On + * BCTRL bit 5 controls brightness block: 0 = Off, 1 = On + */ + u8 wrctrld; + /** + * @wrcabc: write content adaptive brightness control + * There is possible to use 4 different modes for content adaptive + * image functionality: + * 0: Off + * 1: User Interface Image (UI-Mode) + * 2: Still Picture Image (Still-Mode) + * 3: Moving Picture Image (Moving-Mode) + * The default is 0 + */ + u8 wrcabc; + /** + * @wrcabcmb: write CABC minimum brightness + * Set the minimum brightness value of the display for CABC + * function. + * 0x00 value means the lowest brightness for CABC and 0xff + * value means the highest brightness for CABC. + * The default is 0x00. + */ + u8 wrcabcmb; }; /** @@ -584,6 +675,16 @@ static int nt35510_setup_power(struct nt35510 *nt) nt->conf->bt2ctr); if (ret) return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVCL, + NT35510_P1_VCL_LEN, + nt->conf->vcl); + if (ret) + return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_BT3CTR, + NT35510_P1_BT3CTR_LEN, + nt->conf->bt3ctr); + if (ret) + return ret; ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGH, NT35510_P1_VGH_LEN, nt->conf->vgh); @@ -620,6 +721,12 @@ static int nt35510_setup_power(struct nt35510 *nt) if (ret) return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVCMOFF, + NT35510_P1_VCMOFF_LEN, + nt->conf->vcmoff); + if (ret) + return ret; + /* Typically 10 ms */ usleep_range(10000, 20000); @@ -799,36 +906,38 @@ static int nt35510_power_on(struct nt35510 *nt) if (ret) return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_r); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_g); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_b); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_r); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_g); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_b); - if (ret) - return ret; + if (nt->conf->cmds & NT35510_CMD_CORRECT_GAMMA) { + ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_pos_r); + if (ret) + return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_pos_g); + if (ret) + return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_pos_b); + if (ret) + return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_neg_r); + if (ret) + return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_neg_g); + if (ret) + return ret; + ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_neg_b); + if (ret) + return ret; + } /* Set up stuff in manufacturer control, page 0 */ ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, @@ -907,6 +1016,26 @@ static int nt35510_prepare(struct drm_panel *panel) /* Up to 120 ms */ usleep_range(120000, 150000); + if (nt->conf->cmds & NT35510_CMD_CONTROL_DISPLAY) { + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, + &nt->conf->wrctrld, + sizeof(nt->conf->wrctrld)); + if (ret < 0) + return ret; + + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE, + &nt->conf->wrcabc, + sizeof(nt->conf->wrcabc)); + if (ret < 0) + return ret; + + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, + &nt->conf->wrcabcmb, + sizeof(nt->conf->wrcabcmb)); + if (ret < 0) + return ret; + } + ret = mipi_dsi_dcs_set_display_on(dsi); if (ret) { dev_err(nt->dev, "failed to turn display on (%d)\n", ret); @@ -1033,7 +1162,10 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) return PTR_ERR(bl); } bl->props.max_brightness = 255; - bl->props.brightness = 255; + if (nt->conf->cmds & NT35510_CMD_CONTROL_DISPLAY) + bl->props.brightness = nt->conf->wrdisbv; + else + bl->props.brightness = 255; bl->props.power = FB_BLANK_POWERDOWN; nt->panel.backlight = bl; } @@ -1112,6 +1244,7 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .flags = 0, }, .mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS, + .cmds = NT35510_CMD_CORRECT_GAMMA, /* 0x09: AVDD = 5.6V */ .avdd = { 0x09, 0x09, 0x09 }, /* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */ @@ -1120,6 +1253,10 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .avee = { 0x09, 0x09, 0x09 }, /* 0x24: NCK = Hsync/2, BTN = -2 x VDDB */ .bt2ctr = { 0x24, 0x24, 0x24 }, + /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -2.5V */ + .vcl = { 0x00, 0x00, 0x00 }, + /* 0x24: CLCK = Hsync/2, BTN = -1 x VDDB */ + .bt3ctr = { 0x24, 0x24, 0x24 }, /* 0x05 = 12V */ .vgh = { 0x05, 0x05, 0x05 }, /* 0x24: NCKA = Hsync/2, VGH = 2 x AVDD - AVEE */ @@ -1132,6 +1269,8 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .vgp = { 0x00, 0xA3, 0x00 }, /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */ .vgn = { 0x00, 0xA3, 0x00 }, + /* VCMOFFSEL = VCOM voltage offset mode, VCM = 0V */ + .vcmoff = { 0x00, 0x00 }, /* Enable TE, EoTP and RGB pixel format */ .dopctr = { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB }, @@ -1163,7 +1302,88 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .gamma_corr_neg_b = { NT35510_GAMMA_NEG_DEFAULT }, }; +static const struct nt35510_config nt35510_frida_frd400b25025 = { + .width_mm = 52, + .height_mm = 86, + .mode = { + .clock = 23000, + .hdisplay = 480, + .hsync_start = 480 + 34, /* HFP = 34 */ + .hsync_end = 480 + 34 + 2, /* HSync = 2 */ + .htotal = 480 + 34 + 2 + 34, /* HBP = 34 */ + .vdisplay = 800, + .vsync_start = 800 + 15, /* VFP = 15 */ + .vsync_end = 800 + 15 + 12, /* VSync = 12 */ + .vtotal = 800 + 15 + 12 + 15, /* VBP = 15 */ + .flags = 0, + }, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM, + .cmds = NT35510_CMD_CONTROL_DISPLAY, + /* 0x03: AVDD = 6.2V */ + .avdd = { 0x03, 0x03, 0x03 }, + /* 0x46: PCK = 2 x Hsync, BTP = 2.5 x VDDB */ + .bt1ctr = { 0x46, 0x46, 0x46 }, + /* 0x03: AVEE = -6.2V */ + .avee = { 0x03, 0x03, 0x03 }, + /* 0x36: PCK = 2 x Hsync, BTP = 2 x VDDB */ + .bt2ctr = { 0x36, 0x36, 0x36 }, + /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -3.5V */ + .vcl = { 0x00, 0x00, 0x02 }, + /* 0x26: CLCK = 2 x Hsync, BTN = -1 x VDDB */ + .bt3ctr = { 0x26, 0x26, 0x26 }, + /* 0x09 = 16V */ + .vgh = { 0x09, 0x09, 0x09 }, + /* 0x36: HCK = 2 x Hsync, VGH = 2 x AVDD - AVEE */ + .bt4ctr = { 0x36, 0x36, 0x36 }, + /* 0x08 = -10V */ + .vgl = { 0x08, 0x08, 0x08 }, + /* 0x26: LCK = 2 x Hsync, VGL = AVDD + VCL - AVDD */ + .bt5ctr = { 0x26, 0x26, 0x26 }, + /* VGMP: 0x080 = 4.6V, VGSP = 0V */ + .vgp = { 0x00, 0x80, 0x00 }, + /* VGMP: 0x080 = 4.6V, VGSP = 0V */ + .vgn = { 0x00, 0x80, 0x00 }, + /* VCMOFFSEL = VCOM voltage offset mode, VCM = -1V */ + .vcmoff = { 0x00, 0x50 }, + .dopctr = { NT35510_DOPCTR_0_RAMKP | NT35510_DOPCTR_0_DSITE | + NT35510_DOPCTR_0_DSIG | NT35510_DOPCTR_0_DSIM | + NT35510_DOPCTR_0_EOTP | NT35510_DOPCTR_0_N565, 0 }, + .madctl = NT35510_ROTATE_180_SETTING, + /* 0x03: SDT = 1.5 us */ + .sdhdtctr = 0x03, + /* EQ control for gate signals, 0x00 = 0 us */ + .gseqctr = { 0x00, 0x00 }, + /* SDEQCTR: source driver EQ mode 2, 1 us rise time on each step */ + .sdeqctr = { 0x01, 0x02, 0x02, 0x02 }, + /* SDVPCTR: Normal operation off color during v porch */ + .sdvpctr = 0x01, + /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */ + .t1 = 0x0184, + /* VBP: vertical back porch toward the panel */ + .vbp = 0x1C, + /* VFP: vertical front porch toward the panel */ + .vfp = 0x1C, + /* PSEL: divide pixel clock 23MHz with 1 (no clock downscaling) */ + .psel = 0, + /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */ + .dpmctr12 = { 0x03, 0x00, 0x00, }, + /* write display brightness */ + .wrdisbv = 0x7f, + /* write control display */ + .wrctrld = NT35510_WRCTRLD_BCTRL | NT35510_WRCTRLD_DD | + NT35510_WRCTRLD_BL, + /* write content adaptive brightness control */ + .wrcabc = NT35510_WRCABC_STILL_MODE, + /* write CABC minimum brightness */ + .wrcabcmb = 0xff, +}; + static const struct of_device_id nt35510_of_match[] = { + { + .compatible = "frida,frd400b25025", + .data = &nt35510_frida_frd400b25025, + }, { .compatible = "hydis,hva40wv1", .data = &nt35510_hydis_hva40wv1,