From patchwork Sat Nov 12 21:29:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19258 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1434527wru; Sat, 12 Nov 2022 13:31:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf7EFzNEQwbndt8cEYC+qeQYvSRuoeHwsEvJDslvm4/pkHcrnnVEBDB63cREDDeM/GFMgK82 X-Received: by 2002:a17:906:b1c6:b0:783:5326:90e5 with SMTP id bv6-20020a170906b1c600b00783532690e5mr5969999ejb.374.1668288677790; Sat, 12 Nov 2022 13:31:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288677; cv=none; d=google.com; s=arc-20160816; b=x1+a/P5amrdPvssBzFFtTYPeVXbOTy0wXIwUjUKc75cYWREdJ67xLvxS2dsj0huUJo 6eRcP+0BfHmIgPSp4ZENX/JlzXFjNhbznUpZTr9vB84+Z4hG2yG+3oo6i8hXtG24NMIb rNb1N4fPj94kl54Gn9/saO35MJE/XZH37p85Y41lJKO8gMGLPPsCmiqdb7Cvd6hJVAQi 3+I16jIGSwoXTeRYs0ghHxQpq9laZkADP2OnLPrw8Up+URM3lolW4ZKfnJebAhW8hwP0 TRS/R13u6N8+S5wLaqZV7uOZv9+fAZ0qetRg0ulNw3bkmy5131mg1zKCAGFxForpoywd brCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=LzHdUHTecZ9iXLGEZMicojcbCnUM+cTwTJW2ChrRsek=; b=dZBKmFlmboZ6jbHvp5tvfHlH5IEQi38Us7krnkZwuf74AC6CNwhs+D6c4Xy6Zqt8I+ guWFuJ2vqEa23MTFfn9jR5almjaoroXSLt5P0oUyyMq2r1j2sV25hXSEOOLIZ+XXIgcS qPBG9PZ2GywTnum1nC5MKib5rhUwCL0742rnsNDOgo5RrQ0b7qT6213oQdVNqveFLtNn dvaPiaC6JQ6kO5UxhA7uQN5K2NEwwOp4vfLg7BQFl1wbRjzVxquaiU1aRoj2YSkAaa1g 2DKOaYIrFCJsA9i0RHhnoz/cNaIkCkHO8aUG3ED0GkVDrXTgOuTM0RvZsnQ6kVYVbxcz HwlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=DTPAazE2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id t23-20020a1709064f1700b007a7b4b41ccasi4163525eju.562.2022.11.12.13.31.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:31:17 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=DTPAazE2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D003638A8167 for ; Sat, 12 Nov 2022 21:30:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 5C209385841E for ; Sat, 12 Nov 2022 21:29:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5C209385841E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x236.google.com with SMTP id u11so8364218ljk.6 for ; Sat, 12 Nov 2022 13:29:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LzHdUHTecZ9iXLGEZMicojcbCnUM+cTwTJW2ChrRsek=; b=DTPAazE2CjXWUZOPQFt0nNNXZ0U2wtJ7fJQWWuxbRXkKpeEUurlxDfNvDgVy9sMBFQ yzyj3lRUTS1dCq6HH2RXe8gorLxT4Z8Jfe63ZH9X9K/ukHIPDL++6Oydv2+UumeYsAkK B7I7DvBl3Cde9u031KtnknKnQ2axM5QHDfoOiUk9T28P5JNy6wcRJm39ADPtPTKXnxFN CxW2xipEdtQDhTtUIUIYUsovCoCx4jkNFJfO0851Cksffmg3ZrqpNnE5zztru4Up8DqM BCbjcj9CnApt5CBd1gIv40zZhRAZ+l7yHUZRD3Fk/8khqi+7l9a2Bm8vUQ84ph7qFDHW 6Vkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LzHdUHTecZ9iXLGEZMicojcbCnUM+cTwTJW2ChrRsek=; b=k1TBReBm0YVZpXZvT1YL/hcYroDddynE0YG0/+kZLZRRqseJaP4zNUK7lPdco6eXaw imHhhe4daVBWYi6qphN1C8KoszJUpZ8To1cmdvG0qxBQa4ov4nKngL+QbTcBiWOK0pVo IY7HcSqhqa8NVvS+IQ0IlBD4fBVIC751QWu7Dk0sgd2Qxb37Xoum1+lezN/nt4pfGE5l tvSr/YSfIQoCCOorlW7XH3rHjRJ1VNbwIlNvJ/HulEGiHMxdKng+yWFVpIZqaAyDgWcu weuJK+WfOrUBIZVfVdUWA6J9LGCQYsuizj46Nu2GQaejah4QqPPBPT5K7rcdu1g0i9Ph Dr/Q== X-Gm-Message-State: ANoB5plBGpbjFduOTdTbiKLNx1yY2K+CMuQg+eUQhSczV4cQ3Ne/OBA3 pNr+iNKCv3ktw7wuCu68W5soHrv1TY+m7rry X-Received: by 2002:a2e:8e2b:0:b0:278:f572:c9ac with SMTP id r11-20020a2e8e2b000000b00278f572c9acmr1045112ljk.73.1668288588622; Sat, 12 Nov 2022 13:29:48 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:47 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 1/7] RISC-V: Recognize xventanacondops extension Date: Sat, 12 Nov 2022 22:29:37 +0100 Message-Id: <20221112212943.3068249-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327468477356764?= X-GMAIL-MSGID: =?utf-8?q?1749327468477356764?= This adds the xventanacondops extension to the option parsing and as a default for the ventana-vt1 core: gcc/Changelog: * common/config/riscv/riscv-common.cc: Recognize "xventanacondops" as part of an architecture string. * config/riscv/riscv-cores.def (RISCV_CORE): Enable "xventanacondops" by default for "ventana-vt1". * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define. (TARGET_XVENTANACONDOPS): Define. * config/riscv/riscv.opt: Add "riscv_xventanacondops". Signed-off-by: Philipp Tomsich --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 8 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4b7f777c103..6b2bdda5feb 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 25fd85b09b1..84c987626bc 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -189,4 +189,7 @@ enum stack_protector_guard { ? 0 \ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define MASK_XVENTANACONDOPS (1 << 0) +#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7c3ca48d1cc..9595078bdd4 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -233,6 +233,9 @@ int riscv_zm_subext TargetVariable int riscv_sv_subext +TargetVariable +int riscv_xventanacondops = 0 + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): From patchwork Sat Nov 12 21:29:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19259 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1434555wru; Sat, 12 Nov 2022 13:31:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf7xVGGcqMYsZ+3EBcN9PMQW66aeEuovBXyu3QJbZht2m/b5T/BNN4G3kfa7+PuUZlIdvLXz X-Received: by 2002:aa7:d74a:0:b0:461:5b75:d3df with SMTP id a10-20020aa7d74a000000b004615b75d3dfmr6581384eds.367.1668288683600; Sat, 12 Nov 2022 13:31:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288683; cv=none; d=google.com; s=arc-20160816; b=Db9cm1wSKxAlryRbECZrD8VfXrlxlnjbhWEC25VQpQBXG3ki/ZFWXZ3CNuDp0toZBK H1rmLvKUg+wjOlU3e6M0wpvGa7UIkUK+VkR+Lbv3M1IbBVC4h3wnken1eoiDFBBqAhTk 6FZfYbwZjKhurPDBuWmcm3nkTtKj8pB8jNbnmtE0A1L+G6Ojy4s2Cm+J9+b4yqSK/uLQ uB/q+buunvPskBL96QsPOpIcTmQh2XzhajMyTtpSDwWfV8QClO7BOKtQcHUXQQzqzX6b jYK7bqsX1bKZSXhTHfO3Db5/z7/Cw0n5GfBb5qJSHC616+cLIcSDu6IQxlNY5ssmtQ2c f/1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=WrK9mdL95Oa2/tF09tvi1BHk3kFvq3Nb/yaPaL7WfhM=; b=uNTbx8kyptpEYw+BQJ0L6bAH90G5t98LcIYUhPJukprpiKj4S4GlNNHIbhC8a5M4Na 2JFwHJZfeI09TWGvsZTq8HFS4vZD49icUu6oSuNt8Nj24I3AdWMTWqJR94RY45chghI+ RjNjn2fm8F3j6GLJ87M+3R2hS8O4rxho08tfjlekd4j2BXh4EmTDXFM9Ttz5LpjxKfcs LwzGVk7Zwbg/cHECKa7zQt1aIojAPVJM/khqIK2BjztZyoU2L+YOfHT69h7J9oN2vNKJ aa0vHE3jEwrshQUKz97vAvNeZTcpu2UOjHYM3wEno9QimHjAt/ht7CXPcvnaUUYrC6DE XMFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=VDmATrx1; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:49 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 2/7] RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion Date: Sat, 12 Nov 2022 22:29:38 +0100 Message-Id: <20221112212943.3068249-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327475147067340?= X-GMAIL-MSGID: =?utf-8?q?1749327475147067340?= Adds a pattern to map the output of noce_try_store_flag_mask if-conversion in the combiner onto vt.maskc; the input patterns supported are similar to the following: (set (reg/v/f:DI 75 [ ]) (and:DI (neg:DI (ne:DI (reg:DI 82) (const_int 0 [0]))) (reg/v/f:DI 75 [ ]))) This reduces dynamic instruction counts for the perlbench-workload in SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the each of the 3 workloads in the 'ref'-workload). To ensure that the combine-pass doesn't get confused about profitability, we recognize the idiom as requiring a single instruction when the XVentanaCondOps extension is present. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for vt.maskc as a single insn with TARGET_XVENTANACONDOPS. * config/riscv/riscv.md: Include xventanacondops.md. * config/riscv/xventanacondops.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ne-03.c: New test. * gcc.target/riscv/xventanacondops-ne-04.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.cc | 14 +++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/xventanacondops.md | 30 +++++++++++++++++++ .../gcc.target/riscv/xventanacondops-ne-03.c | 15 ++++++++++ .../gcc.target/riscv/xventanacondops-ne-04.c | 15 ++++++++++ 5 files changed, 75 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2a94482b8ed..1883b5b13a7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2269,6 +2269,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case AND: + /* vt.maskc/vt.maskcn for XVentanaCondOps */ + if (TARGET_XVENTANACONDOPS && mode == word_mode + && GET_CODE (XEXP (x, 0)) == NEG) + { + rtx inner = XEXP (XEXP (x, 0), 0); + + if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE) + && CONST_INT_P (XEXP (inner, 1)) + && INTVAL (XEXP (inner, 1)) == 0) + { + *total = COSTS_N_INSNS (1); + return true; + } + } /* slli.uw pattern for zba. */ if (TARGET_ZBA && TARGET_64BIT && mode == DImode && GET_CODE (XEXP (x, 0)) == ASHIFT) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1514e10dbd1..4331842b7b2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3196,3 +3196,4 @@ (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "xventanacondops.md") diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md new file mode 100644 index 00000000000..641cef0e44e --- /dev/null +++ b/gcc/config/riscv/xventanacondops.md @@ -0,0 +1,30 @@ +;; Machine description for X-Ventana-CondOps +;; Copyright (C) 2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator eq_or_ne [eq ne]) +(define_code_attr n [(eq "n") (ne "")]) + +(define_insn "*vt.maskc" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (neg:DI (eq_or_ne:DI + (match_operand:DI 1 "register_operand" "r") + (const_int 0))) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_XVENTANACONDOPS" + "vt.maskc\t%0,%2,%1") diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c new file mode 100644 index 00000000000..87cc69480ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long ne3(long long a, long long b) +{ + if (a != 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ + + diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c new file mode 100644 index 00000000000..3a04f7e52e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long ne4(long long a, long long b) +{ + if (a != 0) + return 0; + + return b; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ + + From patchwork Sat Nov 12 21:29:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19261 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1434943wru; Sat, 12 Nov 2022 13:32:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf5uOnQ/3MU1gJIcwE0J4WRFNwrZJfMhtCdeF//ry2REJ+m63d48M0ICkUWqr5SifmXyJgWZ X-Received: by 2002:a05:6402:1f0e:b0:461:4059:eb3f with SMTP id b14-20020a0564021f0e00b004614059eb3fmr6315577edb.157.1668288770116; Sat, 12 Nov 2022 13:32:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288770; cv=none; d=google.com; s=arc-20160816; b=Z2dkOFB1RbheHCIIxZTIP1kzA4Z/zouQESS7E6XjEcX8hH1kLh5DRv7I/DqZEXzmFk fzMRYe9qol4G08hsAI11T54L7Ddq2y3V4hMzb/PojT17+Hm1puOUArtTg5GQJfQF2VdZ XTHpvSaZgSrIb/m1z2eshI2sVfhbiU5dgSCbFFg9tX0+hSgBM3/tVkwh0A8XSNzV19kI HhwUmtlTl+taEnlIHRcxgNwe8UjVVrDJCobc1bEUM1pTRpfL2ulDPaSuFKNgPl84TGeZ bwsaO6URwBmN8MAexur+pves4TrPSzvVSlQvuww2ajOj7ygHnRZNycdWjBEtO/Vn/FK+ 5gLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=lISVVrsG1vq/KpiCnd9/dBiLXCDpf+gEKOUV8kvf/58=; b=f0dZ3iSmQMplY0i7fM6U0ImBQsycQf91OdOYdSAnEdVxrsEAUH+Y26FP3N6e2zH08q Yuu8pPaQ/psQf83++L3+JE7E7A3dMElhcc06JiUEeW5swZdri0y7rBfRx5Bl8wykGQ5s DrUBmdtuyoQC+L89TCm1t8h7OUXTM4P4WLX3tbHLkobCo0kUA30yiMkv5ENYFEs9UoB/ PGisRpGh1jJVcegBD9Cx1EzBJe5aoRI0xrzCh1S45Ia1w9mUXaW+kysy6Seb7+cOOu4D IJkOchxPZdHK0D86hfjKTJB4w4f5bhI0kBwwx7Fxxtwtgb+mDp+LUC4cAW1X9xZAgteN lOZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=eFqXEoxk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:50 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc Date: Sat, 12 Nov 2022 22:29:39 +0100 Message-Id: <20221112212943.3068249-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327565526809415?= X-GMAIL-MSGID: =?utf-8?q?1749327565526809415?= When if-conversion in noce_try_store_flag_mask starts the sequence off with an order-operator, our patterns for vt.maskc will receive the result of the order-operator as a register argument; consequently, they can't know that the result will be either 1 or 0. To convey this information (and make vt.maskc applicable), we wrap the result of the order-operator in a eq/ne against (const_int 0). This commit adds the split pattern to handle these cases. gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to wrap an an order-operator suitably for generating vt.maskc. Signed-off-by: Philipp Tomsich Ref vrull/gcc#157 RISC-V: Recognize 'ge'/'le' operators as 'slt'/'sgt' During if-conversion, if noce_try_store_flag_mask succeeds, we may see if (cur < next) { next = 0; } transformed into 27: r82:SI=ltu(r76:DI,r75:DI) REG_DEAD r76:DI 28: r81:SI=r82:SI^0x1 REG_DEAD r82:SI 29: r80:DI=zero_extend(r81:SI) REG_DEAD r81:SI This currently escapes the combiner, as RISC-V does not have a pattern to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in this commit, we match such cases. gcc/ChangeLog: * config/riscv/predicates.md (anyge_operator): Define. (anygt_operator): Define. (anyle_operator): Define. (anylt_operator): Define. * config/riscv/riscv.md (*sge_): Add a pattern to map 'geu' onto slt w/ reversed operands. * config/riscv/riscv.md: Helpers for ge & le. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-le-01.c: New test. * gcc.target/riscv/xventanacondops-lt-03.c: New test. --- gcc/config/riscv/predicates.md | 12 +++++ gcc/config/riscv/riscv.md | 26 +++++++++++ gcc/config/riscv/xventanacondops.md | 45 +++++++++++++++++++ .../gcc.target/riscv/xventanacondops-le-01.c | 17 +++++++ .../gcc.target/riscv/xventanacondops-lt-03.c | 17 +++++++ 5 files changed, 117 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index b368c11c930..490bff688a7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -204,6 +204,18 @@ (define_predicate "equality_operator" (match_code "eq,ne")) +(define_predicate "anyge_operator" + (match_code "ge,geu")) + +(define_predicate "anygt_operator" + (match_code "gt,gtu")) + +(define_predicate "anyle_operator" + (match_code "le,leu")) + +(define_predicate "anylt_operator" + (match_code "lt,ltu")) + (define_predicate "order_operator" (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4331842b7b2..d1f3270a3c8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2636,6 +2636,19 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] + { + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? LT : LTU, + mode, operands[3], operands[2]); + }) + (define_insn "*slt_" [(set (match_operand:GPR 0 "register_operand" "= r") (any_lt:GPR (match_operand:X 1 "register_operand" " r") @@ -2657,6 +2670,19 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] +{ + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + ;; ;; .................... ;; diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 641cef0e44e..7930ef1d837 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -28,3 +28,48 @@ (match_operand:DI 2 "register_operand" "r")))] "TARGET_XVENTANACONDOPS" "vt.maskc\t%0,%2,%1") + +;; Make order operators digestible to the vt.maskc logic by +;; wrapping their result in a comparison against (const_int 0). + +;; "a >= b" is "!(a < b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + +;; "a > b" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anygt_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) + +;; "a <= b" is "!(a > b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c new file mode 100644 index 00000000000..231b570158a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a <= b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskc\t" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c new file mode 100644 index 00000000000..b693521ba2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ + From patchwork Sat Nov 12 21:29:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19262 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1434949wru; Sat, 12 Nov 2022 13:32:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf6XU9HoulkrAbmgHMtjjqjLLEkXj9H7Wmsywm8N+xaV8Lcma+5vomvuK06BlWrUoy6uQvCY X-Received: by 2002:a05:6402:457:b0:462:750b:bced with SMTP id p23-20020a056402045700b00462750bbcedmr6170875edw.313.1668288771022; Sat, 12 Nov 2022 13:32:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288771; cv=none; d=google.com; s=arc-20160816; b=JZI4hUQl3DqvB20LssMRtmmxQqRgGIhTCkXVKOi6kTRmJov/osiw15Om73By0QGXAz urgk8yXxVCD/cBmUvYRqUN3zyML0vYOWuPjaPHkTAly6jgnoYEKnO1veqnQLDUeTHwP0 +N0sgPjtmxxx9MkNvmQkPNsQ9E7NKgXlzkfi0os7pgQxS/owi52vy/z8tNsSjd0D/WVg iNSAipLnIVIVrmmpXLsc/+b57izOEFJ+SV6xxChlXv0YksxRBArkurLooYwoBoBWxSQe vpUoWVY41753OZgOaBEPDExfQK8tjt0M5sDyQhL+5wRpzqMAUd2LG/1wmVJUzPsoWr+f DT6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=av3HGlKmOdZJOiz5VlCudPOVhItgnhX1h3QcFeonyS8=; b=XUfIOaiH3VJafD7R1YAdteO+xorvwI9RI+0ICao24MxapqH/vNulsIDZ5c3gxKJHrZ hMxfpg75BnGLClLX9595XSZvitNgVacfg6k4VIKdm+EZLlZ6Ok/G9Zoi1NXmG3lh8clX AeE5wa8U/dvub96/wUzjJMqR8ob3D65Dy7Un2rbwKxHXn8q3MW7rFBeHMZ17Zjw14HdW q92M367ppPBLU6oHxM8jK32kJ9uJXSjWJeDqnzAe6JDDs4T3uW3bXDY9HYueE7iUv84K qkXWPUNjPPwTCrH1lQHGA+n1ScSJCAZa05RnRIp5x2tWbz9jv9ERKTIEhlIGO+97Yh9F mo0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=fSiWUQky; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:51 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Date: Sat, 12 Nov 2022 22:29:40 +0100 Message-Id: <20221112212943.3068249-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327565894527491?= X-GMAIL-MSGID: =?utf-8?q?1749327565894527491?= Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combination of XVentanaCondOps and Zbs are available, this will map to the following sequences: - bexti + vt.maskc, if both Zbs and XVentanaCondOps are present - andi + vt.maskc, if only XVentanaCondOps is available and the sign-extract is operating on bits 10:0 (bit 11 can't be reached, as the immediate is sign-extended) - slli + srli + and, otherwise. gcc/ChangeLog: * config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT of a single-bit followed by AND for XVentanaCondOps. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 7930ef1d837..3e9d5833a4b 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -73,3 +73,49 @@ "TARGET_XVENTANACONDOPS" [(set (match_dup 5) (match_dup 1)) (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + +;; Users might use explicit arithmetic operations to create a mask and +;; then and it, in a sequence like +;; cond = (bits >> SHIFT) & 1; +;; mask = ~(cond - 1); +;; val &= mask; +;; which will present as a single-bit sign-extract in the combiner. +;; +;; This will give rise to any of the following cases: +;; - with Zbs and XVentanaCondOps: bexti + vt.maskc +;; - with XVentanaCondOps (but w/o Zbs): +;; - andi + vt.maskc, if the mask is representable in the immediate +;; (which requires extra care due to the immediate +;; being sign-extended) +;; - slli + srli + and +;; - otherwise: slli + srli + and + +;; With Zbb, we have bexti for all possible bits... +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_XVENTANACONDOPS && TARGET_ZBS" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))]) + +;; ...whereas RV64I only allows us access to bits 0..10 in a single andi. +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))] +{ + operands[2] = GEN_INT(1 << UINTVAL(operands[2])); +}) + From patchwork Sat Nov 12 21:29:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19263 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1435186wru; Sat, 12 Nov 2022 13:33:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf6US07dS0R7hrBkWSJB/7BEmHYz0fWRxdyTBBjqRXgDCTYDAgW2swjHnHQL2FCT3sIQLlQQ X-Received: by 2002:a17:906:28da:b0:78d:95d8:f8db with SMTP id p26-20020a17090628da00b0078d95d8f8dbmr5753672ejd.592.1668288829625; Sat, 12 Nov 2022 13:33:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288829; cv=none; d=google.com; s=arc-20160816; b=lPijjE6FEKiN5mwEZvj2/j8whwlZddEo9vWAmEgd7/a8lO0lO8La4dg3bGwtEvPzVI bi6aepURkwOVF4+pW9EAXDz5IYMSVw/Vc33swR88q9xlyuFYKrfnHwjyuIagqXr01QEW V3FEMCTUxNHYZY6kZXj5AuXgMhHktnAxA3StUNNAtEAL4TeAzc7V+Vkk8mohm0xBgke2 zFN7yNTFDUU6jUJgBWroSo7aCQqu7HIxI+x0J5t4HoGVaVCgohG41bZrZcmNJQtU5/nw 3C2El0klaQ3xeBOonflpWRmOXtI2oTxdweLTcG+JDzEZOc5E4ScGZpsp2AyURkBLU+Dr hXGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=HzM1g8L3yNLOBnPg7N/FUArqD+BUKb9iG4pB+KZCidU=; b=aggeKbchwCbkEUn1XZrSE+K91w5nd5nJaYd4gn6bQ7pm02t76XsQm51Is5VunhmZAm dmZnRcbJTXC9e4WzZqJaUVru05giLzZnGgrOK/aL61PN640KCK4ADaclKMAM72Lgv+Zw gLzW5DIomhh8h0NfkfVzB+13+ETiXSo2pvx8z6T00FGg0R/c1B/6IrQx/VsCO0JImB5+ d/qtxIfuT3bRrB9Xa6maACgNPCa91K9Gd6OMSWSN1O92Q8U45urV268W2W3+84juphBe 9ZkvYFb74obPxdYugnG8xG2x3NIQLB8e4UY2oCOZg8f6znaSy7yE4r5WAHJyIxMo0ZO+ 6vPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=MTkwBQqm; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:53 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 5/7] RISC-V: Recognize bexti in negated if-conversion Date: Sat, 12 Nov 2022 22:29:41 +0100 Message-Id: <20221112212943.3068249-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327628069362995?= X-GMAIL-MSGID: =?utf-8?q?1749327628069362995?= While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with XVentanaCondOps (andi + vt.maskc) the inverted/negated case results in andi a5,a0,1024 seqz a5,a5 neg a5,a5 and a5,a5,a1 due to how the sequence presents to the combine pass. This adds an additional splitter to reassociate the polarity reversed case into bexti + addi, if Zbs is present. Signed-off-by: Philipp Tomsich gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to reassociate "andi + seqz + neg" into "bexti + addi". --- gcc/config/riscv/xventanacondops.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 3e9d5833a4b..22b4b7d103a 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -119,3 +119,12 @@ operands[2] = GEN_INT(1 << UINTVAL(operands[2])); }) +(define_split + [(set (match_operand:X 0 "register_operand") + (neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (const_int 0))))] + "!TARGET_XVENTANACONDOPS && TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))]) From patchwork Sat Nov 12 21:29:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19260 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1434656wru; Sat, 12 Nov 2022 13:31:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf5znu7YKJdgD5PsqFP5kcxnZhxhMRcXYMqDhiEhE8y2mHyarSUEmZ5pdf9Khm+qrc9rqaH6 X-Received: by 2002:a17:906:a443:b0:7ad:9760:539d with SMTP id cb3-20020a170906a44300b007ad9760539dmr5940036ejb.369.1668288704881; Sat, 12 Nov 2022 13:31:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288704; cv=none; d=google.com; s=arc-20160816; b=AwJIpHiM4zpw4bJpGB24mbmxmnZxE+UbHJdnhWN9sTYnzxNAXLAnvcNXhLdsqMQBVd PVLbA4Gryi1EY3ieZY8fdI0uIzSVkavAVU/BATQe1hjQ3P+5FlsalpOprStVv6nBXwqs lgvOhahFJ0KmSw8gDdFaHLUvyRhiC2LEZt0rQV/4rnHKqUwpbjl/uBtvV63SOz8vYpdu 8ZZ7IMBblBIauhDKMG1JeTlOIxXmzWU9u5hi/HI0Tlnv4yw6uBJ3FYZeOFjXHp54ESw4 x2A3b5M7RJwPhA726FA8cCeyUyt73KIVtu/dI1IUaLCZwCwsjr1KittE4kVHfF7aMiK5 UbdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=p0HqPdbJ37QW4k98t0NP/xZq9bKhQMcaRRxhsftjbtI=; b=SXUyWmMpiS+qMWC8UrNxRtvIQyOALj9msLRxKFwY+FxpTeDdF5rZUnkVxncO5BPZxn IwLM3gMDbBTThK2lPRvbK1AfIf5Qmc5GTeReAiqnoiJXw7VQeBURnN4IQg2wlkeXI6Lz R7vSwsEtFvCeVSifKx0vd/oQgvVUt1uxA8LugSJvIUxoBuyQz0WMc/eRNSvGWjb2U/E7 COwvdlB2wByd1jFYwVZ4yOEDGvvtBKYUyGwEM5ltIQg2lsT7YUhW7NmvaoamvUn70ONT GSFx6D1vZDQHg+i84POeb2t/xKHAGaW4bWkT6naiF/FLuLuR1TFOmxXtJO2LTa6wcmJe 2EBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=H0VIs4bk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:54 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich , Henry Brausen Subject: [PATCH 6/7] RISC-V: Support immediates in XVentanaCondOps Date: Sat, 12 Nov 2022 22:29:42 +0100 Message-Id: <20221112212943.3068249-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327496821982281?= X-GMAIL-MSGID: =?utf-8?q?1749327496821982281?= When if-conversion encounters sequences using immediates, the sequences can't trivially map back onto vt.maskc/vt.maskcn (even if benefitial) due to vt.maskc and vt.maskcn not having immediate forms. This adds a splitter to rewrite opportunities for XVentanaCondOps that operate on an immediate by first putting the immediate into a register to enable the non-immediate vt.maskc/vt.maskcn instructions to operate on the value. Consider code, such as long func2 (long a, long c) { if (c) a = 2; else a = 5; return a; } which will be converted to func2: seqz a0,a2 neg a0,a0 andi a0,a0,3 addi a0,a0,2 ret Following this change, we generate li a0,3 vt.maskcn a0,a0,a2 addi a0,a0,2 ret This commit also introduces a simple unit test for if-conversion with immediate (literal) values as the sources for simple sets in the THEN and ELSE blocks. The test checks that Ventana's conditional mask instruction (vt.maskc) is emitted as part of the resultant branchless instruction sequence. gcc/ChangeLog: * config/riscv/xventanacondops.md: Support immediates for vt.maskc/vt.maskcn through a splitter. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ifconv-imm.c: New test. Signed-off-by: Philipp Tomsich Reviewed-by: Henry Brausen --- Ref #204 gcc/config/riscv/xventanacondops.md | 24 +++++++++++++++++-- .../riscv/xventanacondops-ifconv-imm.c | 19 +++++++++++++++ 2 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 22b4b7d103a..0e09ee91a69 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -29,6 +29,26 @@ "TARGET_XVENTANACONDOPS" "vt.maskc\t%0,%2,%1") +;; XVentanaCondOps does not have immediate forms, so we need to do extra +;; work to support these: if we encounter a vt.maskc/n with an immediate, +;; we split this into a load-immediate followed by a vt.maskc/n. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (neg:DI (match_operator:DI 1 "equality_operator" + [(match_operand:DI 2 "register_operand") + (const_int 0)])) + (match_operand:DI 3 "immediate_operand"))) + (clobber (match_operand:DI 4 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (and:DI (neg:DI (match_dup 1)) + (match_dup 4)))] +{ + /* Eliminate the clobber/temporary, if it is not needed. */ + if (!rtx_equal_p (operands[0], operands[2])) + operands[4] = operands[0]; +}) + ;; Make order operators digestible to the vt.maskc logic by ;; wrapping their result in a comparison against (const_int 0). @@ -37,7 +57,7 @@ [(set (match_operand:X 0 "register_operand") (and:X (neg:X (match_operator:X 1 "anyge_operator" [(match_operand:X 2 "register_operand") - (match_operand:X 3 "register_operand")])) + (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] "TARGET_XVENTANACONDOPS" @@ -54,7 +74,7 @@ [(set (match_operand:X 0 "register_operand") (and:X (neg:X (match_operator:X 1 "anygt_operator" [(match_operand:X 2 "register_operand") - (match_operand:X 3 "register_operand")])) + (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] "TARGET_XVENTANACONDOPS" diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c new file mode 100644 index 00000000000..0012e7b669c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* Each function below should emit a vt.maskcn instruction */ + +long +foo0 (long a, long b, long c) +{ + if (c) + a = 0; + else + a = 5; + return a; +} + +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ +/* { dg-final { scan-assembler-not "beqz\t" } } */ +/* { dg-final { scan-assembler-not "bnez\t" } } */ From patchwork Sat Nov 12 21:29:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 19264 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1435227wru; Sat, 12 Nov 2022 13:34:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf6js1rhIV80PcYM39a/zK1ToFxDevN1Ya4BDA7/SIwooMiXcYqGohEmll8n7icNzU+kYLuK X-Received: by 2002:a05:6402:d68:b0:467:b88c:f3af with SMTP id ec40-20020a0564020d6800b00467b88cf3afmr274373edb.24.1668288845881; Sat, 12 Nov 2022 13:34:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668288845; cv=none; d=google.com; s=arc-20160816; b=KX6Wo/bbf0CaoMNqFTObbK+cgztj4x0CS3b3YIgI4w3b5Z1+sL021Y6c43yvrI4EQQ fiiPKTQ+bjvkY2wamjBrn+GmdIk7UIYyLsIrowgl1ZGEiOV0ehupRGXInGzVqZHa6nZ5 z+QhygqhJqLnb8Jlxwlq9d/m8ji84NvPpdz/wXKLdhMN4W8YmETNSlc99huXT2lXYNIk 3a2IQkGbxlqGVzlay9TpoAsAm+NAcWZH1OZ5RiG1B0wF1OF/opQKznYQnFbS2nTqceOD FMiFU5xoUytbs/FI45B2dJaZ++KNLot7+bv0qXadhYBYYC+Tm/9PZ2/N9ecv2IhVi0kJ Tlsg== ARC-Message-Signature: i=1; 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:55 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 7/7] ifcvt: add if-conversion to conditional-zero instructions Date: Sat, 12 Nov 2022 22:29:43 +0100 Message-Id: <20221112212943.3068249-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327644813161898?= X-GMAIL-MSGID: =?utf-8?q?1749327644813161898?= Some architectures, as it the case on RISC-V with the proposed ZiCondOps and the vendor-defined XVentanaCondOps, define a conditional-zero instruction that is equivalent to: - the positive form: rd = (rc != 0) ? rs : 0 - the negated form: rd = (rc == 0) ? rs : 0 While noce_try_store_flag_mask will somewhat work for this case, it will generate a number of atomic RTX that will misdirect the cost calculation and may be too long (i.e., 4 RTX and more) to successfully merge at combine-time. Instead, we add two new transforms that attempt to build up what we define as the canonical form of a conditional-zero expression: (set (match_operand 0 "register_operand" "=r") (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") (const_int 0))) (match_operand 2 "register_operand" "r"))) Architectures that provide a conditional-zero are thus expected to define an instruction matching this pattern in their backend. Based on this, we support the following cases: - noce_try_condzero: a ? a : b a ? b : 0 (and then/else swapped) !a ? b : 0 (and then/else swapped) - noce_try_condzero_arith: conditional-plus, conditional-minus, conditional-and, conditional-or, conditional-xor, conditional-shift, conditional-and Given that this is hooked into the CE passes, it is less powerful than a tree-pass (e.g., it can not transform cases where an extension, such as for uint16_t operations is in either the then or else-branch together with the arithmetic) but already covers a good array of cases and triggers across SPEC CPU 2017. Adding transofmrations in a tree pass will be considered as a future improvement. gcc/ChangeLog: * ifcvt.cc (noce_emit_insn): Add prototype. (noce_emit_condzero): Helper for noce_try_condzero and noce_try_condzero_arith transforms. (noce_try_condzero): New transform. (noce_try_condzero_arith): New transform for conditional arithmetic that can be built up by exploiting that the conditional-zero instruction will inject 0, which acts as the neutral element for operations. (noce_process_if_block): Call noce_try_condzero and noce_try_condzero_arith. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-and-01.c: New test. * gcc.target/riscv/xventanacondops-and-02.c: New test. * gcc.target/riscv/xventanacondops-eq-01.c: New test. * gcc.target/riscv/xventanacondops-eq-02.c: New test. * gcc.target/riscv/xventanacondops-lt-01.c: New test. * gcc.target/riscv/xventanacondops-ne-01.c: New test. * gcc.target/riscv/xventanacondops-xor-01.c: New test. Signed-off-by: Philipp Tomsich --- gcc/ifcvt.cc | 214 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 11 + .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ 8 files changed, 311 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index eb8efb89a89..41c58876d05 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -97,6 +97,7 @@ static int find_if_case_2 (basic_block, edge, edge); static int dead_or_predicable (basic_block, basic_block, basic_block, edge, int); static void noce_emit_move_insn (rtx, rtx); +static rtx_insn *noce_emit_insn (rtx); static rtx_insn *block_has_only_trap (basic_block); static void need_cmov_or_rewire (basic_block, hash_set *, hash_map *); @@ -787,6 +788,9 @@ static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **); static int noce_try_minmax (struct noce_if_info *); static int noce_try_abs (struct noce_if_info *); static int noce_try_sign_mask (struct noce_if_info *); +static rtx noce_emit_condzero (struct noce_if_info *, rtx, bool = false); +static int noce_try_condzero (struct noce_if_info *); +static int noce_try_condzero_arith (struct noce_if_info *); /* Return the comparison code for reversed condition for IF_INFO, or UNKNOWN if reversing the condition is not possible. */ @@ -1664,6 +1668,212 @@ noce_try_addcc (struct noce_if_info *if_info) return FALSE; } +/* Helper to noce_try_condzero: cond ? a : 0. */ +static rtx +noce_emit_condzero (struct noce_if_info *if_info, rtx a, bool reverse) +{ + /* The canonical form for a conditional-zero-or-value is: + (set (match_operand 0 "register_operand" "=r") + (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") + (const_int 0))) + (match_operand 2 "register_operand" "r"))) + */ + + machine_mode opmode = GET_MODE (if_info->x); + enum rtx_code code = GET_CODE (if_info->cond); + rtx cond; + rtx op_a = XEXP (if_info->cond, 0); + rtx op_b = XEXP (if_info->cond, 1); + + /* If it is not a EQ/NE comparison against const0_rtx, canonicalize + by first synthesizing a truth-value and then building a NE + condition around it. */ + if ((code != EQ && code != NE) || XEXP (if_info->cond, 1) != const0_rtx) + { + rtx tmp = gen_reg_rtx (opmode); + + start_sequence (); + cond = gen_rtx_fmt_ee (code, opmode, op_a, op_b); + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) + { + end_sequence (); + + /* If we can't emit this pattern, try to reverse it and + invert the polarity of the second test. */ + start_sequence (); + cond = gen_rtx_fmt_ee (reverse_condition (code), opmode, op_a, op_b); + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) { + end_sequence (); + return NULL_RTX; + } + + /* We have recovered by reversing the first comparison, + so we need change the second one around as well... */ + reverse = !reverse; + } + rtx_insn *seq = get_insns (); + end_sequence (); + emit_insn (seq); + + /* Set up the second comparison that will be embedded in the + canonical conditional-zero-or-value RTX. */ + code = NE; + op_a = tmp; + op_b = const0_rtx; + } + + cond = gen_rtx_fmt_ee (reverse ? reverse_condition (code) : code, + opmode, op_a, op_b); + + /* Build (and (neg (eq_or_ne ... const0_rtx)) (reg )) */ + rtx target = gen_reg_rtx (opmode); + rtx czero = gen_rtx_AND (opmode, gen_rtx_NEG (opmode, cond), a); + noce_emit_move_insn (target, czero); + + return target; +} + +/* Use a conditional-zero instruction for "if (test) x = 0;", if available. */ +static int +noce_try_condzero (struct noce_if_info *if_info) +{ + rtx target; + rtx_insn *seq; + int reversep = 0; + rtx orig_b = NULL_RTX; + rtx cond = if_info->cond; + enum rtx_code code = GET_CODE (cond); + rtx cond_arg0 = XEXP (cond, 0); + rtx cond_arg1 = XEXP (cond, 1); + + if (!noce_simple_bbs (if_info)) + return FALSE; + + /* We may encounter the form "(a != 0) ? a : b", which can be + simplified to "a | ((a != 0) ? 0 : b)". */ + if (code == NE && cond_arg1 == const0_rtx && + REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0)) + { + orig_b = if_info->b; + if_info->b = const0_rtx; + } + + /* We may encounter the form "(a != 0) ? b : a", which can be + simplied to "(a != 0) ? b : 0". */ + if (code == EQ && cond_arg1 == const0_rtx && + REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0)) + { + /* We know that cond_arg0 is const_0, if the THEN branch is + taken... so if it is the same as if_info->b (yes, things are + backwards!), we can rewrite it with that knowledge. */ + if_info->b = const0_rtx; + } + + start_sequence (); + + if ((if_info->a == const0_rtx + && (REG_P (if_info->b) || rtx_equal_p (if_info->b, if_info->x))) + || ((reversep = (noce_reversed_cond_code (if_info) != UNKNOWN)) + && if_info->b == const0_rtx + && (REG_P (if_info->a) || rtx_equal_p (if_info->a, if_info->x)))) + { + target = noce_emit_condzero(if_info, + reversep ? if_info->a : if_info->b, + reversep); + + if (orig_b && target) + target = expand_simple_binop (GET_MODE (if_info->x), IOR, orig_b, + target, if_info->x, 0, OPTAB_WIDEN); + + if (target) + { + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc (seq, if_info->jump, + INSN_LOCATION (if_info->insn_a)); + if_info->transform_name = "noce_try_condzero"; + + return TRUE; + } + } + + end_sequence (); + + return FALSE; +} + +/* Convert "if (test) x op= a;" to a branchless sequence using the + canonical form for a conditional-zero. */ +static int +noce_try_condzero_arith (struct noce_if_info *if_info) +{ + rtx target; + rtx_insn *seq; + rtx_code op = GET_CODE (if_info->a); + const rtx arg0 = XEXP (if_info->a, 0); + const rtx arg1 = XEXP (if_info->a, 1); + + if (!noce_simple_bbs (if_info)) + return FALSE; + + /* Check for no else condition. */ + if (!rtx_equal_p (if_info->x, if_info->b)) + return FALSE; + + if (op != PLUS && op != MINUS && op != IOR && op != XOR && + op != ASHIFT && op != ASHIFTRT && op != LSHIFTRT && op != AND) + return FALSE; + + if (!rtx_equal_p (if_info->x, arg0)) + return FALSE; + + start_sequence (); + + target = noce_emit_condzero(if_info, arg1, op != AND ? true : false); + + if (target) + { + rtx op1 = if_info->x; + + if (op == AND) + { + /* Emit "tmp = x & val;" followed by "tmp |= !cond ? x : 0;" */ + op1 = expand_simple_binop (GET_MODE (if_info->x), AND, op1, + arg1, NULL_RTX, 0, OPTAB_WIDEN); + op = IOR; + } + + if (op1) + target = expand_simple_binop (GET_MODE (if_info->x), op, op1, + target, if_info->x, 0, OPTAB_WIDEN); + } + + if (target) + { + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc(seq, if_info->jump, + INSN_LOCATION(if_info->insn_a)); + if_info->transform_name = "noce_try_condzero_arith"; + + return TRUE; + } + + end_sequence (); + + return FALSE; +} + /* Convert "if (test) x = 0;" to "x &= -(test == 0);" */ static int @@ -3967,8 +4177,12 @@ noce_process_if_block (struct noce_if_info *if_info) { if (noce_try_addcc (if_info)) goto success; + if (noce_try_condzero (if_info)) + goto success; if (noce_try_store_flag_mask (if_info)) goto success; + if (noce_try_condzero_arith (if_info)) + goto success; if (HAVE_conditional_move && noce_try_cmove_arith (if_info)) goto success; diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c new file mode 100644 index 00000000000..9b26cdf0513 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long and1(long a, long b, long c, long d) +{ + if (c < d) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "slt" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c new file mode 100644 index 00000000000..66d2ec10211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +int and2(int a, int b, long c) +{ + if (c) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c new file mode 100644 index 00000000000..bc877d9e81b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq1 (long a, long b) +{ + return (a == 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c new file mode 100644 index 00000000000..28317613ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq2 (long a, long b) +{ + if (a == 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c new file mode 100644 index 00000000000..db7498801f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "vt.maskcn\" 1 } } */ +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c new file mode 100644 index 00000000000..eff1486828c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long ne1(long long a, long long b) +{ + return (a != 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c new file mode 100644 index 00000000000..43020790a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long xor1(long crc, long poly) +{ + if (crc & 1) + crc ^= poly; + + return crc; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ +/* { dg-final { scan-assembler-times "xor\t" 1 } } */