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[2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id t5-20020ac85885000000b004281f2d2b96si5770162qta.202.2024.01.02.19.10.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:10:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15116-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=V0IGfVSw; spf=pass (google.com: domain of linux-kernel+bounces-15116-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15116-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 0B2EE1C2149E for ; Wed, 3 Jan 2024 03:10:20 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 142771805D; Wed, 3 Jan 2024 03:09:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V0IGfVSw" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DE72179AA; Wed, 3 Jan 2024 03:09:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251375; x=1735787375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y4GdVfvr4r3TS2jPrXzPuftPnG1qKJX1nHclPM7uF4Y=; b=V0IGfVSwEe3nvtV02yFbK6g1F/UmV/sfTNBRDFisJc2SHdyGm90IpD5J eBwErT38LEpuUiH53lS5w+tDNTSvF/gPyfVEyf7MhMxm90DmfreZ/lEUK mUKkxeCk7bVsvr2DRyIZAkFCCFGuE5Sjonnq7qBp2Ab8hk0dGNHQQlekm tKKYtHVodc1WW/dyww+ZbkVmYE8cQQC22s9q9NAK1mcvyBuKpmt+/S/FY 5jKfZMqRbKZxT/frqRt/EHaTdxyK3Zh2OnYqOfxK9zgJivPys3nEMGQuJ 09xhev3Zx2+qbkskzeVsqumRjjbfydgHWPpbNY9138+6pip3dM5fai9PN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343118" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343118" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665910" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665910" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:30 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 01/11] x86: pmu: Remove duplicate code in pmu_init() Date: Wed, 3 Jan 2024 11:13:59 +0800 Message-Id: <20240103031409.2504051-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037137231845618 X-GMAIL-MSGID: 1787037137231845618 From: Xiong Zhang There are totally same code in pmu_init() helper, remove the duplicate code. Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi --- lib/x86/pmu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c index 0f2afd650bc9..d06e94553024 100644 --- a/lib/x86/pmu.c +++ b/lib/x86/pmu.c @@ -16,11 +16,6 @@ void pmu_init(void) pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; } - if (pmu.version > 1) { - pmu.nr_fixed_counters = cpuid_10.d & 0x1f; - pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; - } - pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; From patchwork Wed Jan 3 03:14:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184587 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806025dyb; Tue, 2 Jan 2024 19:10:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IGUcir1LSMSgH//nFoXGLzfs+k6LDaSR0kf7wjsdNH30SlD4rycaxZjgvaH4rCFN1EJp1Er X-Received: by 2002:a05:620a:47ed:b0:781:5f1e:4158 with SMTP id du45-20020a05620a47ed00b007815f1e4158mr9348706qkb.64.1704251443820; Tue, 02 Jan 2024 19:10:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251443; cv=none; d=google.com; s=arc-20160816; b=vQweI1d1ve/y6Xi406sfvD7x9NEYPQp3cyO0nJRm0XkUqxQ/Liy74Dw+x6W8AM7lI/ +0vuIYrlrUGa2WKwezfV7nuCNMMoNIUvhFUzu5B6IuoBSLV+PEPWSfNtrae739JuZceg lZ0cJRARk2UvexMPFbhkPcXUo3n3OI0YzXrs4OpZJ5tZB+QWYsL6XvZQEnFkdPJM3SWm gJ4DXLxA+S76OgVYvAipNMy2bsWnwhZPmar0H7n3KFz8wMf2Tpz2doUFAjdt2kSIRUtm wwZItXbGE2zBhJNIVX4HZO7USIhAkujSdrkuF14FoXyP3FPE27miY7OrQ2V6waBFcbzM OS8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=iHl0PqGfnstcGQ/mqAQ/a2TEN85mgw2O/ElQI70b8MI=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=qrQqaTcM0aPvxtXzqBrggG1MfAX3TJkXHpVj09v7zimYkD78cT0nCxlBPt7IoFdT+2 kFovFCYOT1klDNRlTblc70qhHGLFQreWe0rOfvdHWgJKyGhJYUtnZRfNuRUHd6eSb3aw mFAHzovs/UO5SVbZRq59YreSrnA5g4QTTAjkuU535KD8j+uhC03JtBdUGwXvnUbXf+6c 8f59td9cTY39vGVT+4SBmIUUdKXyxlF+ledyr9xoxroMuw38u3BXnFzg/ywCo8K6aIsq qdtw37uTN91BM34umTjQeR8jRNFIEVWASn/G5mXEYNnptBxrRV3PWn1SrZbTvyUkEdF5 uHmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EF1M32V1; spf=pass (google.com: domain of linux-kernel+bounces-15117-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15117-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id tz13-20020a05620a690d00b007811cc47b86si30327371qkn.617.2024.01.02.19.10.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:10:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15117-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EF1M32V1; spf=pass (google.com: domain of linux-kernel+bounces-15117-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15117-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 9A4B91C20CFB for ; Wed, 3 Jan 2024 03:10:43 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 31A0918625; Wed, 3 Jan 2024 03:09:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EF1M32V1" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53F3018050; Wed, 3 Jan 2024 03:09:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251378; x=1735787378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kfSCHGv/CfTNu74cuaUBe9OREwyoA2RBsBWS61xedrk=; b=EF1M32V11YXtj4z32ZUgMykRigj3I3rCzWbJPfOhoOXjOo3vSpJWTXQO g/UNX/fuaOwBOGLdNeaXI8CEePum9Bv5snsDEYT3pBmTitFu221rljvCl j01m1ikEgrZbVimS+4wPFEQYdCqFsHt0TH5P1UHEItBU/lyme3NiQcfNT Guf/+dNKdm2k5Qzsq92pcXuqMo/2He0hZX8SsP2ARKVoCLyfpnIC7gfRm hb3HtI+lfkwbZOpXiWWTaREzROa1M9iy3ks7Xuin+hdBNd/T2UhFitANu qUzMc1Gl5NJ3Y8jAeOcAMm2fbY4nndRc9/shuSwidT2gY71iMeXPPmeQq g==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343125" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343125" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665921" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665921" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:33 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 02/11] x86: pmu: Enlarge cnt[] length to 64 in check_counters_many() Date: Wed, 3 Jan 2024 11:14:00 +0800 Message-Id: <20240103031409.2504051-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037161913547847 X-GMAIL-MSGID: 1787037161913547847 Considering there are already 8 GP counters and 4 fixed counters on latest Intel processors, like Sapphire Rapids. The original cnt[] array length 10 is definitely not enough to cover all supported PMU counters on these new processors even through currently KVM only supports 3 fixed counters at most. This would cause out of bound memory access and may trigger false alarm on PMU counter validation It's probably more and more GP and fixed counters are introduced in the future and then directly extends the cnt[] array length to 64 once and for all. Signed-off-by: Dapeng Mi --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 0def28695c70..a13b8a8398c6 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -254,7 +254,7 @@ static void check_fixed_counters(void) static void check_counters_many(void) { - pmu_counter_t cnt[10]; + pmu_counter_t cnt[64]; int i, n; for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) { From patchwork Wed Jan 3 03:14:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184588 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806128dyb; Tue, 2 Jan 2024 19:11:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IFk4SO9v7F2roXyAZjjibv2bn4HLmUedTwQDRN/XNm4sZeXc9yylHS8CagzwGwinscyb8VT X-Received: by 2002:a05:6358:2c93:b0:174:d9c0:91a2 with SMTP id l19-20020a0563582c9300b00174d9c091a2mr14292122rwm.56.1704251470321; Tue, 02 Jan 2024 19:11:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251470; cv=none; d=google.com; s=arc-20160816; b=dkhk8ufVc8Z1sNsnLGEwbi0tKLIRz1xpa8F0oSR5apPMHPDMU91m+ESaCCCcG9qRso QVwLbTHVHqz9rLzCEE8Ckhl0sUiWt2Zht++cPIIqvQ7JKI4PVjUlq4yh3BVZRdgSwrlB fEX7nY3Lqj5JR/0YS2ruO+XWsMpYreQjH6RGMMKBSM3lKLCiGvkcDKSCZNy9GluYI+h9 ppizItGFF4bMhxtV2VQlyKGYIE47C2b9p8440CJTfhUefvDG0HcsyeBasAjjP8vSXOG/ jUo9g0F2FE6IVPd0SfqFIsZuaFy/2R27Bi/GK0o/tejOrDRBP9iiu79btjGNCIopV8EI NLCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mRVHqXiQs/mwc8unqleB0bjA0K8jN3uEiaReD9ZgM84=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=xUuO9Fai4j9Zanmtc9gxGG/37TkBGLiRetzR+3qLVjsmXKxJa/vTfboMa/0zf9plDU 09v5gyx1JJnRjsrHsExubMezkeCJtX0iPZ/ed28OVUMy0ytGu7C/YD7pOx/eb3Es0u68 2l/x0hLOcc3FBPz51b7zOaJ7gXNOt8yprTfxvvjzOiwwl3+dyizj14XwsDgiQYOBLgCN yF09MDXw/FWk9+oqjoV58oewD3XMVxQ+zhEENeXH4wJBbQqGZvhjz49A6i7K7b7JjXwe gXAoo7Zvi54ZZwHOdgZ1O5R+pMZKvMdQ8UiYfvL6mZZTguyjtPuJPAXF4mHNojExd1qk Kgow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lTK7QezD; spf=pass (google.com: domain of linux-kernel+bounces-15118-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15118-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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If so, it would cause memory access out of range. So add assert to warn this invalid case. Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index a13b8a8398c6..a42fff8d8b36 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -111,8 +111,12 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) for (i = 0; i < gp_events_size; i++) if (gp_events[i].unit_sel == (cnt->config & 0xffff)) return &gp_events[i]; - } else - return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; + } else { + int idx = cnt->ctr - MSR_CORE_PERF_FIXED_CTR0; + + assert(idx < ARRAY_SIZE(fixed_events)); + return &fixed_events[idx]; + } return (void*)0; } @@ -245,6 +249,7 @@ static void check_fixed_counters(void) }; int i; + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); for (i = 0; i < pmu.nr_fixed_counters; i++) { cnt.ctr = fixed_events[i].unit_sel; measure_one(&cnt); @@ -266,6 +271,7 @@ static void check_counters_many(void) gp_events[i % gp_events_size].unit_sel; n++; } + assert(pmu.nr_fixed_counters <= ARRAY_SIZE(fixed_events)); for (i = 0; i < pmu.nr_fixed_counters; i++) { cnt[n].ctr = fixed_events[i].unit_sel; cnt[n].config = EVNTSEL_OS | EVNTSEL_USR; From patchwork Wed Jan 3 03:14:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184589 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806222dyb; Tue, 2 Jan 2024 19:11:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHvOfDW6jmw4QoK/A76VCJfRJObdjwhe2N0+KSEx99k/DiqBynIeTMSLwZfbVjfNipUKae X-Received: by 2002:a05:6a00:1390:b0:6d9:e462:7110 with SMTP id t16-20020a056a00139000b006d9e4627110mr7219462pfg.58.1704251491201; Tue, 02 Jan 2024 19:11:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251491; cv=none; d=google.com; s=arc-20160816; b=XR0gtk3c5mbMzneP18XX+y3AjA0Uc43ON27bEXvZ/DSSOTBQttoxr7PpGbZLEq0TuB b9XhzrfNrBZoO0qbUXPnIixv2kv72+a9mfSfp3qcV++/UwLz3qR6F0sNe4NvE4j7vD6U aO/1XAJ5A2ElkUh8S1FWnvg7esgWns+i8NOCU0dlz10BvSJxGVfhVR1RO5swfRnkLsHa GpVlkyzwrEDFfNnLtFE8/RtsCYDF13aVPAN1c2vScMKO7wdbbsQPxOfrzf4ngNTLrZR+ SMwi5/esjkWkltUyxYqlmctGVoP8cGMSyEyPkt0iqUF0VsYxTdeiYNQKQCFBlMIKKn65 65Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=l/mlYdtE+bBgie5VngfPcoO872vrB0YrTZNY8+M4RXg=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=VuZjbwkw0hgniyZGN8n7u2Gb28ir1WJ3XOBfJmAqur51WAUOA0WJJJDedFBJL2tvkB z7l2i+pm1oeEnCI4J020Cz4Dlx8b6M9Yj86hZY9JV1srE1n2+MOXrXWN9Rd4nqvlGVko rUCcuUMOGgXqwqvdK29pNqoY8yJ1Nit/DwSRu5a+gVx2N5yG5zRI1iuDpI4/KELYXTvZ vfYD44RtXCGjWXLCzMUlFzWsAHoNlHulFzOZLYABem69mUqwST2sHTPXwZVDNwXBBQ2L 6Pnq1kUMurn3mdRpMizDl9cuIf+ZDT/rBcuXjKzudhFIwIZ+nOV6c5iq+kZ5EYzpYfBJ MnQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="CF/B0rch"; spf=pass (google.com: domain of linux-kernel+bounces-15119-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15119-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id fb34-20020a056a002da200b006cb852928ffsi17576804pfb.66.2024.01.02.19.11.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:11:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15119-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="CF/B0rch"; spf=pass (google.com: domain of linux-kernel+bounces-15119-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15119-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id F1F70281C01 for ; Wed, 3 Jan 2024 03:11:30 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E75A618C05; Wed, 3 Jan 2024 03:09:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CF/B0rch" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ECD318657; Wed, 3 Jan 2024 03:09:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251385; x=1735787385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFRmYSrTmp2pxalXjLvBMU2+p6f3KOk5hMuD5pr8++o=; b=CF/B0rchhttdHjZIi6qOw6XwO2OQnj34waFacoSZHU83mJQ/gg/Qo2hL dTFIs56Y2FK7+unpkQek2PAX+mrhnCada5UBYZ9VcXw+NPD2bfmTeki25 zrkpp7TvR70zI4K9fMoSDgOu1Sdt9BWUoYFSacKtXr0gi/gB48nxU3s6V dC/S5lS7JHUJwBgKZm5+GZpR0UVnvvztEf7WKxhyX5TKrDb5p1ngCJXxr fnO5AiOSQQJUYvqbRcdjz3SduqQtkak5BUsQGTVuZgvJxyWJ30NDzV2wS /661zVJaewB37m3VhBBNKc3N5VuVIWO8cKS6kUYDXWNihB4bIi7kDcV06 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343137" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343137" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665937" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665937" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:40 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 04/11] x86: pmu: Switch instructions and core cycles events sequence Date: Wed, 3 Jan 2024 11:14:02 +0800 Message-Id: <20240103031409.2504051-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037211413580952 X-GMAIL-MSGID: 1787037211413580952 When running pmu test on SPR, sometimes the following failure is reported. PMU version: 2 GP counters: 8 GP counter width: 48 Mask length: 8 Fixed counters: 3 Fixed counter width: 48 1000000 <= 55109398 <= 50000000 FAIL: Intel: core cycles-0 1000000 <= 18279571 <= 50000000 PASS: Intel: core cycles-1 1000000 <= 12238092 <= 50000000 PASS: Intel: core cycles-2 1000000 <= 7981727 <= 50000000 PASS: Intel: core cycles-3 1000000 <= 6984711 <= 50000000 PASS: Intel: core cycles-4 1000000 <= 6773673 <= 50000000 PASS: Intel: core cycles-5 1000000 <= 6697842 <= 50000000 PASS: Intel: core cycles-6 1000000 <= 6747947 <= 50000000 PASS: Intel: core cycles-7 The count of the "core cycles" on first counter would exceed the upper boundary and leads to a failure, and then the "core cycles" count would drop gradually and reach a stable state. That looks reasonable. The "core cycles" event is defined as the 1st event in xxx_gp_events[] array and it is always verified at first. when the program loop() is executed at the first time it needs to warm up the pipeline and cache, such as it has to wait for cache is filled. All these warm-up work leads to a quite large core cycles count which may exceeds the verification range. The event "instructions" instead of "core cycles" is a good choice as the warm-up event since it would always return a fixed count. Thus switch instructions and core cycles events sequence in the xxx_gp_events[] array. Signed-off-by: Dapeng Mi --- x86/pmu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index a42fff8d8b36..67ebfbe55b49 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -31,16 +31,16 @@ struct pmu_event { int min; int max; } intel_gp_events[] = { - {"core cycles", 0x003c, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, + {"core cycles", 0x003c, 1*N, 50*N}, {"ref cycles", 0x013c, 1*N, 30*N}, {"llc references", 0x4f2e, 1, 2*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, {"branch misses", 0x00c5, 0, 0.1*N}, }, amd_gp_events[] = { - {"core cycles", 0x0076, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, + {"core cycles", 0x0076, 1*N, 50*N}, {"branches", 0x00c2, 1*N, 1.1*N}, {"branch misses", 0x00c3, 0, 0.1*N}, }, fixed_events[] = { @@ -307,7 +307,7 @@ static void check_counter_overflow(void) int i; pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel /* instructions */, }; overflow_preset = measure_for_overflow(&cnt); @@ -365,11 +365,11 @@ static void check_gp_counter_cmask(void) { pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel /* instructions */, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); measure_one(&cnt); - report(cnt.count < gp_events[1].min, "cmask"); + report(cnt.count < gp_events[0].min, "cmask"); } static void do_rdpmc_fast(void *ptr) @@ -446,7 +446,7 @@ static void check_running_counter_wrmsr(void) uint64_t count; pmu_counter_t evt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel, }; report_prefix_push("running counter wrmsr"); @@ -455,7 +455,7 @@ static void check_running_counter_wrmsr(void) loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); - report(evt.count < gp_events[1].min, "cntr"); + report(evt.count < gp_events[0].min, "cntr"); /* clear status before overflow test */ if (this_cpu_has_perf_global_status()) @@ -493,7 +493,7 @@ static void check_emulated_instr(void) pmu_counter_t instr_cnt = { .ctr = MSR_GP_COUNTERx(1), /* instructions */ - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[0].unit_sel, }; report_prefix_push("emulated instruction"); From patchwork Wed Jan 3 03:14:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184590 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806333dyb; Tue, 2 Jan 2024 19:11:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfI6AIqce0mJkMIBiLKrybN1ESrbpn3K0zBZwYaMpRcobwNjPPan4TzbQeD0zw8nWWCE3k X-Received: by 2002:a05:6358:927:b0:175:4c7a:9dd6 with SMTP id r39-20020a056358092700b001754c7a9dd6mr1582990rwi.25.1704251515575; Tue, 02 Jan 2024 19:11:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251515; cv=none; d=google.com; s=arc-20160816; b=NT0r5iebb5aqZ3WyjyyRk9TdQx8MVKYZPxAMISYmZrjh2IKg+5W80D7bndhOuENpry SERcBLLABezwufo58IgRpeExklk5k1Wc+G3pu1FJI7vZ1VmYUhE0uuZvEQ6AaQqgaRls mvZ36GU7/nLc52hZSuepTmFPEG7l18fDxXyLvPgIxqquHKsmHHWok0DZ1XZ6JDOoev+3 P0McDlND8RvjyWhI0pytDUejlGHwkZqsb09jQCm4u2eGzJ7aR5Jca9uduTjmbPBURc/h 22XGkgcBASFfJDP3GLpHNPdZPPzxq5pGPuk1VkV3HGLNgvaOvzlb5bRPhKqrvJ62/tua Rvwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=R6VGL9A3SNqHbRYK2sTOkKHSSjJk4/YlVjOGXiTFjPw=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=0yuWZELdK8jhbLkIappmzaY6EJvnZIIC9o7CMjpphVx8pxQP0Wh5f1KqtMxRFQx9En IvslPIPhUMTpMk6hwLNmChf0DcxbKx/K+OeJ52agXZ2pEbHc1yJVzcRCK67YpVhaJtAy VfFOO6QOgRGmQwyEe+yciudwLENFUCmT8qMcwgZKKVmHSO0O8QcJejTmclZEfIADoISy hT1Ts5Ynb/YCAMEpsWxBswWVpj8GryrjTlIryEzZ0ApqTzl/6MYYlDmSmvYKa4qOpo6Z ekkrEnfBIEJf+9jAk69WJ6mpDWAFB6ROJUvJ8Exa3SPi67rHVX9sj6WoGaMXvANpbKsK n0ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="D5/T5KqO"; spf=pass (google.com: domain of linux-kernel+bounces-15120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15120-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id m123-20020a632681000000b005cdfee59a71si18061964pgm.897.2024.01.02.19.11.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:11:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="D5/T5KqO"; spf=pass (google.com: domain of linux-kernel+bounces-15120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15120-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 53834281BF4 for ; Wed, 3 Jan 2024 03:11:55 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 14CF018E0C; Wed, 3 Jan 2024 03:09:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="D5/T5KqO" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38A0818B19; Wed, 3 Jan 2024 03:09:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251388; x=1735787388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F3O1AGqo4cde/C+vvkiVvkwpaA4RYdhbUZBoJXM9NzA=; b=D5/T5KqO74nRN2APVdosF+a9fmAEVPzKg/rc49utwVITDt8uC22eFCeI FCH0NnYgYDE1ojSYOzoQTUfGfsgbqGp03HsLiPsh0/VmhHLKOLfNsw1s8 B94nZqRwNZjkXxnddxTbDLwre2Rja2MSBb7zTOW3ux/v4scOHPrVQDa6i 8eD9ZE3mKnke7iPpsP9SsB/c8u7mfAI90Fsk9eUjrn2vuknZQETs4/9t1 GtI04F40G7RlrQ6y1pZbXaqahefGxWjXw+ZT0wyRb7z8jgnA7WoWUGbX9 WJdz92Spb61bFQwkUaZrW/60zS8YIhgxoj8h3qmSi+MJQILFL6fDYt096 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343143" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343143" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665941" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665941" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:44 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 05/11] x86: pmu: Refine fixed_events[] names Date: Wed, 3 Jan 2024 11:14:03 +0800 Message-Id: <20240103031409.2504051-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037237215365976 X-GMAIL-MSGID: 1787037237215365976 In SDM the fixed counter is numbered from 0 but currently the fixed_events names are numbered from 1. It would cause confusion for users. So Change the fixed_events[] names to number from 0 as well and keep identical with SDM. Signed-off-by: Dapeng Mi --- x86/pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 67ebfbe55b49..a2c64a1ce95b 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -44,9 +44,9 @@ struct pmu_event { {"branches", 0x00c2, 1*N, 1.1*N}, {"branch misses", 0x00c3, 0, 0.1*N}, }, fixed_events[] = { - {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, - {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, - {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} + {"fixed 0", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, + {"fixed 1", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, + {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} }; char *buf; From patchwork Wed Jan 3 03:14:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184591 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806432dyb; Tue, 2 Jan 2024 19:12:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IEKb3nm5rU5WwIhyz+L+F9/nPog8CfvR2JUqrvNu7Ss/mJ5wnzz+e2LPx8996EbZzSA7cqu X-Received: by 2002:aa7:d6d0:0:b0:556:528d:7739 with SMTP id x16-20020aa7d6d0000000b00556528d7739mr364645edr.15.1704251542160; Tue, 02 Jan 2024 19:12:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251542; cv=none; d=google.com; s=arc-20160816; b=ORwGTYnTPAjX1Z5ni+lBGFse/65SXszECk6+tQysXwTXGr1URSuU9gEsu6CqSqJY2B MAl9oj9pyxciWREQi7EhJ4Mf3BFqlIsLVD9RzsTbgbU9fA5yvwiuTXqISesOkcLbYX61 hPED+SELIfpcaItxFJDliZHMb99gLt28hEyqjVq4nRfuclK6VQW005gIVCXDMTAyWj1x RzAygTBpWR8btPmfYw+7iJaABlSAI0ZfGmAvz4duTCmeks/ipCwNzjKPjll0UguzVoR/ CgHDW9k07/FeeazKrrBM0EbWHFyDRFtUuDLgkVC2d/X9rl0fhU0ItwD/7C46SnO58bMw RAPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OXewUFkc0t88ozLFC25+VW2dnt6DGBV/hBW3v/xF3/g=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=B6oRkfQyKZkBxU8LAehjWQVGnbXT/icN/rsZBf1FlkguOUPmILlH62kr20GrBLTB+d 0eN0qyv2qvlzIXU5+1BHADpA+Ca7WOc14S0PI1puV3trlHx5CzbQKvpLtx/tAJNv4eZI 1GWy/yZpLfedjU+f+5RY/9ZYLSFYG5ueV5l1s8Q0DLJJmdq7Zi5mfELaELF4Gw699uw+ 5KQ5hag75cFvPv/XdEVxdx2N3mFR7TDaF81P+w+mTSabcgq7m/Mn8yJzcpy/OOfwmRdu l+AhhJZrMVtMowXnbbzK6o7WrO/alhyqhg3qPnV8DyVkM9Su1eNljzhhf/17BYYRrA0h Te6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ID6m0ohx; spf=pass (google.com: domain of linux-kernel+bounces-15121-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15121-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Dapeng Mi --- x86/pmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index a2c64a1ce95b..46bed66c5c9f 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -207,8 +207,7 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { // printf("%d <= %ld <= %d\n", e->min, count, e->max); - return count >= e->min && count <= e->max; - + return count >= e->min && count <= e->max; } static bool verify_counter(pmu_counter_t *cnt) From patchwork Wed Jan 3 03:14:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184592 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806583dyb; Tue, 2 Jan 2024 19:12:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IGI8g/ZH/uulrza//2/L56cAZEYHbgLDNTd2Mb+KfrcP5Q6jj1NyDE2Lq5O67MNIfBn8XbH X-Received: by 2002:a37:de08:0:b0:781:1d86:a4bb with SMTP id h8-20020a37de08000000b007811d86a4bbmr498728qkj.67.1704251575152; Tue, 02 Jan 2024 19:12:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251575; cv=none; d=google.com; s=arc-20160816; b=vSQih4z/6VmFWE/HCJ8oeKoaxBEnhn3qVuQ7aqXRLfkK1SG8H8+LEUKYKJFq2XM6CW /MMhnAqewzsq9S7z0FnWAgjyTkw2wvpVMA/J+9PmT0CRORGCe0vLsCSveNi8+hzmxXaj E9JrfzzlzFho1OjGZYSRXQIrpV+etK8ARICWLG/sj3g+bjJqXzcwHTPCAmYcjgFovnbP ps31pcE1KI5ye2L4fT6lipte/+N54V3zKyUrVb7Epl7rHrvOkaw09p35QpFug3hnw/5Z Svd2GN6prkXy3M7ZS0LggzG11ye3+Xb2OlqsuBI6cnJwmMIoWHx9YueFnOP7z5t4YZjK ea6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QMIuvbxkv9zxsaP1ueHXynfcrJjdLWQcp2U+TmUjGIA=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=fy0xr6gmqJTo3NgZqDj5k0VLawIwjj4GSOQQEuSLL+tt4iYHm0hyUXJTlyR8I7bCKL CIHZC9wW1RolBggauIWMdD7MeWoBVjysHVAMZqtPAHWdwP8l7/ADZUlZ1smPW8MqsQ8E apyeBqHpY0syU5tAHcgRZh/31Nsl7o7r0jrHJOkYwfbph3GYJxz4TiKML2ZndXm/3Uh3 95GdZeEa/1XniKpCHOtEHag0Pg0tKmQwaTms8ZQC+che7cUth0alXr4rZ1idWxF64nU3 7iyzm038Y9bMrbYx2oouqawAYz3lCcHiwpBiGf+MvFU6r6tjN43jblzvVDFTqhwJHYjt j8LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Y1GnUrsN; spf=pass (google.com: domain of linux-kernel+bounces-15122-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15122-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id j25-20020a05620a147900b0077f62e42f75si27241556qkl.584.2024.01.02.19.12.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:12:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15122-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Y1GnUrsN; spf=pass (google.com: domain of linux-kernel+bounces-15122-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15122-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id DF2D61C22D3C for ; Wed, 3 Jan 2024 03:12:54 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7376F19441; Wed, 3 Jan 2024 03:10:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y1GnUrsN" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77C1418EA5; Wed, 3 Jan 2024 03:09:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251398; x=1735787398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VsfReKWKrlyt+Eg4eEpxHPMlAigKAPvNomF616KoHYs=; b=Y1GnUrsNkT/N+0X8jzVZYcXI2zjPjMFwVDai23ai3ay5DdE+yZCq22O8 US7AjyLN0kiK3jq/n42vjhFtCN/H85ClXy950bVcNm5rnWF7lBQmklD8X NKNXUZXUYMPnj+iDCpqFuiYfGJScGseW4eB1yMklhRqYZXUl84tG0Jwa9 uplwuPoHc5WLs9OKnCB27WM+iPA8foma/iJ+vCdfyd0eeg+awEgrhKszX NZ1IX2NwLUA9lhJAuJACeE/Zi/EKh99jTb1JP1asrfO6ZTk7+EyRiLlhF 53l977paB0QYKHzDsv/spJw7YP1aGjaA4UCOGUTzKRxDZlGmmQ8kdUF1P Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343159" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343159" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:09:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665956" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665956" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:50 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 07/11] x86: pmu: Enable and disable PMCs in loop() asm blob Date: Wed, 3 Jan 2024 11:14:05 +0800 Message-Id: <20240103031409.2504051-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037299347425038 X-GMAIL-MSGID: 1787037299347425038 Currently enabling PMCs, executing loop() and disabling PMCs are divided 3 separated functions. So there could be other instructions executed between enabling PMCS and running loop() or running loop() and disabling PMCs, e.g. if there are multiple counters enabled in measure_many() function, the instructions which enabling the 2nd and more counters would be counted in by the 1st counter. So current implementation can only verify the correctness of count by an rough range rather than a precise count even for instructions and branches events. Strictly speaking, this verification is meaningless as the test could still pass even though KVM vPMU has something wrong and reports an incorrect instructions or branches count which is in the rough range. Thus, move the PMCs enabling and disabling into the loop() asm blob and ensure only the loop asm instructions would be counted, then the instructions or branches events can be verified with an precise count instead of an rough range. Signed-off-by: Dapeng Mi --- x86/pmu.c | 83 +++++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 69 insertions(+), 14 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 46bed66c5c9f..88b89ad889b9 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -18,6 +18,20 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 +// Instrustion number of LOOP_ASM code +#define LOOP_INSTRNS 10 +#define LOOP_ASM \ + "1: mov (%1), %2; add $64, %1;\n\t" \ + "nop; nop; nop; nop; nop; nop; nop;\n\t" \ + "loop 1b;\n\t" + +#define PRECISE_LOOP_ASM \ + "wrmsr;\n\t" \ + "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ + LOOP_ASM \ + "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ + "wrmsr;\n\t" + typedef struct { uint32_t ctr; uint64_t config; @@ -54,13 +68,43 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; -static inline void loop(void) + +static inline void __loop(void) +{ + unsigned long tmp, tmp2, tmp3; + + asm volatile(LOOP_ASM + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) + : "0"(N), "1"(buf)); +} + +/* + * Enable and disable counters in a whole asm blob to ensure + * no other instructions are counted in the time slot between + * counters enabling and really LOOP_ASM code executing. + * Thus counters can verify instructions and branches events + * against precise counts instead of a rough valid count range. + */ +static inline void __precise_count_loop(u64 cntrs) { unsigned long tmp, tmp2, tmp3; + unsigned int global_ctl = pmu.msr_global_ctl; + u32 eax = cntrs & (BIT_ULL(32) - 1); + u32 edx = cntrs >> 32; - asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); + asm volatile(PRECISE_LOOP_ASM + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) + : "a"(eax), "d"(edx), "c"(global_ctl), + "0"(N), "1"(buf) + : "edi"); +} +static inline void loop(u64 cntrs) +{ + if (!this_cpu_has_perf_global_ctrl()) + __loop(); + else + __precise_count_loop(cntrs); } volatile uint64_t irq_received; @@ -159,18 +203,17 @@ static void __start_event(pmu_counter_t *evt, uint64_t count) ctrl = (ctrl & ~(0xf << shift)) | (usrospmi << shift); wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); } - global_enable(evt); apic_write(APIC_LVTPC, PMI_VECTOR); } static void start_event(pmu_counter_t *evt) { __start_event(evt, 0); + global_enable(evt); } -static void stop_event(pmu_counter_t *evt) +static void __stop_event(pmu_counter_t *evt) { - global_disable(evt); if (is_gp(evt)) { wrmsr(MSR_GP_EVENT_SELECTx(event_to_global_idx(evt)), evt->config & ~EVNTSEL_EN); @@ -182,14 +225,24 @@ static void stop_event(pmu_counter_t *evt) evt->count = rdmsr(evt->ctr); } +static void stop_event(pmu_counter_t *evt) +{ + global_disable(evt); + __stop_event(evt); +} + static noinline void measure_many(pmu_counter_t *evt, int count) { int i; + u64 cntrs = 0; + + for (i = 0; i < count; i++) { + __start_event(&evt[i], 0); + cntrs |= BIT_ULL(event_to_global_idx(&evt[i])); + } + loop(cntrs); for (i = 0; i < count; i++) - start_event(&evt[i]); - loop(); - for (i = 0; i < count; i++) - stop_event(&evt[i]); + __stop_event(&evt[i]); } static void measure_one(pmu_counter_t *evt) @@ -199,9 +252,11 @@ static void measure_one(pmu_counter_t *evt) static noinline void __measure(pmu_counter_t *evt, uint64_t count) { + u64 cntrs = BIT_ULL(event_to_global_idx(evt)); + __start_event(evt, count); - loop(); - stop_event(evt); + loop(cntrs); + __stop_event(evt); } static bool verify_event(uint64_t count, struct pmu_event *e) @@ -451,7 +506,7 @@ static void check_running_counter_wrmsr(void) report_prefix_push("running counter wrmsr"); start_event(&evt); - loop(); + __loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); report(evt.count < gp_events[0].min, "cntr"); @@ -468,7 +523,7 @@ static void check_running_counter_wrmsr(void) wrmsr(MSR_GP_COUNTERx(0), count); - loop(); + __loop(); stop_event(&evt); if (this_cpu_has_perf_global_status()) { From patchwork Wed Jan 3 03:14:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184593 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806671dyb; Tue, 2 Jan 2024 19:13:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IFTwlExDx/mz5T0xF5PBnneOpSyOSjMSGDvZh9xOOyWR9C56ka8djo9l6zkWTGoDFu2ZyIa X-Received: by 2002:ac8:7dcf:0:b0:428:1f60:5dce with SMTP id c15-20020ac87dcf000000b004281f605dcemr6446162qte.86.1704251590464; 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[2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id i16-20020ac85e50000000b00425869c1ba5si27651280qtx.617.2024.01.02.19.13.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:13:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15123-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=isNWIjuL; spf=pass (google.com: domain of linux-kernel+bounces-15123-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15123-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 32AD21C22D9C for ; Wed, 3 Jan 2024 03:13:10 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2842D19460; Wed, 3 Jan 2024 03:10:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="isNWIjuL" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51C5818EB1; Wed, 3 Jan 2024 03:09:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251400; x=1735787400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Eeaf7B8dirhUHv9DIHZWEq1uq11aLwrgRQAZz8Kd1ZM=; b=isNWIjuLYa45CXCh8QfQKbNUDDMZPGOU3xV2f7/47nAsgiAyezx9CVHe M24cg8yQRU8T1EXoclil3Hztukzti0tqAVB+li6yl8at11i3gR9rpLIVp 7wySSup3uhQBbakcLcp+YF+8XWeCdWu6b98mDHk+rmz2T5VpXFh7etjvs 4xcHOpcYDux0OJj+hQHHn80rTrcRJ05u8dzc9RPT/VLmvWvv0mt5KPq5g kB9NyuWoNhM4HoVaoiyQxg2aL+Zrm9IAPnZx64MnkwoJ3+f0DqngmsTNU R0io7lbb8ocowenlOUw1TLgWnRa8MR8rsBTmwaZhAXPVitNjFMviYaU/5 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343166" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343166" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665980" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665980" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:55 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 08/11] x86: pmu: Improve instruction and branches events verification Date: Wed, 3 Jan 2024 11:14:06 +0800 Message-Id: <20240103031409.2504051-9-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037315876352267 X-GMAIL-MSGID: 1787037315876352267 If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are moved in __precise_count_loop(). Thus, instructions and branches events can be verified against a precise count instead of a rough range. Signed-off-by: Dapeng Mi --- x86/pmu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 88b89ad889b9..b764827c1c3d 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -25,6 +25,10 @@ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" +/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ +#define PRECISE_EXTRA_INSTRNS (2 + 4) +#define PRECISE_LOOP_INSTRNS (N * LOOP_INSTRNS + PRECISE_EXTRA_INSTRNS) +#define PRECISE_LOOP_BRANCHES (N) #define PRECISE_LOOP_ASM \ "wrmsr;\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ @@ -107,6 +111,24 @@ static inline void loop(u64 cntrs) __precise_count_loop(cntrs); } +static void adjust_events_range(struct pmu_event *gp_events, int branch_idx) +{ + /* + * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are + * moved in __precise_count_loop(). Thus, instructions and branches + * events can be verified against a precise count instead of a rough + * range. + */ + if (this_cpu_has_perf_global_ctrl()) { + /* instructions event */ + gp_events[0].min = PRECISE_LOOP_INSTRNS; + gp_events[0].max = PRECISE_LOOP_INSTRNS; + /* branches event */ + gp_events[branch_idx].min = PRECISE_LOOP_BRANCHES; + gp_events[branch_idx].max = PRECISE_LOOP_BRANCHES; + } +} + volatile uint64_t irq_received; static void cnt_overflow(isr_regs_t *regs) @@ -771,6 +793,7 @@ static void check_invalid_rdpmc_gp(void) int main(int ac, char **av) { + int branch_idx; setup_vm(); handle_irq(PMI_VECTOR, cnt_overflow); buf = malloc(N*64); @@ -784,13 +807,16 @@ int main(int ac, char **av) } gp_events = (struct pmu_event *)intel_gp_events; gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); + branch_idx = 5; report_prefix_push("Intel"); set_ref_cycle_expectations(); } else { gp_events_size = sizeof(amd_gp_events)/sizeof(amd_gp_events[0]); gp_events = (struct pmu_event *)amd_gp_events; + branch_idx = 2; report_prefix_push("AMD"); } + adjust_events_range(gp_events, branch_idx); printf("PMU version: %d\n", pmu.version); printf("GP counters: %d\n", pmu.nr_gp_counters); From patchwork Wed Jan 3 03:14:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184594 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806800dyb; Tue, 2 Jan 2024 19:13:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IEPGtTAL8WNKs/+p45l+uuizjlrxBYuvn5v+0bmkgsWba509IysM4TDRNVTOSqoWXXTWLpd X-Received: by 2002:a05:6808:3011:b0:3bc:76:a657 with SMTP id ay17-20020a056808301100b003bc0076a657mr6563444oib.50.1704251613589; Tue, 02 Jan 2024 19:13:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251613; cv=none; d=google.com; s=arc-20160816; b=TtcUE6Gi5D9Qz6R5VMTkl6st3Wsr6JlOEqy55+im/BDU17mVLfZypTX0Q44gNlnP6G /0sjBUy/OSKTw/BunshjI45tAsmpzgVJ1oMa51pnqSmamcyl9E7dbyxaLsxXIdpsV/tg 5nNrQi7eoTso46hYJMEVkBgbVaOq6vHGyd3pjFTu0J9Ff7mVi3kf+fL5bv0fmibfAvWM +6wowpmanXLkX3kWUZ0Npyrc8i1n6BdAB+aPOnb0fL2SlXa4FPYqDMinjxpmSiC1csr0 gowI6kXTXegq10ageXHADX0ctYtaEHzeXdPA/TogYmP0E8hDt4RLEO6ea5ciAsim53Q/ etbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=zVqeM+Y9jv2cUvb0qeRIQuiKpXfNojG9ZtVegEOFNwE=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=aAnT1zx3ZE4qeptkSyykibbNiuSvO3+35rdp2KHpN07fgeORyeUHJPMtTvNpuLPZt6 ozzlHffSPI26coLr9NnTE/nmMgDvXKgHNuiayKVHQQ5ovrWX8aYVYKeLXnmOjS310nzz vIqgLOu27MqDzE2C8JfilpUtmeUShg3f7FZbyli6frg6iJHDQivTTU6Z6ZrX8FwFH2zt MV/tjEnuKIVBLDctsbg25k0927Q+LsSxjPmuodGX0rGzfVSmF3BgGNOYbXJHMEoPVJ2l 8r1UoPrDQ4awLvJSF7KWZyN1ODSkQndT6UZWFqJ5CD8CDkRbUGZT/fiUxNQugY7H0UOX yWtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jaOdIqdh; spf=pass (google.com: domain of linux-kernel+bounces-15124-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15124-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id bw15-20020a056a00408f00b006d9bcb822dasi14725025pfb.306.2024.01.02.19.13.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:13:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15124-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jaOdIqdh; spf=pass (google.com: domain of linux-kernel+bounces-15124-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15124-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 5C86E283F37 for ; Wed, 3 Jan 2024 03:13:33 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A0D73199C2; Wed, 3 Jan 2024 03:10:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jaOdIqdh" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD34319463; Wed, 3 Jan 2024 03:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251403; x=1735787403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ggD022wR84eJIDVFaJvrBBLC8iM3MXpUAJp9grwTY5c=; b=jaOdIqdhjNOVG2PVsQDLtksIY2ZirVCejRu9P0SlMsoTR7kOm6dhsT+7 KU/YOf3E/f+U6PrV4Ql6Eu16nka87XPqOz3HZohY0K3/lK2A0hRgqDQZ4 d4VvBP0FAtAN1Gi+vG2boC9QLau0uxuCx157YFClazgQnls7YK8Wlbmkg eY4w6tYIquyRv8wnsp+sOatbpk+P4fkS7E4tc0BvJtce1fAmGczfy7d+H 30qDqFzwpI8ul5qaVv7OhEH+KYEXi5+r/Czo0uC9N6FmVnBJ8YIlatz/U CYZJOoQJL3icoqs5dUCJ8hVIn8MdRTyifyUYCAkH2RQk9vV/a5uual5yv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343171" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343171" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729665992" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729665992" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:09:59 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 09/11] x86: pmu: Improve LLC misses event verification Date: Wed, 3 Jan 2024 11:14:07 +0800 Message-Id: <20240103031409.2504051-10-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037339550958637 X-GMAIL-MSGID: 1787037339550958637 When running pmu test on SPR, sometimes the following failure is reported. 1 <= 0 <= 1000000 FAIL: Intel: llc misses-4 Currently The LLC misses occurring only depends on probability. It's possible that there is no LLC misses happened in the whole loop(), especially along with processors have larger and larger cache size just like what we observed on SPR. Thus, add clflush instruction into the loop() asm blob and ensure once LLC miss is triggered at least. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 43 ++++++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index b764827c1c3d..8fd3db0fbf81 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -20,19 +20,21 @@ // Instrustion number of LOOP_ASM code #define LOOP_INSTRNS 10 -#define LOOP_ASM \ +#define LOOP_ASM(_clflush) \ + _clflush "\n\t" \ + "mfence;\n\t" \ "1: mov (%1), %2; add $64, %1;\n\t" \ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" -/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ -#define PRECISE_EXTRA_INSTRNS (2 + 4) +/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ +#define PRECISE_EXTRA_INSTRNS (2 + 4 + 2) #define PRECISE_LOOP_INSTRNS (N * LOOP_INSTRNS + PRECISE_EXTRA_INSTRNS) #define PRECISE_LOOP_BRANCHES (N) -#define PRECISE_LOOP_ASM \ +#define PRECISE_LOOP_ASM(_clflush) \ "wrmsr;\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ - LOOP_ASM \ + LOOP_ASM(_clflush) \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ "wrmsr;\n\t" @@ -72,14 +74,30 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; +#define _loop_asm(_clflush) \ +do { \ + asm volatile(LOOP_ASM(_clflush) \ + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) \ + : "0"(N), "1"(buf)); \ +} while (0) + +#define _precise_loop_asm(_clflush) \ +do { \ + asm volatile(PRECISE_LOOP_ASM(_clflush) \ + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ + : "a"(eax), "d"(edx), "c"(global_ctl), \ + "0"(N), "1"(buf) \ + : "edi"); \ +} while (0) static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; - asm volatile(LOOP_ASM - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) - : "0"(N), "1"(buf)); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("clflush (%1)"); + else + _loop_asm("nop"); } /* @@ -96,11 +114,10 @@ static inline void __precise_count_loop(u64 cntrs) u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - asm volatile(PRECISE_LOOP_ASM - : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) - : "a"(eax), "d"(edx), "c"(global_ctl), - "0"(N), "1"(buf) - : "edi"); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _precise_loop_asm("clflush (%1)"); + else + _precise_loop_asm("nop"); } static inline void loop(u64 cntrs) From patchwork Wed Jan 3 03:14:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184595 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4806993dyb; Tue, 2 Jan 2024 19:14:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfCq0iGosF6PV4oB21TS5nYYjL62J3n1IGsIxGeu/atkIR+QDu0UKBDQOvyjMxPcUxDiJW X-Received: by 2002:a17:903:22ca:b0:1d4:ceaf:e759 with SMTP id y10-20020a17090322ca00b001d4ceafe759mr732281plg.32.1704251655428; Tue, 02 Jan 2024 19:14:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704251655; cv=none; d=google.com; s=arc-20160816; b=ZKhdsv3ukh+21ahW/yNa0NcZzYQoxjH5L56mocvhjOSf35sF6glcXQ4DQlT/Kq93EM /CFfOGhsBmCVeFzdYWEosew1424X+53T4LFJJWD74jdG8UAaV3CMup/Wo4BpUrM5ZJal sRoukJTAdo3MxPzuzdnEnwfg3/HXxKqVQXarcOHl6TNlj1/aLItIcb/ISbpfVF/Ws6cp PhYaEc6dFOaHwUe+PePOBFup0zusYN1vYWOe31SS/6OLXJdbHwFW1MtUmMXXxPhAjfuh GXmr9H7sRi2vyDN1FwL3sFtBVX0oUtoR4kbuAP5RAmgWITSo8tqrp7SvDkoYJIWrxwnA pRFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=msJ6c3J2HW8/jr71ECpmogxTxPX9xcaVKgVRmGAQujA=; fh=YsfTl7qN5yLiZ/GhYjuBdDgWBv8FNcMbD5266uBeHkY=; b=GZ0mH8Wtx5Lx93ajUxEXrAOLuHbKfmWYFrUGEBRtlRB1BYbiyvmdJUKkuZu+eBKe8h atXwBdrtgWz/Kqgel/RND6VlBeXJY+3TFo7iUdfoL3sJLgg0bUMUzeeezh0kqgt4P1mr 9sFRNw43mS8JRDJE4qoEOSnv5sOF/6nNUrmENQtFvhplL/yTnGW6HLOxTVRANsUqwn+n avZLr6NdWN7GLtyDEuj3rC0Qa3cMLD4KBSMh/L2jOMJL5yqBDQUzviewTBxic3WDmc2+ ATT0/KKCo2pCHQC/w1jzjeNjOMxqgPsT1KFKIuiWKGYZtwpaLWZ+fTMdXzS4NlG+sl/B AE0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ixumY8aB; spf=pass (google.com: domain of linux-kernel+bounces-15125-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15125-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [147.75.48.161]) by mx.google.com with ESMTPS id t12-20020a17090a024c00b0028c17b55221si479793pje.16.2024.01.02.19.14.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:14:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15125-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ixumY8aB; spf=pass (google.com: domain of linux-kernel+bounces-15125-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15125-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id F2113B21CF2 for ; Wed, 3 Jan 2024 03:13:57 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DFB4119BCB; Wed, 3 Jan 2024 03:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ixumY8aB" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0B5199BA; Wed, 3 Jan 2024 03:10:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251407; x=1735787407; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z72wvalERNtglXdFe8pPE83KEOIKaIWcyGSzLUbOvDI=; b=ixumY8aBQOIA1m9LZaMEx+qy7AZHiVz52HmKzcu6l//fAJ2NBF/2zVBr mpERtf11o9D85zSiw6up3ufVuXrdPKgyvr+YZbr77JJiXQtpCdaWTthqZ qVFvaXE6xEd9GDKbedJETIzdxNkni54XtGHLKdB9P06E95B1v8We4TU2W 3fc2vB0nZrMucpDayYizIcgZYssl+lZAQNaFpOGDjWPiswYLhPrbmJmIq fiDx6aRfC8sNmqdmOj7eCEezwdHjMXWe83Wfh8dPaq1lhGfRAhq8MHh9J t1RUbn/0M7S+uWnlzYw+Fj8RwWRxkTg6ivKpDHIRWskGVZfftrG75ACwQ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343176" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343176" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729666003" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729666003" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:10:02 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 10/11] x86: pmu: Add IBPB indirect jump asm blob Date: Wed, 3 Jan 2024 11:14:08 +0800 Message-Id: <20240103031409.2504051-11-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037383855407190 X-GMAIL-MSGID: 1787037383855407190 Currently the lower boundary of branch misses event is set to 0. Strictly speaking 0 shouldn't be a valid count since it can't tell us if branch misses event counter works correctly or even disabled. Whereas it's also possible and reasonable that branch misses event count is 0 especailly for such simple loop() program with advanced branch predictor. To eliminate such ambiguity and make branch misses event verification more acccurately, an extra IBPB indirect jump asm blob is appended and IBPB command is leveraged to clear the branch target buffer and force to cause a branch miss for the indirect jump. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi --- x86/pmu.c | 56 +++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 8fd3db0fbf81..c8d4a0dcd362 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -27,14 +27,26 @@ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" -/*Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ -#define PRECISE_EXTRA_INSTRNS (2 + 4 + 2) +#define IBPB_JMP_INSTRNS 7 +#define IBPB_JMP_BRANCHES 1 +#define IBPB_JMP_ASM(_wrmsr) \ + "mov $1, %%eax; xor %%edx, %%edx;\n\t" \ + "mov $73, %%ecx;\n\t" \ + _wrmsr "\n\t" \ + "lea 2f, %%rax;\n\t" \ + "jmp *%%rax;\n\t" \ + "nop;\n\t" \ + "2: nop;\n\t" + +/* GLOBAL_CTRL enable + disable + clflush/mfence + IBPB_JMP */ +#define PRECISE_EXTRA_INSTRNS (2 + 4 + 2 + IBPB_JMP_INSTRNS) #define PRECISE_LOOP_INSTRNS (N * LOOP_INSTRNS + PRECISE_EXTRA_INSTRNS) -#define PRECISE_LOOP_BRANCHES (N) -#define PRECISE_LOOP_ASM(_clflush) \ +#define PRECISE_LOOP_BRANCHES (N + IBPB_JMP_BRANCHES) +#define PRECISE_LOOP_ASM(_clflush, _wrmsr) \ "wrmsr;\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ LOOP_ASM(_clflush) \ + IBPB_JMP_ASM(_wrmsr) \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ "wrmsr;\n\t" @@ -74,30 +86,42 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; -#define _loop_asm(_clflush) \ +#define _loop_asm(_clflush, _wrmsr) \ do { \ asm volatile(LOOP_ASM(_clflush) \ + IBPB_JMP_ASM(_wrmsr) \ : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) \ - : "0"(N), "1"(buf)); \ + : "0"(N), "1"(buf) \ + : "eax", "edx"); \ } while (0) -#define _precise_loop_asm(_clflush) \ +#define _precise_loop_asm(_clflush, _wrmsr) \ do { \ - asm volatile(PRECISE_LOOP_ASM(_clflush) \ + asm volatile(PRECISE_LOOP_ASM(_clflush, _wrmsr) \ : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ : "a"(eax), "d"(edx), "c"(global_ctl), \ "0"(N), "1"(buf) \ : "edi"); \ } while (0) +static int has_ibpb(void) +{ + return this_cpu_has(X86_FEATURE_SPEC_CTRL) || + this_cpu_has(X86_FEATURE_AMD_IBPB); +} + static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _loop_asm("clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _loop_asm("clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("clflush (%1)", "nop"); + else if (has_ibpb()) + _loop_asm("nop", "wrmsr"); else - _loop_asm("nop"); + _loop_asm("nop", "nop"); } /* @@ -114,10 +138,14 @@ static inline void __precise_count_loop(u64 cntrs) u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _precise_loop_asm("clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _precise_loop_asm("clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _precise_loop_asm("clflush (%1)", "nop"); + else if (has_ibpb()) + _precise_loop_asm("nop", "wrmsr"); else - _precise_loop_asm("nop"); + _precise_loop_asm("nop", "nop"); } static inline void loop(u64 cntrs) From patchwork Wed Jan 3 03:14:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 184596 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4807100dyb; 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[2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id i13-20020a056a00004d00b006d9ac93cf24si16402496pfk.14.2024.01.02.19.14.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 19:14:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15126-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="nOQoswZ/"; spf=pass (google.com: domain of linux-kernel+bounces-15126-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15126-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 75A73B216A3 for ; Wed, 3 Jan 2024 03:14:21 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1D3191A592; Wed, 3 Jan 2024 03:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nOQoswZ/" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F63E19BBA; Wed, 3 Jan 2024 03:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704251410; x=1735787410; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yfYuDnLnosyafof+2dmQ1VR1lM0gJ9NDYqFf6ZR3LWc=; b=nOQoswZ/XJISB+0KTz6EGPUrqXoJcFoyMF5bQxntCXKUB6D3hhWDbWax A0qvZqAwZZZJvjhq5ihfGx6y+fE+4DXkSLJqiIYpk4sjS7cL4oBymtVBu 5Pw0Hp3ixDHWyPDGbjMZ4MHSxeqAx2EkJEFrcD/tBXLMDJ3Jyx/R9gEiJ 9fwcCd+qwcbwrPJ4n5h4yIJIGOOsk9YDuBXVO5czEDaU7ghVDkP+TnCsx XJh4gM8X0Z7sqIvG8MQbbdHhrt+CImGPd74m13T5fH+X5+rpdd8P6Ywzg rrB4BY3lZbgPvNO5E+5jOUyHIv5D0bh5C0hYyoq9ozi/YoGxlNvN12YKu g==; X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="10343183" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="10343183" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2024 19:10:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10941"; a="729666013" X-IronPort-AV: E=Sophos;i="6.04,326,1695711600"; d="scan'208";a="729666013" Received: from dmi-pnp-i7.sh.intel.com ([10.239.159.155]) by orsmga003.jf.intel.com with ESMTP; 02 Jan 2024 19:10:06 -0800 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini , Jim Mattson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Jinrong Liang , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests Patch v3 11/11] x86: pmu: Improve branch misses event verification Date: Wed, 3 Jan 2024 11:14:09 +0800 Message-Id: <20240103031409.2504051-12-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> References: <20240103031409.2504051-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787037411406844981 X-GMAIL-MSGID: 1787037411406844981 Since IBPB command is already leveraged to force one branch miss triggering, the lower boundary of branch misses event can be set to 1 instead of 0 on IBPB supported processors. Thus the ambiguity from 0 can be eliminated. Signed-off-by: Dapeng Mi --- x86/pmu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index c8d4a0dcd362..d5c3fcfaa84c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -172,6 +172,16 @@ static void adjust_events_range(struct pmu_event *gp_events, int branch_idx) gp_events[branch_idx].min = PRECISE_LOOP_BRANCHES; gp_events[branch_idx].max = PRECISE_LOOP_BRANCHES; } + + /* + * If HW supports IBPB, one branch miss is forced to trigger by + * IBPB command. Thus overwrite the lower boundary of branch misses + * event to 1. + */ + if (has_ibpb()) { + /* branch misses event */ + gp_events[branch_idx + 1].min = 1; + } } volatile uint64_t irq_received;