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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:26 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] arm64: dts: rockchip: Enable GPU on SOQuartz CM4 Date: Sat, 12 Nov 2022 17:03:58 +0100 Message-Id: <20221112160404.70868-2-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749307062500241534?= X-GMAIL-MSGID: =?utf-8?q?1749307062500241534?= This enables the Mali-G52 GPU on the SOQuartz CM4 module. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index 5bcd4be32964..6e99f049501c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -143,6 +143,11 @@ &gmac1m0_clkinout status = "disabled"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; From patchwork Sat Nov 12 16:03:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 19215 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1333805wru; Sat, 12 Nov 2022 08:06:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf50/EqZolBPTEAFO3WEc3DLZOgCd/Xy+QYQBlBMjE5UxBoP2FBO/+wm37cL3cI2gqs+e9Y9 X-Received: by 2002:a17:906:b142:b0:7ae:2964:72dc with SMTP id bt2-20020a170906b14200b007ae296472dcmr5710665ejb.111.1668269200577; Sat, 12 Nov 2022 08:06:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668269200; cv=none; d=google.com; s=arc-20160816; b=tMn8iUPLYXRGAQrd6vkfeJubWeqhAGX0dLHJ3cKAktuYWth9U+lwqFfP3cSUEo/9JP L7Y5tV1TBq5DhD6IANevO3jVf8FmVfAfXsaAyxEpXsIc2Pqmevdil36HL/BiDNmxcyui QOTV97Vwt9uCH+Hsfma+lB7IwQqtun0SnWiDM7d8Bd31MuuXb9vgX/cd7D/kD41VE3UO xjP12ONx6bYbC0D/SzPwvBS6DX6WAJyivToQVOXX0JwTkY6LE84HVqT35dfjL87m4Qck lk2raHCva7Z+yuU6UCRRNv1jzIbNq5ldAW1l0vjVAnNiSFNpqzktTC+cgBGM1wMff4dV utGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ryja4COVOHIl0RDlGLdndcpFHG6CZ7IIZjln1Zob1wI=; b=SCQeQQ3m33jVt7yCTI2h5d01+2R50erD5zjyUHGgSGCjOyNWS256FjxetXhtz7efE4 tQB4MkiZJGRv1z5lR8toBCbFXZntn9TuXdQO1xz9xLdu7GIL/7K7v51YW18B2gHErAeL TstIoyQYzkpHyNhUBi5vDBrclgTSQuBVwG4GN14wyh8FLipkMsRss16CFyRuh+PN0iMA pIJnyrhPuxduB22lw0yI+C/60W98ULf4I4hKpvmWM1Z90yBWlwSmWuxLM4jM/nd+Qkv4 P2B0pp5D3Y7PZC8BlBLsc9wxTX4TJOksnIFcc0BHd2jknW8VJ0qHgh6u/X8EsQqA0GiM 1cLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=W2+hFqYR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:28 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] arm64: dts: rockchip: Enable video output and HDMI on SOQuartz Date: Sat, 12 Nov 2022 17:03:59 +0100 Message-Id: <20221112160404.70868-3-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749307045091346557?= X-GMAIL-MSGID: =?utf-8?q?1749307045091346557?= This patch adds and enables the necessary device tree nodes to enable video output and HDMI functionality on the SOQuartz module. Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3566-soquartz.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index 6e99f049501c..0bfb0cea7d6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -4,6 +4,7 @@ #include #include +#include #include "rk3566.dtsi" / { @@ -28,6 +29,17 @@ gmac1_clkin: external-gmac1-clock { #clock-cells = <0>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -148,6 +160,24 @@ &gpu { status = "okay"; }; +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -619,3 +649,20 @@ &usb2phy0_otg { &usb_host0_xhci { status = "disabled"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From patchwork Sat Nov 12 16:04:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 19219 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1333924wru; Sat, 12 Nov 2022 08:06:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf51ucSfrKy8XiMpXTZnQ3vG6veeoHVWqfNnGB83a43wEo53uWkeSwACvYHDYj2+5K+O83NJ X-Received: by 2002:a17:907:78c8:b0:7ae:215:2dd5 with SMTP id kv8-20020a17090778c800b007ae02152dd5mr5568995ejc.208.1668269217237; Sat, 12 Nov 2022 08:06:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668269217; cv=none; d=google.com; s=arc-20160816; b=hlIS+ix78Q7h/31KSOCZPeb4k6Sb6FtLw62MrFziwC3X69VsLhuRzjpVdn38wWNegR q1DlN/43WPBaat85tcCcr9S5aoUuice86dM070pc9NARtL4WZd3MfVySjQdB5Bt6b5ff lw6MO5WdDpG3txSf5pKCjJQflm9wukNGDfTwWWM/P54bc2cb5g/AIkFaPrTFHDT2MDvp JP+UdlUp230gmOx/OMq8BP6ecflmk2AmtgB2khg+tv9/H0syX8RYZOZrzLoLLdaddztp VP3HuthVLL9ZVMt2D/T+5oIKCRv0LzP/X1RNKNVobZDY9R2eiT6Txz+1e8IfseEGJqeW T00g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ijKNfiunV63AFU9RzYinLsQfMGW1tKqr0LKOgrxroKY=; b=xzID1JP5+3SlHoqWengteKFXdYLuVvNrZLX0qkt6mbfuZsgkuKGknJ6/7dyj4fDPzm mmC6eRiNV12ru1Mgzc7UVG0Lm/6Rw8E/79OrlvV2CC9OnRkkENLV+ZC+rex9rCuML08m MLl+ChqKgWnROgAjuXv7OtfwyIJgaTpSYmHnROnpisq9IXqNyU5ckNWNC+/YQjzsYp9X Gs+G6LlOV4uSWcpZL3zETSkF33Pvv+aPB+ruYKePhKejefCLkVagIIXp5MSZrJ1dkDDs wytEe6GQ8edV1XZExTwaQfQVI5k9BtzbiAMBjNsrc660dpyYmA9LHGnYjczgldvVf+gw yIcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=HH+eoyr8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:30 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] arm64: dts: rockchip: Enable HDMI sound on SOQuartz Date: Sat, 12 Nov 2022 17:04:00 +0100 Message-Id: <20221112160404.70868-4-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749307062712030354?= X-GMAIL-MSGID: =?utf-8?q?1749307062712030354?= This patch enables the i2s0 node on SOQuartz, which is responsible for hdmi audio, and adds an hdmi-sound node to enable said audio. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index 0bfb0cea7d6b..1b975822effa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -178,6 +178,10 @@ hdmi_out_con: endpoint { }; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -446,6 +450,10 @@ &i2c4 { status = "disabled"; }; +&i2s0_8ch { + status = "okay"; +}; + /* * i2s1_8ch is exposed on CM1 / Module1A * pin 24 - i2s1_sdi1_m1 From patchwork Sat Nov 12 16:04:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 19216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1333807wru; Sat, 12 Nov 2022 08:06:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf5FNWni1nC3Vl8INhxV7VJgDQj0DDprvmIEjXw2jxfvlwa34Oy+Fyqt6FsNC5pWaKLvtgJZ X-Received: by 2002:a17:906:27d5:b0:78d:34a:f466 with SMTP id k21-20020a17090627d500b0078d034af466mr5559633ejc.162.1668269200582; Sat, 12 Nov 2022 08:06:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668269200; cv=none; d=google.com; s=arc-20160816; b=nvnFhNaH7vps9d38FtorJ82yjtM/Og3feNFDCXQyjClG58LlPs7Ax4SS/mDMQureGX ENTrIDmIJbcKZKTNqHLSoy7yOQ68mLEqQzl3Cm/EhTBrZNaV/g/bEFGc2cT6bPBn/MM1 cid3MHn1IWNR32BoFUoHWfJMWTXcFLENs/ChM4K3/Eu0XjSsav/kUqG5fSc1HaFlLjZZ J58ujehdU0X1P60zFGOpkw2DgWIdL524QBuLhLkBe31AlU0leEXVWW0iFEFdX93kHw3j rZt7H+cJaP29Y+rPFqmfQ0ve7kfhfXcyBs6YXEvM6dC7wufVrR2vYsFjwP0YapnhgoxE cmzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oJ27VAZylslPL3euOsLLalZQXH6wtWYg2Z/Is/uMUw0=; b=eXp9SmdkaGZFDBRdUKOJyIKDw3iyWCiraFrjd603Hh8fYrc7nfor4GUlKC829wEd+t LUoYd0AyzTXfZE42yx/3CHoBWIL0kcG+Ou4qYeBcnRJe2uHuR8DZxt/1WG361VuReCTk LV0A4Z32EtqssFBgdFtOXsc5+KPpDU4vS8HIGj0wSh5ADVGH+yC2fVmrNsxwUBgNK6lt 2ePfd/CKBrhlGEPT9Cqf8xmRoyITU9xiqTN2cnCT7b+hGy1uVn2WMvss6STRyuu40vyo +ArzQkH1zj7PwlMWKGg+dOVA8yu/+ggmJFZzvcsO4non8LYDSa5pKcZs4xEOYNEwS8X2 q5ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="HKKk23/n"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:32 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO Date: Sat, 12 Nov 2022 17:04:01 +0100 Message-Id: <20221112160404.70868-5-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749307045427043735?= X-GMAIL-MSGID: =?utf-8?q?1749307045427043735?= This patch enables the PCIe2 on the CM4IO board when paired with a SOQuartz CM4 System-on-Module board. combphy2 also needs to be enabled in this case to make the PHY work for this. Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 +++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts index e00568a6be5c..263ce40770dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -30,6 +30,12 @@ vcc_5v: vcc-5v-regulator { }; }; +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + &gmac1 { status = "okay"; }; @@ -105,6 +111,11 @@ &led_work { status = "okay"; }; +&pcie2x1 { + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &rgmii_phy1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index 1b975822effa..ce7165d7f1a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -487,6 +487,12 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -512,6 +518,15 @@ diy_led_enable_h: diy-led-enable-h { }; }; + pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; From patchwork Sat Nov 12 16:04:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 19217 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1333809wru; Sat, 12 Nov 2022 08:06:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf7+Kl7gXI/wiZl9xdmSIf0/OgXsOX6uNNZH0LRGmn3tCATFeOOtpvt4AMFqAOBWFYp/QKlm X-Received: by 2002:a05:6402:500c:b0:462:7b99:d3b2 with SMTP id p12-20020a056402500c00b004627b99d3b2mr5700661eda.248.1668269200886; Sat, 12 Nov 2022 08:06:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668269200; cv=none; d=google.com; s=arc-20160816; b=vMFsATnWgUhCr6Zrus60eS85NtCBpbPgCdIdhcZtSQtSZJFHuqz/T7UwO1FaEN3Qkq Sswk/x6nSgK+XOX9zI/bDKs6fdN4/N8nFs+U/FUoR03GEmgrHq/eaRr/2l6DNxBYBZrm mweOeYTwpB2hEQBIdWQENaOijRm/gg6EpgcFxcYDga+gTWBYnXdvQuWCCctU8WaoC82I y9DzDW7t1F0M5bbZSBFh5Ba9vYdGYyDJiHfuW0u4ZCL0ALTKyjHB1/HIMchlwdDoyaVv ETHI+a1k0P73FkoBCfdq2E/YgEslogjSHnxD7RHX7b9yWKATcUWrDgLUZmdioSESJ8VF 59eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oo1e2pdndrGc6hVcKePpw8O0AQvGqHawFLLzPC17yeY=; b=cwAD9dma0pM3RMnHKzW78dWLRE22Ls0ZWuP6J/MGYXZu7+EJMqlyNYcmfxQgvXaxaI Px7rmavnh1wPl3s2+FdKTjCuugbzt55urf1SYVd7QYbYtoHRUjJm9knfEz40Sof9goEe rLRgIyLXNW8K9W+6SEDya7MAEtDE95RHcRJS25iuNByrHnUGA3zslDAjlaFz6Ew5MVRE 2LgF6rhhucFNQUKUuEjBo2lnlOFtsUf+4VTpXB4VQRrDhAwx3QZfnEy54Mw+VJBP2D+K C0jKXKEbNpuMF8CYvk7bRmCppAGn7tz0WpdMIxIfc9C/YAfZ86xKQdXwWFhgosGVZpBv J/xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=pP5PuMeT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:35 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Andrew Powers-Holmes , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] arm64: dts: rockchip: Add SOQuartz blade board Date: Sat, 12 Nov 2022 17:04:03 +0100 Message-Id: <20221112160404.70868-7-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749307065049499490?= X-GMAIL-MSGID: =?utf-8?q?1749307065049499490?= From: Andrew Powers-Holmes This adds a device tree for the PINE64 SOQuartz blade baseboard, a 1U rack mountable baseboard for the CM4 form factor with PoE support designed for the SOQuartz CM4 System-on-Module. The board takes power from either PoE or a 5V DC input, and allows for mounting an M.2 SSD. The board also features one USB 2.0 host port, one HDMI output, a 3.5mm jack for UART, and the aforementioned gigabit networking port. Signed-off-by: Andrew Powers-Holmes [rebase, squash, reword, misc fixes] Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ 2 files changed, 195 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 50942086490d..2157f086c59e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + color = ; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "disk-activity"; + status = "okay"; +}; + +&led_work { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc3v0_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v_dcin>; +};