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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:20 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Lee Jones , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/8] dt-bindings: mfd: stm32f7: Add binding definition for DSI Date: Fri, 29 Dec 2023 14:51:16 +0100 Message-ID: <20231229135154.675946-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624588205895900 X-GMAIL-MSGID: 1786624588205895900 Add binding definition for MIPI DSI Host controller. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index 8d73a9c51e2b..a4e4f9271395 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -108,6 +108,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) From patchwork Fri Dec 29 13:51:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 183908 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp2579493dyb; Fri, 29 Dec 2023 05:53:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IFWq5PKe/h/HkcsP1k9zNt4vHyhhVJB71BjJmUy64QktX3QG+NkMu3a6xK7XKaPYvQnrKm2 X-Received: by 2002:a17:907:9709:b0:a27:7dd8:5674 with SMTP id jg9-20020a170907970900b00a277dd85674mr1206165ejc.133.1703857995212; Fri, 29 Dec 2023 05:53:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703857995; cv=none; d=google.com; s=arc-20160816; b=aBLYcearChkL/D/ClDtc/Z6ajCLuxr4mVZtTGyuqKPHdVdCj6b2trmNz2vUxX8gWeM p0V3umNt3YzELWz448vJjw1jII7qBU4QTWXEQyBz4fVaRoRJnYVEhzddCpjRGaqakf9m FOUYL2oBhhdh82RlT3z6DpzRenYvrwdvq0o44WrBgX4hFER5L2StVy8ntkdzXZfViQOh DaWyYYRSMH74jBm+78i483Jaifzea2Utw2XqMpFA2w6H7LiJszgAF71aQXCOizBSTmMs +BnQjAO63PpGMLZJ5+Hl/N1+OlG3LpBwfxybtbQG0vk8KnmsbCE51lyae2bU0QBpMnQ0 3AcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Fm4SMpBWyIuCnxOoIcwbmnLaagYfOE7lx8vpRJXcsrs=; fh=vtNV/F+F7Ia7aRobr1lDLcPdFj/lrCkZfthyTDWv03U=; b=VPI0m+0oiFrDrBrHqxa1y6La9WBBQ6pYNv03Q5wwmz0x2uS5py4dMnixtQ/YhTPmgl mqzNc5v4r0nTArBWVnb5E+rKj/pK+5dzRDpHgT56krZwZRKIbzTKdbnokBgjhcS9Sslw ckKZqvr0oSoJ3AZxEfXmMLIPxTLaH3gbZmQqx8JSgOBTef1vHKdce/vW4tWF3j9vWw5o QiFLzURe+HDwVQw4oCOj5RN09aqZuk42SAjCZI9D6ui8dvJEcEnCHwj+ubWd9qTsttdp DuSfBySIs9rsRWRqMrifybv89hrwQXXygQpntDZNiuyxo9McDq8X6erYWusoD7izZKLk jDeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="EPb2A/v2"; spf=pass (google.com: domain of linux-kernel+bounces-13107-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-13107-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:21 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/8] ARM: dts: stm32: add DSI support on stm32f769 Date: Fri, 29 Dec 2023 14:51:17 +0100 Message-ID: <20231229135154.675946-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624601098518531 X-GMAIL-MSGID: 1786624601098518531 Add support for MIPI DSI Host controller. Since MIPI DSI is not available on stm32f746, the patch adds the "stm32f769.dtsi" file containing the dsi node inside. Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/st/stm32f769.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm32f769.dtsi new file mode 100644 index 000000000000..e09184f7079c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f746.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + interrupts = <98>; + clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + reset-names = "apb"; + status = "disabled"; + }; + }; +}; From patchwork Fri Dec 29 13:51:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 183909 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp2579618dyb; Fri, 29 Dec 2023 05:53:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IGP5bw0hZeczxVvZ0JL27PIeKgXiEtBVsQzHwGKmQ8hMlWzQWc3/MjoHdrePVK/Nv6PxbXd X-Received: by 2002:a05:6871:2b24:b0:204:2ac1:87ee with SMTP id dr36-20020a0568712b2400b002042ac187eemr12364453oac.105.1703858009696; Fri, 29 Dec 2023 05:53:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703858009; cv=none; d=google.com; s=arc-20160816; b=cKOcr3JVFdYCFBqKJnqdpguIMuAp6KiK9Fhjp09UNoL/1tpkKuDjbHbPoDzRDHyBpI Z7CF+CD9MBw29/GLOmfi5zi1nRPsSzRrgF9BO7SXK0I82Y84ctqVWXcBRSis56MCrIT+ we7WhKNvlSK44rVnUbEV42/kuohVrIn4A5x7+iVs4eYG3SmMbd0DvBp9zxY7ZCBrrSFe L2xeuNkoudfCNVBgGTO4lfa0XNcpBmMnm13p76TjTYEE7fBQgMdm9nZpdR0jqcAh3iNy 2fJ3oUKQlWVvdmQvt8WIM/Jk4auj/daUOJUom9oKc870OP2j4SDr8llh7yQag/eJm7r1 NxZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=e3yxjZOhlVwQSVQZtiupnCrzdwjrfUb/s2Kg9VCWikE=; fh=vtNV/F+F7Ia7aRobr1lDLcPdFj/lrCkZfthyTDWv03U=; b=ZDFEYtCi3gUaVbptEdp3fN3nzlEt3wZp4AAz8iM2rNP/eLk/2Vujkc1Py0yE8fTBAH ScvFWNQp1Jaru937xvcqLEJR6GpPcus3WH86ObsMBoJWE4C1LHQBwznKYNZ+Bs6ClgiC RlnFGvnKLbA1MuboHV2IzsFBqEGHKLCFvlWb5LuMG/AcU5Pr5EC4QMQYx5lTx21DIy2s HYugf0WhX+gL4uVkIBf8n9Jp4vnm2gAKtMCBa8QIv37MTjZjBjLHqf3i4mRKjhJHwECe MYWs3xTUdcVlVVqQCFHCgo4TdnoKORWZagFTcfCPTwcCNxk2GW0tdoeSzKeM2dyZosXH TPjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GE7g0qCH; spf=pass (google.com: domain of linux-kernel+bounces-13108-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-13108-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:22 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/8] ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco Date: Fri, 29 Dec 2023 14:51:18 +0100 Message-ID: <20231229135154.675946-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624616446907786 X-GMAIL-MSGID: 1786624616446907786 In the schematics of document UM2033, the power supply for the micro SD card is the same 3v3 voltage that is used to power other devices on the board. By generalizing the name of the voltage regulator, it can be referenced by other nodes in the device tree without creating misunderstandings. This patch is preparatory for future developments. Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/st/stm32f769-disco.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 5d12ae25b327..8632bd866272 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -92,9 +92,9 @@ usbotg_hs_phy: usb-phy { clock-names = "main_clk"; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc_3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -128,7 +128,7 @@ &rtc { &sdio2 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; pinctrl-names = "default", "opendrain", "sleep"; From patchwork Fri Dec 29 13:51:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 183910 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp2579801dyb; Fri, 29 Dec 2023 05:53:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IE+7MH/jXcRySCyaQl/vnd/ODRgerxsF/LcMuSFiAoLSUMozitNDAjzP361op8zIBpTE6j6 X-Received: by 2002:aa7:81cc:0:b0:6da:42da:c09c with SMTP id c12-20020aa781cc000000b006da42dac09cmr377721pfn.30.1703858031169; Fri, 29 Dec 2023 05:53:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703858031; cv=none; d=google.com; s=arc-20160816; b=S3pFkxZuOm+6KSDWdxnwd4im2jBVEuQoG2IgDZYPiJYsMOD2jsBEMfj83sh/bsRaB4 Fudm/Qwa4wjhpRGnHm3koxdnIwuuuWOiCb3er1376N8bABlhBDXIOmB/5DXygl0wNCzi B37kMJV64rnw2fMdJ9qX/VZd5h18IaO4mS3WUBUoYwU2HRXyK5fEq310DD+gpu+9AcB6 MZx5PqBrmbFrGXN8G0dwb7NwoD3tw9GO++meZQQRaISE/zoQSDLWE2Qv0o89UdqC30mE FE09NV17Ry+1G9fqH8Uz43AVSWS9ggWICtrzByPmv6PEe64PA3dtcIwlmEU2sd2ta5XY ugBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Gga6jIGQV6Uokv7TaAQoZWe7KKBaoCfGdy4Mk3xFQ7I=; fh=vtNV/F+F7Ia7aRobr1lDLcPdFj/lrCkZfthyTDWv03U=; b=iyHympasARfJCWjMRMQIMQAEAwtihjlj+V65leC6OFj5UtbtTbTrXYiaM4OTquovvV zo3eD6EQF0RirhUttnQjkdhCm/rBCAZXVqR8DekTwRe70nuls0rxdlExnMa3QHAkyOYo 68sZXjDezqwd2Cmf1u1olJrfoxXzZ5e5dqJuuuWw6/W/7o3tMji+Qzi4RmnB4WEc2xJS 8P472S1/gfcgrGMZ1UIGk7wncFJ3eZnLHU02WgFaolDPHD1Z1Wv/h++KiTYGFsswpncx O4SSWLAJnElTfQgwa0M9Wr2wc6F9zL8OC5tLXdcOw0nDOR8QwHPQVogx0seghPYA67VM GXJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=cleI8mmO; spf=pass (google.com: domain of linux-kernel+bounces-13109-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-13109-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:23 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/8] ARM: dts: stm32: add display support on stm32f769-disco Date: Fri, 29 Dec 2023 14:51:19 +0100 Message-ID: <20231229135154.675946-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624639040046166 X-GMAIL-MSGID: 1786624639040046166 The patch adds display support on the stm32f769-disco board. Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/st/stm32f769-disco.dts | 72 +++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 8632bd866272..d1eb5f9c78bf 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -41,7 +41,7 @@ */ /dts-v1/; -#include "stm32f746.dtsi" +#include "stm32f769.dtsi" #include "stm32f769-pinctrl.dtsi" #include #include @@ -60,6 +60,19 @@ memory@c0000000 { reg = <0xC0000000 0x1000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,dma { + compatible = "shared-dma-pool"; + linux,dma-default; + no-map; + size = <0x100000>; + }; + }; + aliases { serial0 = &usart1; }; @@ -85,6 +98,13 @@ button-0 { }; }; + panel_backlight: panel-backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 14 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -114,6 +134,46 @@ &clk_hse { clock-frequency = <25000000>; }; +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel0: panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>; + power-supply = <&vcc_3v3>; + backlight = <&panel_backlight>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -122,6 +182,16 @@ &i2c1 { status = "okay"; }; +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + remote-endpoint = <&dsi_in>; + }; + }; +}; + &rtc { status = "okay"; }; From patchwork Fri Dec 29 13:51:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 183911 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp2579838dyb; Fri, 29 Dec 2023 05:53:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IHIR6p8QYJ/2xgKv49bT/xOxNZgUC2NPfyobek39kTmPCug833mR+sknCcBfC6rCQyVl6AL X-Received: by 2002:aa7:8658:0:b0:6d9:bbd6:49ed with SMTP id a24-20020aa78658000000b006d9bbd649edmr8081046pfo.26.1703858036682; Fri, 29 Dec 2023 05:53:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703858036; cv=none; d=google.com; s=arc-20160816; b=KzG0Xo/E+ibdfjS32wZz5ESb4pFtzcUfbFyeACTvIc51uXKU90rXVm8GmHsRPISFd2 EiriowjnNHkfBo/NRMNjS1LJFqTJ4cguwzc9C/3+iZrG5sh8J7ED0+oEg7xNiUOnqfzm OFV8/Ie/TBy+PAilBk7DNShcapjtWATkwgdjLv2t0LD9OujAcAXadsb8jXcWOwirququ 2+5bkV/Von/9Zle7/qsGqN1iXd8mzhWiusJaGN2Ow/6TQ3D+d36VcG5Y11WzQoOIEPcJ CJr14ZLNgOzJbF1qPpVlKdEIKenx2wNvkc6x1FdlMKeVRuef2BpeHNUlad8pmKBYXKEq 3BDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5FZShzhdUUXvOv6YwhzCq6E+ow3Z9zOiz8SIKSQQ5aQ=; fh=wPQP9HjC4b2j9fFVtoaE3tgh1QSkOqWUU7J9OsHbAwI=; b=v93ybWG4o+bO7yKai8UO68qN/wslaaBLX8Z+PtcYLdZz+I67XAZnQk7XqAFgoApqO8 zqINoeZlK6UZmGBGx7Oe91P/F/SJRjkVF1Qf5qjjnv6n8SispP5ZmlG4+bL8tvVKwA3b 9kTdby3mETqyiUf+/BP4gYs6dwMY4wo5KMkGAM38jcBnVp9VED6UCSaecsFks/YpgMVz 7sLtqLdoVBJN1FR16Tjn6ZsUwY7u5qt93jJIxkKHPSpAb/boo3LXJEa5WBFyyq+3HFPe MBJCOSQVBMeqC9q161FXlJYKrfGPWsGVocdUMZCJvYMyrxjVSZ2IUJP6wK9oJEYYpRoG wQtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Z9cnbRpB; spf=pass (google.com: domain of linux-kernel+bounces-13110-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-13110-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:24 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Daniel Vetter , David Airlie , Jessica Zhang , Krzysztof Kozlowski , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Rob Herring , Sam Ravnborg , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 5/8] dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK Date: Fri, 29 Dec 2023 14:51:20 +0100 Message-ID: <20231229135154.675946-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624644285339454 X-GMAIL-MSGID: 1786624644285339454 The patch adds the FRIDA FRD400B25025-A-CTK panel, which belongs to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi --- .../display/panel/novatek,nt35510.yaml | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml index bc92928c805b..511b93a376b7 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml @@ -14,14 +14,18 @@ allOf: properties: compatible: - items: - - const: hydis,hva40wv1 - - const: novatek,nt35510 - description: This indicates the panel manufacturer of the panel - that is in turn using the NT35510 panel driver. The compatible - string determines how the NT35510 panel driver shall be configured - to work with the indicated panel. The novatek,nt35510 compatible shall - always be provided as a fallback. + oneOf: + items: + - const: hydis,hva40wv1 + - const: novatek,nt35510 + items: + - const: frida,frd400b25025 + - const: novatek,nt35510 + description: This indicates the panel manufacturer of the panel + that is in turn using the NT35510 panel driver. The compatible + string determines how the NT35510 panel driver shall be configured + to work with the indicated panel. The novatek,nt35510 compatible shall + always be provided as a fallback. reg: true reset-gpios: true vdd-supply: From patchwork Fri Dec 29 13:51:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 183912 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp2579891dyb; Fri, 29 Dec 2023 05:54:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IHptGHFucSuKf45YHwWGALs9QcS7DcA3kUCTz4LBTyk9vqXPRCk0GQOJ9yTuM8vbHxDO49+ X-Received: by 2002:a17:903:2292:b0:1d4:39cb:f912 with SMTP id b18-20020a170903229200b001d439cbf912mr11950529plh.71.1703858045925; Fri, 29 Dec 2023 05:54:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703858045; cv=none; d=google.com; s=arc-20160816; b=JC3Uyeg66ytt7NaSKWcYWU9Bh2m18SxXcEleLlTiD3bU7ecXNi63Sc6huP1Uv5KYmP 2jxx0ANwYNK2HRm9OM590ZUAzAaM77998p2uv9JU394q2CEd2V/+yb+9tfVUq23nAjq/ w6lasTqVeK6PjisXHaDVR1fKN9QvMnIn4SGtnP87RLNWQ9qswp08YK+riypc8A3vEQ92 3cKWpOrZbvGnnR2dUlsFShlT7k1Wk7PWYFjSw3/aDUDA1dKon362Y2vrCNtrDF0gbnFt i/83+/BOqOK4UAFsW7KUJNNNvxs9DSNA6mEiySKnLz1hl5xIuAs9LrVsAcgKyx5fvQk9 SZDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=G2Gi1EmHukIt0jQJzaSt07+yXVEQJCsMbb8bSZVal5c=; fh=Q9MrInqKR5qw13DjusYCCVmzPW+bs/ge07Z5OTwo5qk=; b=UrWNr+WY3rqONPwAazLmZfd4ibMF/P1drideAkhfSmW0a1+VGX3PAQXMH7ibxCwl2/ wdrvC+0J9ZS2VXLkXL8FdVHW7lUMrvOtAV77sctPJyaSjwi2EMaSUC80wrXCDp3jmOrr mYp2Ek2yPqQSVhNHvZvU/w7j8ATXZVL0/G9B3HGXn7Z3TqAsyy32nmO2BsLV/XMFHS9X 3RHi6v5hUdWSoiIGRdPMdPobvcHYSvwOjZbwPY5SIaysxdwkFvnGLakaKHF7rlswidVZ mTN+Kbgb1TlHMTqQ8C9Bp6IvkSDOwRf8ia9Zotcg/xxl7NCXfx8MDE/3uoWMjhEZN8R7 9Iuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="pUC7/h5h"; spf=pass (google.com: domain of linux-kernel+bounces-13111-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-13111-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:26 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Andre Przywara , Conor Dooley , Krzysztof Kozlowski , =?utf-8?q?Leonard_?= =?utf-8?q?G=C3=B6hrs?= , Linus Walleij , Maxime Coquelin , Olivier Moysan , Rob Herring , Sean Nyekjaer , Tony Lindgren , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 6/8] ARM: dts: add stm32f769-disco-mb1225-revb03-mb1166-reva09 Date: Fri, 29 Dec 2023 14:51:21 +0100 Message-ID: <20231229135154.675946-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624654021955330 X-GMAIL-MSGID: 1786624654021955330 As reported in the section 8.3 (i. e. Board revision history) of document UM2033 (i. e. Discovery kit with STM32F769NI MCU) these are the changes related to the board revisions addressed by the patch: - Board MB1225 revision B-03: - Memory MICRON MT48LC4M32B2B5-6A replaced by ISSI IS42S32400F-6BL - Board MB1166 revision A-09: - LCD FRIDA FRD397B25009-D-CTK replaced by FRIDA FRD400B25025-A-CTK The patch only adds the DTS support for the new display which belongs to to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/st/Makefile | 1 + .../stm32f769-disco-mb1225-revb03-mb1166-reva09.dts | 13 +++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 7892ad69b441..390dbd300a57 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32f469-disco.dtb \ stm32f746-disco.dtb \ stm32f769-disco.dtb \ + stm32f769-disco-mb1225-revb03-mb1166-reva09.dts \ stm32429i-eval.dtb \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ diff --git a/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts b/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts new file mode 100644 index 000000000000..ff7ff32371d0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f769-disco.dts" + +&panel0 { + compatible = "frida,frd400b25025", "novatek,nt35510"; + vddi-supply = <&vcc_3v3>; + vdd-supply = <&vcc_3v3>; + /delete-property/power-supply; +}; From patchwork Fri Dec 29 13:51:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 183914 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp2580322dyb; Fri, 29 Dec 2023 05:55:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IFdmtbNswPHQVICq082IL88ty0yZBGqp3b1prFk/6/g8J3oUEEZa7JLlWLV7QdkkUuCBx0z X-Received: by 2002:a05:6358:9144:b0:172:aeb5:2338 with SMTP id r4-20020a056358914400b00172aeb52338mr9329104rwr.44.1703858104198; Fri, 29 Dec 2023 05:55:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703858104; cv=none; d=google.com; s=arc-20160816; b=wkxxAgghNGGP3+cn//iAQrn+ooI0c77Vq3uw75+42zdPArn6DVzL0icN2R6X3Xb4Gt fDK4pZ1dGLxzBc/+0x2JsCEPTwQEeGWuPKbZSDnQIKb2w09EQVVK21u/WjFUPFP9VDsi EOg0LNzGeh7c61llF08W8uzPi8CxbmXYO1BrB6UvB9Hu4zGu0DRnspJI/0ijDbJTJPIF ChJXk4MMaueH9c9JC+9zt/4mBuJS5+vGzTdN3PFEKe8PeXmH8CXqV5fqO2q4vAyEr0Tf EDwZwCQUOtkAFwT6Q4fnJVc2H2kr+hlTtLIZOahwW3rQegoWcBuuM/pIrl+qV8sObmpW MmAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=CvOVtGfr0/pzjQ+m6iJLaMRfy/Q5WgVQTgmUZQlV9hQ=; fh=LxW2lm9EXaAAWVYvTkRHJEwtDqo5+5rTSh+cuVdTysw=; b=pkj2GfvdK/HEpgl/AsGv2yN4ek11oh4iwXzO5HnZ6vMqZgiFVtNzEyAv0MPXa2R/aC SgzmQ7rL01TRRbF+IoK6xGif0Xm4jMUwbPOzyAARdXYuNSsKXLF3Im9bfPOvNssg2r5v 0a4+gbUAFJPJz6qTWyfdV8AE7yDrT5jL0yBpydSGnul7LIHJsaOK8Wv9fFRHyxOBlNZP tmWFDsPyz+8v41DAIjp5pFA2Xv+oFISoRL6EucsdeeBqtwNYjNihsbnxglvcJZecb5qX mLGxvz1w36bVbN6PJUyxdf+52tS60IYCLpknhvaSzCb0YTyln+/PTM+r02PHUkQDgfT3 Eyqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="B3d/gRa0"; spf=pass (google.com: domain of linux-kernel+bounces-13112-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-13112-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:27 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH 7/8] drm/panel: nt35510: refactor panel initialization Date: Fri, 29 Dec 2023 14:51:22 +0100 Message-ID: <20231229135154.675946-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624715522198863 X-GMAIL-MSGID: 1786624715522198863 The previous implementation did not make it easy to support new NT35510-based panels with different initialization sequences. This patch, preparatory for future developmentes, simplifies the addition of new NT35510-based displays and also avoids the risk of creating regressions on already managed panels. Signed-off-by: Dario Binacchi --- drivers/gpu/drm/panel/panel-novatek-nt35510.c | 797 ++++-------------- 1 file changed, 165 insertions(+), 632 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/drm/panel/panel-novatek-nt35510.c index d6dceb858008..2a5a624fe447 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -36,126 +36,33 @@ #include #include -#define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */ #define MCS_CMD_READ_ID1 0xDA #define MCS_CMD_READ_ID2 0xDB #define MCS_CMD_READ_ID3 0xDC #define MCS_CMD_MTP_READ_SETTING 0xF8 /* Uncertain about name */ #define MCS_CMD_MTP_READ_PARAM 0xFF /* Uncertain about name */ -/* - * These manufacturer commands are available after we enable manufacturer - * command set (MCS) for page 0. - */ -#define NT35510_P0_DOPCTR 0xB1 -#define NT35510_P0_SDHDTCTR 0xB6 -#define NT35510_P0_GSEQCTR 0xB7 -#define NT35510_P0_SDEQCTR 0xB8 -#define NT35510_P0_SDVPCTR 0xBA -#define NT35510_P0_DPFRCTR1 0xBD -#define NT35510_P0_DPFRCTR2 0xBE -#define NT35510_P0_DPFRCTR3 0xBF -#define NT35510_P0_DPMCTR12 0xCC - -#define NT35510_P0_DOPCTR_LEN 2 -#define NT35510_P0_GSEQCTR_LEN 2 -#define NT35510_P0_SDEQCTR_LEN 4 -#define NT35510_P0_SDVPCTR_LEN 1 -#define NT35510_P0_DPFRCTR1_LEN 5 -#define NT35510_P0_DPFRCTR2_LEN 5 -#define NT35510_P0_DPFRCTR3_LEN 5 -#define NT35510_P0_DPMCTR12_LEN 3 - -#define NT35510_DOPCTR_0_RAMKP BIT(7) /* Contents kept in sleep */ -#define NT35510_DOPCTR_0_DSITE BIT(6) /* Enable TE signal */ -#define NT35510_DOPCTR_0_DSIG BIT(5) /* Enable generic read/write */ -#define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */ -#define NT35510_DOPCTR_0_EOTP BIT(3) /* Support EoTP */ -#define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */ -#define NT35510_DOPCTR_1_TW_PWR_SEL BIT(4) /* TE power selector */ -#define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */ -#define NT35510_DOPCTR_1_CTB BIT(2) /* Vertical scanning direction */ -#define NT35510_DOPCTR_1_CRL BIT(1) /* Source driver data shift */ -#define NT35510_P0_SDVPCTR_PRG BIT(2) /* 0 = normal operation, 1 = VGLO */ -#define NT35510_P0_SDVPCTR_AVDD 0 /* source driver output = AVDD */ -#define NT35510_P0_SDVPCTR_OFFCOL 1 /* source driver output = off color */ -#define NT35510_P0_SDVPCTR_AVSS 2 /* source driver output = AVSS */ -#define NT35510_P0_SDVPCTR_HI_Z 3 /* source driver output = High impedance */ +#define _INIT_DCS_CMD(...) { \ + .type = INIT_DCS_CMD, \ + .len = sizeof((u8[]){__VA_ARGS__}), \ + .data = (u8[]){__VA_ARGS__} } -/* - * These manufacturer commands are available after we enable manufacturer - * command set (MCS) for page 1. - */ -#define NT35510_P1_SETAVDD 0xB0 -#define NT35510_P1_SETAVEE 0xB1 -#define NT35510_P1_SETVCL 0xB2 -#define NT35510_P1_SETVGH 0xB3 -#define NT35510_P1_SETVRGH 0xB4 -#define NT35510_P1_SETVGL 0xB5 -#define NT35510_P1_BT1CTR 0xB6 -#define NT35510_P1_BT2CTR 0xB7 -#define NT35510_P1_BT3CTR 0xB8 -#define NT35510_P1_BT4CTR 0xB9 /* VGH boosting times/freq */ -#define NT35510_P1_BT5CTR 0xBA -#define NT35510_P1_PFMCTR 0xBB -#define NT35510_P1_SETVGP 0xBC -#define NT35510_P1_SETVGN 0xBD -#define NT35510_P1_SETVCMOFF 0xBE -#define NT35510_P1_VGHCTR 0xBF /* VGH output ctrl */ -#define NT35510_P1_SET_GAMMA_RED_POS 0xD1 -#define NT35510_P1_SET_GAMMA_GREEN_POS 0xD2 -#define NT35510_P1_SET_GAMMA_BLUE_POS 0xD3 -#define NT35510_P1_SET_GAMMA_RED_NEG 0xD4 -#define NT35510_P1_SET_GAMMA_GREEN_NEG 0xD5 -#define NT35510_P1_SET_GAMMA_BLUE_NEG 0xD6 - -/* AVDD and AVEE setting 3 bytes */ -#define NT35510_P1_AVDD_LEN 3 -#define NT35510_P1_AVEE_LEN 3 -#define NT35510_P1_VGH_LEN 3 -#define NT35510_P1_VGL_LEN 3 -#define NT35510_P1_VGP_LEN 3 -#define NT35510_P1_VGN_LEN 3 -/* BT1CTR thru BT5CTR setting 3 bytes */ -#define NT35510_P1_BT1CTR_LEN 3 -#define NT35510_P1_BT2CTR_LEN 3 -#define NT35510_P1_BT4CTR_LEN 3 -#define NT35510_P1_BT5CTR_LEN 3 -/* 52 gamma parameters times two per color: positive and negative */ -#define NT35510_P1_GAMMA_LEN 52 +#define _INIT_DELAY_CMD(...) { \ + .type = DELAY_CMD,\ + .len = sizeof((u8[]){__VA_ARGS__}), \ + .data = (u8[]){__VA_ARGS__} } + +enum dsi_cmd_type { + INIT_DCS_CMD, + DELAY_CMD, +}; + +struct panel_init_cmd { + enum dsi_cmd_type type; + size_t len; + const u8 *data; +}; -/** - * struct nt35510_config - the display-specific NT35510 configuration - * - * Some of the settings provide an array of bytes, A, B C which mean: - * A = normal / idle off mode - * B = idle on mode - * C = partial / idle off mode - * - * Gamma correction arrays are 10bit numbers, two consecutive bytes - * makes out one point on the gamma correction curve. The points are - * not linearly placed along the X axis, we get points 0, 1, 3, 5 - * 7, 11, 15, 23, 31, 47, 63, 95, 127, 128, 160, 192, 208, 224, 232, - * 240, 244, 248, 250, 252, 254, 255. The voltages tuples form - * V0, V1, V3 ... V255, with 0x0000 being the lowest voltage and - * 0x03FF being the highest voltage. - * - * Each value must be strictly higher than the previous value forming - * a rising curve like this: - * - * ^ - * | V255 - * | V254 - * | .... - * | V5 - * | V3 - * | V1 - * | V0 - * +-------------------------------------------> - * - * The details about all settings can be found in the NT35510 Application - * Note. - */ struct nt35510_config { /** * @width_mm: physical panel width [mm] @@ -172,177 +79,90 @@ struct nt35510_config { */ const struct drm_display_mode mode; /** - * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V - * in 0.1V steps the default is 0x05 which means 6.0V - */ - u8 avdd[NT35510_P1_AVDD_LEN]; - /** - * @bt1ctr: setting for boost power control for the AVDD step-up - * circuit (1) - * bits 0..2 in the lower nibble controls PCK, the booster clock - * frequency for the step-up circuit: - * 0 = Hsync/32 - * 1 = Hsync/16 - * 2 = Hsync/8 - * 3 = Hsync/4 - * 4 = Hsync/2 - * 5 = Hsync - * 6 = Hsync x 2 - * 7 = Hsync x 4 - * bits 4..6 in the upper nibble controls BTP, the boosting - * amplification for the step-up circuit: - * 0 = Disable - * 1 = 1.5 x VDDB - * 2 = 1.66 x VDDB - * 3 = 2 x VDDB - * 4 = 2.5 x VDDB - * 5 = 3 x VDDB - * The defaults are 4 and 4 yielding 0x44 - */ - u8 bt1ctr[NT35510_P1_BT1CTR_LEN]; - /** - * @avee: setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V - * in 0.1V steps the default is 0x05 which means -6.0V - */ - u8 avee[NT35510_P1_AVEE_LEN]; - /** - * @bt2ctr: setting for boost power control for the AVEE step-up - * circuit (2) - * bits 0..2 in the lower nibble controls NCK, the booster clock - * frequency, the values are the same as for PCK in @bt1ctr. - * bits 4..5 in the upper nibble controls BTN, the boosting - * amplification for the step-up circuit. - * 0 = Disable - * 1 = -1.5 x VDDB - * 2 = -2 x VDDB - * 3 = -2.5 x VDDB - * 4 = -3 x VDDB - * The defaults are 4 and 3 yielding 0x34 - */ - u8 bt2ctr[NT35510_P1_BT2CTR_LEN]; - /** - * @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V - * in 1V steps, the default is 0x08 which means 15V - */ - u8 vgh[NT35510_P1_VGH_LEN]; - /** - * @bt4ctr: setting for boost power control for the VGH step-up - * circuit (4) - * bits 0..2 in the lower nibble controls HCK, the booster clock - * frequency, the values are the same as for PCK in @bt1ctr. - * bits 4..5 in the upper nibble controls BTH, the boosting - * amplification for the step-up circuit. - * 0 = AVDD + VDDB - * 1 = AVDD - AVEE - * 2 = AVDD - AVEE + VDDB - * 3 = AVDD x 2 - AVEE - * The defaults are 4 and 3 yielding 0x34 - */ - u8 bt4ctr[NT35510_P1_BT4CTR_LEN]; - /** - * @vgl: setting for VGL ranging from 0x00 = -2V to 0x0f = -15V in - * 1V steps, the default is 0x08 which means -10V - */ - u8 vgl[NT35510_P1_VGL_LEN]; - /** - * @bt5ctr: setting for boost power control for the VGL step-up - * circuit (5) - * bits 0..2 in the lower nibble controls LCK, the booster clock - * frequency, the values are the same as for PCK in @bt1ctr. - * bits 4..5 in the upper nibble controls BTL, the boosting - * amplification for the step-up circuit. - * 0 = AVEE + VCL - * 1 = AVEE - AVDD - * 2 = AVEE + VCL - AVDD - * 3 = AVEE x 2 - AVDD - * The defaults are 3 and 2 yielding 0x32 - */ - u8 bt5ctr[NT35510_P1_BT5CTR_LEN]; - /** - * @vgp: setting for VGP, the positive gamma divider voltages - * VGMP the high voltage and VGSP the low voltage. - * The first byte contains bit 8 of VGMP and VGSP in bits 4 and 0 - * The second byte contains bit 0..7 of VGMP - * The third byte contains bit 0..7 of VGSP - * VGMP 0x00 = 3.0V .. 0x108 = 6.3V in steps of 12.5mV - * VGSP 0x00 = 0V .. 0x111 = 3.7V in steps of 12.5mV - */ - u8 vgp[NT35510_P1_VGP_LEN]; - /** - * @vgn: setting for VGN, the negative gamma divider voltages, - * same layout of bytes as @vgp. - */ - u8 vgn[NT35510_P1_VGN_LEN]; - /** - * @sdeqctr: Source driver control settings, first byte is - * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and - * mode 2 uses three steps meaning EQS3 is not used in mode - * 1. Mode 2 is default. The last three parameters are EQS1, EQS2 - * and EQS3, setting the rise time for each equalizer step: - * 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default - * is 0x07 = 3.5 us. - */ - u8 sdeqctr[NT35510_P0_SDEQCTR_LEN]; - /** - * @sdvpctr: power/voltage behaviour during vertical porch time - */ - u8 sdvpctr; - /** - * @t1: the number of pixel clocks on one scanline, range - * 0x100 (258 ticks) .. 0x3FF (1024 ticks) so the value + 1 - * clock ticks. - */ - u16 t1; - /** - * @vbp: vertical back porch toward the PANEL note: not toward - * the DSI host; these are separate interfaces, in from DSI host - * and out to the panel. - */ - u8 vbp; - /** - * @vfp: vertical front porch toward the PANEL. - */ - u8 vfp; + * @lanes: number of active data lanes + */ + unsigned int lanes; /** - * @psel: pixel clock divisor: 0 = 1, 1 = 2, 2 = 4, 3 = 8. + * @format: pixel format for video mode */ - u8 psel; + enum mipi_dsi_pixel_format format; /** - * @dpmctr12: Display timing control 12 - * Byte 1 bit 4 selects LVGL voltage level: 0 = VGLX, 1 = VGL_REG - * Byte 1 bit 1 selects gate signal mode: 0 = non-overlap, 1 = overlap - * Byte 1 bit 0 selects output signal control R/L swap, 0 = normal - * 1 = swap all O->E, L->R - * Byte 2 is CLW delay clock for CK O/E and CKB O/E signals: - * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps - * Byte 3 is FTI_H0 delay time for STP O/E signals: - * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps + * @mode_flags: DSI operation mode related flags */ - u8 dpmctr12[NT35510_P0_DPMCTR12_LEN]; + unsigned long mode_flags; /** - * @gamma_corr_pos_r: Red gamma correction parameters, positive + * @hs_rate: maximum lane frequency for high speed mode in hertz, this should + * be set to the real limits of the hardware, zero is only accepted for + * legacy drivers */ - u8 gamma_corr_pos_r[NT35510_P1_GAMMA_LEN]; + unsigned long hs_rate; /** - * @gamma_corr_pos_g: Green gamma correction parameters, positive + * @lp_rate: maximum lane frequency for low power mode in hertz, this should + * be set to the real limits of the hardware, zero is only accepted for + * legacy drivers */ - u8 gamma_corr_pos_g[NT35510_P1_GAMMA_LEN]; + unsigned long lp_rate; /** - * @gamma_corr_pos_b: Blue gamma correction parameters, positive + * @init_cmds: initialization command list */ - u8 gamma_corr_pos_b[NT35510_P1_GAMMA_LEN]; - /** - * @gamma_corr_neg_r: Red gamma correction parameters, negative - */ - u8 gamma_corr_neg_r[NT35510_P1_GAMMA_LEN]; - /** - * @gamma_corr_neg_g: Green gamma correction parameters, negative - */ - u8 gamma_corr_neg_g[NT35510_P1_GAMMA_LEN]; - /** - * @gamma_corr_neg_b: Blue gamma correction parameters, negative - */ - u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN]; + const struct panel_init_cmd *init_cmds; +}; + +static const struct panel_init_cmd hydis_hva40wv1_init_cmds[] = { + _INIT_DCS_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01), + _INIT_DCS_CMD(0xB0, 0x09, 0x09, 0x09), + _INIT_DCS_CMD(0xB6, 0x34, 0x34, 0x34), + _INIT_DCS_CMD(0xB1, 0x09, 0x09, 0x09), + _INIT_DCS_CMD(0xB7, 0x24, 0x24, 0x24), + _INIT_DCS_CMD(0xB3, 0x05, 0x05, 0x05), + _INIT_DCS_CMD(0xB9, 0x24, 0x24, 0x24), + _INIT_DCS_CMD(0xBF, 0x01), + _INIT_DCS_CMD(0xB5, 0x0B, 0x0B, 0x0B), + _INIT_DCS_CMD(0xBA, 0x24, 0x24, 0x24), + _INIT_DCS_CMD(0xBC, 0x00, 0xA3, 0x00), + _INIT_DCS_CMD(0xBD, 0x00, 0xA3, 0x00), + _INIT_DELAY_CMD(0x0A), + _INIT_DCS_CMD(0xD1, 0x00, 0x01, 0x00, 0x43, 0x00, 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01), + _INIT_DCS_CMD(0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, 0x83, 0x02, 0x78, 0x02, 0x9E), + _INIT_DCS_CMD(0x02, 0xDD, 0x03, 0x00, 0x03, 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03), + _INIT_DCS_CMD(0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE), + _INIT_DCS_CMD(0xD2, 0x00, 0x01, 0x00, 0x43, 0x00, 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01), + _INIT_DCS_CMD(0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, 0x83, 0x02, 0x78, 0x02, 0x9E), + _INIT_DCS_CMD(0x02, 0xDD, 0x03, 0x00, 0x03, 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03), + _INIT_DCS_CMD(0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE), + _INIT_DCS_CMD(0xD3, 0x00, 0x01, 0x00, 0x43, 0x00, 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01), + _INIT_DCS_CMD(0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, 0x83, 0x02, 0x78, 0x02, 0x9E), + _INIT_DCS_CMD(0x02, 0xDD, 0x03, 0x00, 0x03, 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03), + _INIT_DCS_CMD(0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE), + _INIT_DCS_CMD(0xD4, 0x00, 0x01, 0x00, 0x43, 0x00, 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01), + _INIT_DCS_CMD(0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, 0x43, 0x02, 0x50, 0x02, 0x9E), + _INIT_DCS_CMD(0x02, 0xDD, 0x03, 0x00, 0x03, 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03), + _INIT_DCS_CMD(0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE), + _INIT_DCS_CMD(0xD5, 0x00, 0x01, 0x00, 0x43, 0x00, 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01), + _INIT_DCS_CMD(0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, 0x43, 0x02, 0x50, 0x02, 0x9E), + _INIT_DCS_CMD(0x02, 0xDD, 0x03, 0x00, 0x03, 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03), + _INIT_DCS_CMD(0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE), + _INIT_DCS_CMD(0xD6, 0x00, 0x01, 0x00, 0x43, 0x00, 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01), + _INIT_DCS_CMD(0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, 0x43, 0x02, 0x50, 0x02, 0x9E), + _INIT_DCS_CMD(0x02, 0xDD, 0x03, 0x00, 0x03, 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03), + _INIT_DCS_CMD(0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE), + _INIT_DCS_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00), + _INIT_DCS_CMD(0xB1, 0x4C, 0x04), + _INIT_DCS_CMD(0x36, 0x02), + _INIT_DCS_CMD(0xB6, 0x0A), + _INIT_DCS_CMD(0xB7, 0x00, 0x00), + _INIT_DCS_CMD(0xB8, 0x01, 0x05, 0x05, 0x05), + _INIT_DCS_CMD(0xBA, 0x01), + _INIT_DCS_CMD(0xBD, 0x01, 0x84, 0x07, 0x32, 0x00), + _INIT_DCS_CMD(0xBE, 0x01, 0x84, 0x07, 0x31, 0x00), + _INIT_DCS_CMD(0xBF, 0x01, 0x84, 0x07, 0x31, 0x00), + _INIT_DCS_CMD(0x35, 0x00), + _INIT_DCS_CMD(0xCC, 0x03, 0x00, 0x00), + _INIT_DCS_CMD(0x11), + _INIT_DELAY_CMD(0x78), + _INIT_DCS_CMD(0x29), + _INIT_DELAY_CMD(0x0A), + {}, }; /** @@ -379,18 +199,11 @@ static const u8 nt35510_mauc_mtp_read_param[] = { 0xAA, 0x55, 0x25, 0x01 }; static const u8 nt35510_mauc_mtp_read_setting[] = { 0x01, 0x02, 0x00, 0x20, 0x33, 0x13, 0x00, 0x40, 0x00, 0x00, 0x23, 0x02 }; -static const u8 nt35510_mauc_select_page_0[] = { 0x55, 0xAA, 0x52, 0x08, 0x00 }; -static const u8 nt35510_mauc_select_page_1[] = { 0x55, 0xAA, 0x52, 0x08, 0x01 }; -static const u8 nt35510_vgh_on[] = { 0x01 }; - static inline struct nt35510 *panel_to_nt35510(struct drm_panel *panel) { return container_of(panel, struct nt35510, panel); } -#define NT35510_ROTATE_0_SETTING 0x02 -#define NT35510_ROTATE_180_SETTING 0x00 - static int nt35510_send_long(struct nt35510 *nt, struct mipi_dsi_device *dsi, u8 cmd, u8 cmdlen, const u8 *seq) { @@ -457,195 +270,6 @@ static int nt35510_read_id(struct nt35510 *nt) return 0; } -/** - * nt35510_setup_power() - set up power config in page 1 - * @nt: the display instance to set up - */ -static int nt35510_setup_power(struct nt35510 *nt) -{ - struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); - int ret; - - ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVDD, - NT35510_P1_AVDD_LEN, - nt->conf->avdd); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_BT1CTR, - NT35510_P1_BT1CTR_LEN, - nt->conf->bt1ctr); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVEE, - NT35510_P1_AVEE_LEN, - nt->conf->avee); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_BT2CTR, - NT35510_P1_BT2CTR_LEN, - nt->conf->bt2ctr); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGH, - NT35510_P1_VGH_LEN, - nt->conf->vgh); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_BT4CTR, - NT35510_P1_BT4CTR_LEN, - nt->conf->bt4ctr); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_VGHCTR, - ARRAY_SIZE(nt35510_vgh_on), - nt35510_vgh_on); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGL, - NT35510_P1_VGL_LEN, - nt->conf->vgl); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_BT5CTR, - NT35510_P1_BT5CTR_LEN, - nt->conf->bt5ctr); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGP, - NT35510_P1_VGP_LEN, - nt->conf->vgp); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGN, - NT35510_P1_VGN_LEN, - nt->conf->vgn); - if (ret) - return ret; - - /* Typically 10 ms */ - usleep_range(10000, 20000); - - return 0; -} - -/** - * nt35510_setup_display() - set up display config in page 0 - * @nt: the display instance to set up - */ -static int nt35510_setup_display(struct nt35510 *nt) -{ - struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); - const struct nt35510_config *conf = nt->conf; - u8 dopctr[NT35510_P0_DOPCTR_LEN]; - u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; - u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN]; - /* FIXME: set up any rotation (assume none for now) */ - u8 addr_mode = NT35510_ROTATE_0_SETTING; - u8 val; - int ret; - - /* Enable TE, EoTP and RGB pixel format */ - dopctr[0] = NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | - NT35510_DOPCTR_0_N565; - dopctr[1] = NT35510_DOPCTR_1_CTB; - ret = nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR, - NT35510_P0_DOPCTR_LEN, - dopctr); - if (ret) - return ret; - - ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode, - sizeof(addr_mode)); - if (ret < 0) - return ret; - - /* - * Source data hold time, default 0x05 = 2.5us - * 0x00..0x3F = 0 .. 31.5us in steps of 0.5us - * 0x0A = 5us - */ - val = 0x0A; - ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val, - sizeof(val)); - if (ret < 0) - return ret; - - /* EQ control for gate signals, 0x00 = 0 us */ - gseqctr[0] = 0x00; - gseqctr[1] = 0x00; - ret = nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR, - NT35510_P0_GSEQCTR_LEN, - gseqctr); - if (ret) - return ret; - - ret = nt35510_send_long(nt, dsi, NT35510_P0_SDEQCTR, - NT35510_P0_SDEQCTR_LEN, - conf->sdeqctr); - if (ret) - return ret; - - ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDVPCTR, - &conf->sdvpctr, 1); - if (ret < 0) - return ret; - - /* - * Display timing control for active and idle off mode: - * the first byte contains - * the two high bits of T1A and second byte the low 8 bits, and - * the valid range is 0x100 (257) to 0x3ff (1023) representing - * 258..1024 (+1) pixel clock ticks for one scanline. At 20MHz pixel - * clock this covers the range of 12.90us .. 51.20us in steps of - * 0.05us, the default is 0x184 (388) representing 389 ticks. - * The third byte is VBPDA, vertical back porch display active - * and the fourth VFPDA, vertical front porch display active, - * both given in number of scanlines in the range 0x02..0xff - * for 2..255 scanlines. The fifth byte is 2 bits selecting - * PSEL for active and idle off mode, how much the 20MHz clock - * is divided by 0..3. This needs to be adjusted to get the right - * frame rate. - */ - dpfrctr[0] = (conf->t1 >> 8) & 0xFF; - dpfrctr[1] = conf->t1 & 0xFF; - /* Vertical back porch */ - dpfrctr[2] = conf->vbp; - /* Vertical front porch */ - dpfrctr[3] = conf->vfp; - dpfrctr[4] = conf->psel; - ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR1, - NT35510_P0_DPFRCTR1_LEN, - dpfrctr); - if (ret) - return ret; - /* For idle and partial idle off mode we decrease front porch by one */ - dpfrctr[3]--; - ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR2, - NT35510_P0_DPFRCTR2_LEN, - dpfrctr); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR3, - NT35510_P0_DPFRCTR3_LEN, - dpfrctr); - if (ret) - return ret; - - /* Enable TE on vblank */ - ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret) - return ret; - - /* Turn on the pads? */ - ret = nt35510_send_long(nt, dsi, NT35510_P0_DPMCTR12, - NT35510_P0_DPMCTR12_LEN, - conf->dpmctr12); - if (ret) - return ret; - - return 0; -} - static int nt35510_set_brightness(struct backlight_device *bl) { struct nt35510 *nt = bl_get_data(bl); @@ -672,7 +296,6 @@ static const struct backlight_ops nt35510_bl_ops = { */ static int nt35510_power_on(struct nt35510 *nt) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); int ret; ret = regulator_bulk_enable(ARRAY_SIZE(nt->supplies), nt->supplies); @@ -694,73 +317,6 @@ static int nt35510_power_on(struct nt35510 *nt) usleep_range(120000, 140000); } - ret = nt35510_send_long(nt, dsi, MCS_CMD_MTP_READ_PARAM, - ARRAY_SIZE(nt35510_mauc_mtp_read_param), - nt35510_mauc_mtp_read_param); - if (ret) - return ret; - - ret = nt35510_send_long(nt, dsi, MCS_CMD_MTP_READ_SETTING, - ARRAY_SIZE(nt35510_mauc_mtp_read_setting), - nt35510_mauc_mtp_read_setting); - if (ret) - return ret; - - nt35510_read_id(nt); - - /* Set up stuff in manufacturer control, page 1 */ - ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, - ARRAY_SIZE(nt35510_mauc_select_page_1), - nt35510_mauc_select_page_1); - if (ret) - return ret; - - ret = nt35510_setup_power(nt); - if (ret) - return ret; - - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_r); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_g); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_b); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_r); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_g); - if (ret) - return ret; - ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_b); - if (ret) - return ret; - - /* Set up stuff in manufacturer control, page 0 */ - ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, - ARRAY_SIZE(nt35510_mauc_select_page_0), - nt35510_mauc_select_page_0); - if (ret) - return ret; - - ret = nt35510_setup_display(nt); - if (ret) - return ret; - return 0; } @@ -808,6 +364,44 @@ static int nt35510_unprepare(struct drm_panel *panel) return 0; } +static int nt35510_init(struct nt35510 *nt) +{ + struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); + const struct panel_init_cmd *cmds = nt->conf->init_cmds; + int i, ret; + + if (!cmds) { + dev_warn(nt->dev, "empty initialization command list\n"); + return 0; + } + + for (i = 0; cmds[i].len != 0; i++) { + const struct panel_init_cmd *cmd = &cmds[i]; + + switch (cmd->type) { + case DELAY_CMD: + msleep(cmd->data[0]); + ret = 0; + break; + case INIT_DCS_CMD: + ret = nt35510_send_long(nt, dsi, cmd->data[0], + cmd->len - 1, + cmd->len <= 1 ? NULL : + &cmd->data[1]); + break; + default: + ret = -EINVAL; + } + + if (ret < 0) { + dev_err(nt->dev, "failed to write command %u\n", i); + return ret; + } + } + + return 0; +} + static int nt35510_prepare(struct drm_panel *panel) { struct nt35510 *nt = panel_to_nt35510(panel); @@ -818,24 +412,21 @@ static int nt35510_prepare(struct drm_panel *panel) if (ret) return ret; - /* Exit sleep mode */ - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret) { - dev_err(nt->dev, "failed to exit sleep mode (%d)\n", ret); + ret = nt35510_send_long(nt, dsi, MCS_CMD_MTP_READ_PARAM, + ARRAY_SIZE(nt35510_mauc_mtp_read_param), + nt35510_mauc_mtp_read_param); + if (ret) return ret; - } - /* Up to 120 ms */ - usleep_range(120000, 150000); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret) { - dev_err(nt->dev, "failed to turn display on (%d)\n", ret); + ret = nt35510_send_long(nt, dsi, MCS_CMD_MTP_READ_SETTING, + ARRAY_SIZE(nt35510_mauc_mtp_read_setting), + nt35510_mauc_mtp_read_setting); + if (ret) return ret; - } - /* Some 10 ms */ - usleep_range(10000, 20000); - return 0; + nt35510_read_id(nt); + + return nt35510_init(nt); } static int nt35510_get_modes(struct drm_panel *panel, @@ -878,25 +469,6 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) nt = devm_kzalloc(dev, sizeof(struct nt35510), GFP_KERNEL); if (!nt) return -ENOMEM; - mipi_dsi_set_drvdata(dsi, nt); - nt->dev = dev; - - dsi->lanes = 2; - dsi->format = MIPI_DSI_FMT_RGB888; - /* - * Datasheet suggests max HS rate for NT35510 is 250 MHz - * (period time 4ns, see figure 7.6.4 page 365) and max LP rate is - * 20 MHz (period time 50ns, see figure 7.6.6. page 366). - * However these frequencies appear in source code for the Hydis - * HVA40WV1 panel and setting up the LP frequency makes the panel - * not work. - * - * TODO: if other panels prove to be closer to the datasheet, - * maybe make this a per-panel config in struct nt35510_config? - */ - dsi->hs_rate = 349440000; - dsi->lp_rate = 9600000; - dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS; /* * Every new incarnation of this display must have a unique @@ -908,6 +480,15 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) return -ENODEV; } + mipi_dsi_set_drvdata(dsi, nt); + nt->dev = dev; + + dsi->lanes = nt->conf->lanes; + dsi->format = nt->conf->format; + dsi->hs_rate = nt->conf->hs_rate; + dsi->lp_rate = nt->conf->lp_rate; + dsi->mode_flags = nt->conf->mode_flags; + nt->supplies[0].supply = "vdd"; /* 2.3-4.8 V */ nt->supplies[1].supply = "vddi"; /* 1.65-3.3V */ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies), @@ -980,27 +561,6 @@ static void nt35510_remove(struct mipi_dsi_device *dsi) drm_panel_remove(&nt->panel); } -/* - * These gamma correction values are 10bit tuples, so only bits 0 and 1 is - * ever used in the first byte. They form a positive and negative gamma - * correction curve for each color, values must be strictly higher for each - * step on the curve. As can be seen these default curves goes from 0x0001 - * to 0x03FE. - */ -#define NT35510_GAMMA_POS_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \ - 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \ - 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \ - 0x83, 0x02, 0x78, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \ - 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \ - 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE - -#define NT35510_GAMMA_NEG_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \ - 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \ - 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \ - 0x43, 0x02, 0x50, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \ - 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \ - 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE - /* * The Hydis HVA40WV1 panel */ @@ -1030,47 +590,20 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .vtotal = 800 + 2 + 0 + 5, /* VBP = 5 */ .flags = 0, }, - /* 0x09: AVDD = 5.6V */ - .avdd = { 0x09, 0x09, 0x09 }, - /* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */ - .bt1ctr = { 0x34, 0x34, 0x34 }, - /* 0x09: AVEE = -5.6V */ - .avee = { 0x09, 0x09, 0x09 }, - /* 0x24: NCK = Hsync/2, BTN = -2 x VDDB */ - .bt2ctr = { 0x24, 0x24, 0x24 }, - /* 0x05 = 12V */ - .vgh = { 0x05, 0x05, 0x05 }, - /* 0x24: NCKA = Hsync/2, VGH = 2 x AVDD - AVEE */ - .bt4ctr = { 0x24, 0x24, 0x24 }, - /* 0x0B = -13V */ - .vgl = { 0x0B, 0x0B, 0x0B }, - /* 0x24: LCKA = Hsync, VGL = AVDD + VCL - AVDD */ - .bt5ctr = { 0x24, 0x24, 0x24 }, - /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */ - .vgp = { 0x00, 0xA3, 0x00 }, - /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */ - .vgn = { 0x00, 0xA3, 0x00 }, - /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */ - .sdeqctr = { 0x01, 0x05, 0x05, 0x05 }, - /* SDVPCTR: Normal operation off color during v porch */ - .sdvpctr = 0x01, - /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */ - .t1 = 0x0184, - /* VBP: vertical back porch toward the panel */ - .vbp = 7, - /* VFP: vertical front porch toward the panel */ - .vfp = 50, - /* PSEL: divide pixel clock 20MHz with 1 (no clock downscaling) */ - .psel = 0, - /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */ - .dpmctr12 = { 0x03, 0x00, 0x00, }, - /* Default gamma correction values */ - .gamma_corr_pos_r = { NT35510_GAMMA_POS_DEFAULT }, - .gamma_corr_pos_g = { NT35510_GAMMA_POS_DEFAULT }, - .gamma_corr_pos_b = { NT35510_GAMMA_POS_DEFAULT }, - .gamma_corr_neg_r = { NT35510_GAMMA_NEG_DEFAULT }, - .gamma_corr_neg_g = { NT35510_GAMMA_NEG_DEFAULT }, - .gamma_corr_neg_b = { NT35510_GAMMA_NEG_DEFAULT }, + .mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS, + .lanes = 2, + .format = MIPI_DSI_FMT_RGB888, + /* + * Datasheet suggests max HS rate for NT35510 is 250 MHz + * (period time 4ns, see figure 7.6.4 page 365) and max LP rate is + * 20 MHz (period time 50ns, see figure 7.6.6. page 366). + * However these frequencies appear in source code for the Hydis + * HVA40WV1 panel and setting up the LP frequency makes the panel + * not work. + */ + .hs_rate = 349440000, + .lp_rate = 9600000, + .init_cmds = hydis_hva40wv1_init_cmds, }; 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[79.49.57.70]) by smtp.gmail.com with ESMTPSA id i16-20020aa7c710000000b00553b243b1a8sm11019160edq.92.2023.12.29.05.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 05:52:28 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH 8/8] drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK Date: Fri, 29 Dec 2023 14:51:23 +0100 Message-ID: <20231229135154.675946-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> References: <20231229135154.675946-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786624684725458694 X-GMAIL-MSGID: 1786624684725458694 The initialization commands are taken from the STMicroelectronics driver found at https://github.com/STMicroelectronics/STM32CubeF7/blob/master/Drivers/BSP/Components/nt35510/ Signed-off-by: Dario Binacchi --- drivers/gpu/drm/panel/panel-novatek-nt35510.c | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/drm/panel/panel-novatek-nt35510.c index 2a5a624fe447..3cdcc75c4c76 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Novatek NT35510 panel driver + * Copyright (C) 2023 Dario Binacchi + * Add support to Frida FRD400B25025-A-CTK panel. + * Based on code by MCD Application Team (C) 2020 STMicroelectronics * Copyright (C) 2020 Linus Walleij * Based on code by Robert Teather (C) 2012 Samsung * @@ -165,6 +168,49 @@ static const struct panel_init_cmd hydis_hva40wv1_init_cmds[] = { {}, }; +static const struct panel_init_cmd frida_frd400b25025_init_cmds[] = { + _INIT_DCS_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01), + _INIT_DCS_CMD(0xB0, 0x03, 0x03, 0x03), + _INIT_DCS_CMD(0xB6, 0x46, 0x46, 0x46), + _INIT_DCS_CMD(0xB1, 0x03, 0x03, 0x03), + _INIT_DCS_CMD(0xB7, 0x36, 0x36, 0x36), + _INIT_DCS_CMD(0xB2, 0x00, 0x00, 0x02), + _INIT_DCS_CMD(0xB8, 0x26, 0x26, 0x26), + _INIT_DCS_CMD(0xBF, 0x01), + _INIT_DCS_CMD(0xB3, 0x09, 0x09, 0x09), + _INIT_DCS_CMD(0xB9, 0x36, 0x36, 0x36), + _INIT_DCS_CMD(0xB5, 0x08, 0x08, 0x08), + _INIT_DCS_CMD(0xBA, 0x26, 0x26, 0x26), + _INIT_DCS_CMD(0xBC, 0x00, 0x80, 0x00), + _INIT_DCS_CMD(0xBD, 0x00, 0x80, 0x00), + _INIT_DCS_CMD(0xBE, 0x00, 0x50), + _INIT_DCS_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00), + _INIT_DCS_CMD(0xB1, 0xFC, 0x00), + _INIT_DCS_CMD(0xB6, 0x03), + _INIT_DCS_CMD(0xB5, 0x50), + _INIT_DCS_CMD(0xB7, 0x00, 0x00), + _INIT_DCS_CMD(0xB8, 0x01, 0x02, 0x02, 0x02), + _INIT_DCS_CMD(0xBC, 0x00, 0x00, 0x00), + _INIT_DCS_CMD(0xCC, 0x03, 0x00, 0x00), + _INIT_DCS_CMD(0xBA, 0x01), + _INIT_DCS_CMD(0x35, 0x00), + _INIT_DCS_CMD(0x3A, 0x77), + _INIT_DELAY_CMD(0xC8), + _INIT_DCS_CMD(0x36, 0x00), + _INIT_DCS_CMD(0x2A, 0x00, 0x00, 0x01, 0xDF), + _INIT_DCS_CMD(0x2B, 0x00, 0x00, 0x03, 0x1F), + _INIT_DCS_CMD(0x11), + _INIT_DELAY_CMD(0x78), + _INIT_DCS_CMD(0x3A, 0x77), + _INIT_DCS_CMD(0x51, 0x7F, 0x00), + _INIT_DCS_CMD(0x53, 0x2C), + _INIT_DCS_CMD(0x55, 0x02), + _INIT_DCS_CMD(0x5E, 0xFF), + _INIT_DCS_CMD(0x29), + _INIT_DCS_CMD(0x2C), + {}, +}; + /** * struct nt35510 - state container for the NT35510 panel */ @@ -606,7 +652,36 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { .init_cmds = hydis_hva40wv1_init_cmds, }; +/* + * The Frida FRD400B25025-A-CTK panel + */ +static const struct nt35510_config nt35510_frida_frd400b25025 = { + .width_mm = 52, + .height_mm = 86, + .mode = { + .clock = 23000, + .hdisplay = 480, + .hsync_start = 480 + 34, /* HFP = 34 */ + .hsync_end = 480 + 34 + 2, /* HSync = 2 */ + .htotal = 480 + 34 + 2 + 34, /* HBP = 34 */ + .vdisplay = 800, + .vsync_start = 800 + 15, /* VFP = 15 */ + .vsync_end = 800 + 15 + 12, /* VSync = 12 */ + .vtotal = 800 + 15 + 12 + 15, /* VBP = 15 */ + .flags = 0, + }, + .lanes = 2, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM, + .init_cmds = frida_frd400b25025_init_cmds, +}; + static const struct of_device_id nt35510_of_match[] = { + { + .compatible = "frida,frd400b25025", + .data = &nt35510_frida_frd400b25025, + }, { .compatible = "hydis,hva40wv1", .data = &nt35510_hydis_hva40wv1,