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bh=pXl6KcZ/igL/xjrZllsT227KZKbx7d5y+tj+7JC+ULs=; b=WHcBnzPfBA8hjiOO8CH8PRUvKiUeuI+WJw1NsrvRVx7hcqjIc3nlgaBps+1HaIIV7L wRdlS6gSRu5lbIvbWZ0ZUC68ImrfyFleTDo9/SGUOvoYh0Sd82imJiahwZAaB/y9LBWb mnDiT5bonsfbwdOxgE1Yq54uHLX3aYk203GghblkW+6/cap7Z8aaSijC39okEW2qp/bi p0TwLQMFlxCz7yrh+IajngELOepIt1kn08yA9ICTRKZ8oeNmUL6YTnUcJylj6ieZ/VWi jUfV0gVsdBi6wUaa7rxrnFe1/5rxtgeAAGTzISt1kNm2vP4VweUC+7WzC541eMvLiNHm 3JKQ== X-Gm-Message-State: AOJu0Yy23nf/M8l65HKGbquoSTuHmXZxWbo1Lok1LAL/irHflnWlk84k qGrdZCwwSTKSLTVfeOtGQh63mwOKYri31iEi3nvpJJF4c9H7zQ== X-Received: by 2002:a05:6402:1603:b0:554:1431:a977 with SMTP id f3-20020a056402160300b005541431a977mr6379363edv.54.1703840150481; Fri, 29 Dec 2023 00:55:50 -0800 (PST) MIME-Version: 1.0 From: Uros Bizjak Date: Fri, 29 Dec 2023 09:55:39 +0100 Message-ID: Subject: [committed] i386: Fix TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter [PR113133] To: "gcc-patches@gcc.gnu.org" Cc: Haochen Jiang X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786606198988987075 X-GMAIL-MSGID: 1786606198988987075 The post-reload splitter currently allows xmm16+ registers with TARGET_EVEX512. The splitter changes SFmode of the output operand to V4SFmode, but the vector mode is currently unsupported in xmm16+ without TARGET_AVX512VL. lowpart_subreg returns NULL_RTX in this case and the compilation fails with invalid RTX. The patch removes support for x/ymm16+ registers with TARGET_EVEX512. The support should be restored once ix86_hard_regno_mode_ok is fixed to allow 16-byte modes in x/ymm16+ with TARGET_EVEX512. PR target/113133 gcc/ChangeLog: * config/i386/i386.md (TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter): Do not handle xmm16+ with TARGET_EVEX512. gcc/testsuite/ChangeLog: * gcc.target/i386/pr113133-1.c: New test. * gcc.target/i386/pr113133-2.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index ca6dbf42a6d..cdb9ddc4eb3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5210,7 +5210,7 @@ (define_split && optimize_insn_for_speed_p () && reload_completed && (!EXT_REX_SSE_REG_P (operands[0]) - || TARGET_AVX512VL || TARGET_EVEX512)" + || TARGET_AVX512VL)" [(set (match_dup 2) (float_extend:V2DF (vec_select:V2SF diff --git a/gcc/testsuite/gcc.target/i386/pr113133-1.c b/gcc/testsuite/gcc.target/i386/pr113133-1.c new file mode 100644 index 00000000000..63a1a413bba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113133-1.c @@ -0,0 +1,21 @@ +/* PR target/113133 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512f -mtune=barcelona" } */ + +void +foo1 (double *d, float f) +{ + register float x __asm ("xmm16") = f; + asm volatile ("" : "+v" (x)); + + *d = x; +} + +void +foo2 (float *f, double d) +{ + register double x __asm ("xmm16") = d; + asm volatile ("" : "+v" (x)); + + *f = x; +} diff --git a/gcc/testsuite/gcc.target/i386/pr113133-2.c b/gcc/testsuite/gcc.target/i386/pr113133-2.c new file mode 100644 index 00000000000..8974d8ced7f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113133-2.c @@ -0,0 +1,72 @@ +/* PR target/113133 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O -fno-tree-ter -mavx512f -mtune=barcelona" } */ + +typedef char v8u8; +typedef unsigned char __attribute__((__vector_size__(2))) v16u8; +typedef signed char __attribute__((__vector_size__(2))) v16s8; +typedef char __attribute__((__vector_size__(4))) v32u8; +typedef unsigned char __attribute__((__vector_size__(8))) v64u8; +typedef char __attribute__((__vector_size__(16))) v128u8; +typedef signed char __attribute__((__vector_size__(16))) v128s8; +typedef short __attribute__((__vector_size__(8))) v64u16; +typedef int __attribute__((__vector_size__(16))) v128u32; +typedef _Float16 __attribute__((__vector_size__(8))) v64f16; +typedef _Float32 f32; +char foo0_u8_0, foo0_ret; +v16s8 foo0_v16s8_0; +v64u8 foo0_v64u8_0; +v128u8 foo0_v128u8_0; +v128s8 foo0_v128s8_0; +__attribute__((__vector_size__(2 * sizeof(int)))) int foo0_v64s32_0; +v128u32 foo0_v128u32_0, foo0_v128f32_0; +f32 foo0_f32_0, foo0_f128_0; +v16u8 foo0_v16u8_0; +v64u16 foo0_v64u16_1; +void foo0(__attribute__((__vector_size__(4 * sizeof(int)))) int v128s32_0, + __attribute__((__vector_size__(sizeof(long)))) long v64s64_0, + __attribute__((__vector_size__(2 * sizeof(long)))) long v128u64_0, + __attribute__((__vector_size__(2 * sizeof(long)))) long v128s64_0, + _Float16 f16_0) { + v64f16 v64f16_1 = __builtin_convertvector(foo0_v128f32_0, v64f16); + v128u32 v128u32_1 = 0 != foo0_v128u32_0; + v16s8 v16s8_1 = __builtin_shufflevector( + __builtin_convertvector(foo0_v128s8_0, v128s8), foo0_v16s8_0, 2, 3); + v128u8 v128u8_1 = foo0_v128u8_0; + v64f16 v64f16_2 = __builtin_convertvector(v128s32_0, v64f16); + __attribute__((__vector_size__(2 * sizeof(int)))) int v64u32_1 = + -foo0_v64s32_0; + __attribute__((__vector_size__(4))) signed char v32s8_1 = + __builtin_shufflevector((v16s8){}, v16s8_1, 2, 2, 3, 0); + v64u16 v64u16_2 = foo0_v64u16_1 ^ foo0_u8_0; + v64u8 v64u8_1 = __builtin_shufflevector(foo0_v64u8_0, foo0_v16u8_0, 6, 7, 4, + 7, 0, 2, 6, 0); + foo0_f32_0 *= __builtin_asinh(foo0_f128_0); + v128u8 v128u8_r = foo0_v128u8_0 + v128u8_1 + foo0_v128s8_0 + + (v128u8)foo0_v128u32_0 + (v128u8)v128u32_1 + + (v128u8)v128s32_0 + (v128u8)v128u64_0 + (v128u8)v128s64_0 + + (v128u8)foo0_v128f32_0; + v64u8 v64u8_r = ((union { + v128u8 a; + v64u8 b; + })v128u8_r) + .b + + foo0_v64u8_0 + v64u8_1 + (v64u8)v64u16_2 + (v64u8)v64u32_1 + + (v64u8)v64s64_0 + (v64u8)v64f16_1 + (v64u8)v64f16_2; + v32u8 v32u8_r = ((union { + v64u8 a; + v32u8 b; + })v64u8_r) + .b + + v32s8_1; + foo0_ret = ((union { + v16u8 a; + v8u8 b; + })((union { + v32u8 a; + v16u8 b; + })v32u8_r) + .b) + .b + + f16_0; +}