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b=GPLuXs/ppBoIrTy14dlWJCVKrPWZWgKtB5KFhf34K/bhpLxw1piZ1K1IY9zPoUgjPIjx2S893IAy8XAqMMI92vq8itxei7VADqCxAkhXR5ShXbt1HNa1GfNfJr0C0J0g5d6gaQ63dVTtuIMitwDR5GtpISTRZlBEWx8uYK4I5uE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:27:54 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:27:54 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 01/16] PCI: imx6: Simplify clock handling by using bulk_clk_*() function Date: Wed, 27 Dec 2023 13:27:12 -0500 Message-Id: <20231227182727.1747435-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: ca149d39-283f-4b11-3868-08dc07098ad4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Adds clk_names[] define in drvdata. Using clk_bulk*() api simplifies the code. Signed-off-by: Frank Li --- Notes: Change from v4 to v5 - update commit message - direct using clk name list, instead of macro - still keep caculate clk list count because sizeof return pre allocated array size. Change from v3 to v4 - using clk_bulk_*() API Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 125 ++++++++------------------ 1 file changed, 35 insertions(+), 90 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 74703362aeec7..50d9faaa17f71 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,12 +61,15 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_MAX_CLKS 6 + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; u32 flags; int dbi_length; const char *gpr; + const char *clk_names[IMX6_PCIE_MAX_CLKS]; }; struct imx6_pcie { @@ -74,11 +77,8 @@ struct imx6_pcie { int reset_gpio; bool gpio_active_high; bool link_is_up; - struct clk *pcie_bus; - struct clk *pcie_phy; - struct clk *pcie_inbound_axi; - struct clk *pcie; - struct clk *pcie_aux; + struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; + u32 clks_cnt; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -407,13 +407,18 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) { - unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); + unsigned long phy_rate = 0; int mult, div; u16 val; + int i; if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) return 0; + for (i = 0; i < imx6_pcie->clks_cnt; i++) + if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) + phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); + switch (phy_rate) { case 125000000: /* @@ -550,19 +555,11 @@ static int imx6_pcie_attach_pd(struct device *dev) static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; - struct device *dev = pci->dev; unsigned int offset; int ret = 0; switch (imx6_pcie->drvdata->variant) { case IMX6SX: - ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); - if (ret) { - dev_err(dev, "unable to enable pcie_axi clock\n"); - break; - } - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; @@ -589,12 +586,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - ret = clk_prepare_enable(imx6_pcie->pcie_aux); - if (ret) { - dev_err(dev, "unable to enable pcie_aux clock\n"); - break; - } - offset = imx6_pcie_grp_offset(imx6_pcie); /* * Set the over ride low and enabled @@ -615,9 +606,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) { switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); - break; case IMX6QP: case IMX6Q: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, @@ -631,14 +619,6 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - clk_disable_unprepare(imx6_pcie->pcie_aux); - break; default: break; } @@ -650,23 +630,9 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) struct device *dev = pci->dev; int ret; - ret = clk_prepare_enable(imx6_pcie->pcie_phy); - if (ret) { - dev_err(dev, "unable to enable pcie_phy clock\n"); + ret = clk_bulk_prepare_enable(imx6_pcie->clks_cnt, imx6_pcie->clks); + if (ret) return ret; - } - - ret = clk_prepare_enable(imx6_pcie->pcie_bus); - if (ret) { - dev_err(dev, "unable to enable pcie_bus clock\n"); - goto err_pcie_bus; - } - - ret = clk_prepare_enable(imx6_pcie->pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clock\n"); - goto err_pcie; - } ret = imx6_pcie_enable_ref_clk(imx6_pcie); if (ret) { @@ -679,11 +645,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) return 0; err_ref_clk: - clk_disable_unprepare(imx6_pcie->pcie); -err_pcie: - clk_disable_unprepare(imx6_pcie->pcie_bus); -err_pcie_bus: - clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_bulk_disable_unprepare(imx6_pcie->clks_cnt, imx6_pcie->clks); return ret; } @@ -691,9 +653,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) { imx6_pcie_disable_ref_clk(imx6_pcie); - clk_disable_unprepare(imx6_pcie->pcie); - clk_disable_unprepare(imx6_pcie->pcie_bus); - clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_bulk_disable_unprepare(imx6_pcie->clks_cnt, imx6_pcie->clks); } static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) @@ -1305,32 +1265,19 @@ static int imx6_pcie_probe(struct platform_device *pdev) return imx6_pcie->reset_gpio; } - /* Fetch clocks */ - imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); - if (IS_ERR(imx6_pcie->pcie_bus)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), - "pcie_bus clock source missing or invalid\n"); + while (imx6_pcie->drvdata->clk_names[imx6_pcie->clks_cnt]) { + int i = imx6_pcie->clks_cnt; + + imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; + imx6_pcie->clks_cnt++; + } - imx6_pcie->pcie = devm_clk_get(dev, "pcie"); - if (IS_ERR(imx6_pcie->pcie)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), - "pcie clock source missing or invalid\n"); + /* Fetch clocks */ + ret = devm_clk_bulk_get(dev, imx6_pcie->clks_cnt, imx6_pcie->clks); + if (ret) + return ret; switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, - "pcie_inbound_axi"); - if (IS_ERR(imx6_pcie->pcie_inbound_axi)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), - "pcie_inbound_axi clock missing or invalid\n"); - break; - case IMX8MQ: - case IMX8MQ_EP: - imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); - fallthrough; case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; @@ -1353,10 +1300,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) case IMX8MM_EP: case IMX8MP: case IMX8MP_EP: - imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(imx6_pcie->pcie_aux)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), - "pcie_aux clock source missing or invalid\n"); imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) @@ -1372,14 +1315,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) default: break; } - /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */ - if (imx6_pcie->phy == NULL) { - imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); - if (IS_ERR(imx6_pcie->pcie_phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), - "pcie_phy clock source missing or invalid\n"); - } - /* Grab turnoff reset */ imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); @@ -1477,6 +1412,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, }, [IMX6SX] = { .variant = IMX6SX, @@ -1484,6 +1420,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}, }, [IMX6QP] = { .variant = IMX6QP, @@ -1492,40 +1429,48 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, }, [IMX7D] = { .variant = IMX7D, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx7d-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, }, [IMX8MQ] = { .variant = IMX8MQ, .gpr = "fsl,imx8mq-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx8mm-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx8mp-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", + .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, }; 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b=ZbBE7JFVhJO6wGoMxXxHklAOobo1bWHxn90SPuTnbIzYSt+AtpA0ydbzybcbKl6Vk5ZKlbaus3k4c+0cVRqsBoPfcFXfCPSIWukE1shUuTMbfdMwNFOTDKVkaOeuIs5vxVRgz/WCdEIrP/+iCGPY3vHO+PWtzxmRfk4UQn0uUb0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:00 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:00 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 02/16] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Date: Wed, 27 Dec 2023 13:27:13 -0500 Message-Id: <20231227182727.1747435-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: 4433da78-0951-4cd1-87ad-08dc07098e0f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling phy. Signed-off-by: Frank Li --- Notes: Change from v4 to v5: - none, Keep IMX6_PCIE_FLAG_HAS_PHY to indicate dts mismatch when platform require phy suppport. Change from v1 to v3: - none drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 50d9faaa17f71..4d620249f3d52 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -60,6 +60,9 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) + +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) #define IMX6_PCIE_MAX_CLKS 6 @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (ret) return ret; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx6_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + "failed to get pcie phy\n"); + } + switch (imx6_pcie->drvdata->variant) { case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), - "failed to get pcie phy\n"); - break; default: break; @@ -1444,13 +1449,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, @@ -1462,12 +1469,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, From patchwork Wed Dec 27 18:27:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183537 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1599224dyb; Wed, 27 Dec 2023 10:29:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4zJFSxzxe4Ta4BzyB+VOfS1usdaszg2GWN7ZA7lmfL8U65ibJL+X0124DR7KiopIZrvYe X-Received: by 2002:a05:6358:341b:b0:170:6675:a50a with SMTP id h27-20020a056358341b00b001706675a50amr7869875rwd.36.1703701745803; Wed, 27 Dec 2023 10:29:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701745; cv=pass; d=google.com; s=arc-20160816; b=CBRRbulitXB0RVOX8v9VV6tp9hAXxsq1lp52q1VJUMzLY6mrHgKxsfyW5Z8FZ4NUeM So7u0bIjjcWHyS2duv5dmgqsxyJnigxzMqoWApfAd6zdDrnx+aptRBwPeMzHv4Jw9gAD YDh7rxh6HLFm9+ray4AjVxxQIzdxkUxQBhAF22cs4FTuitpE9cBhczGXnvbd0p7POwhA OpGkNnobo+JeeWxIY8FgQ7hZhO4TT+f9yUr9IZmS5No0J8BDK5oKwj7MI1cq3n2s6r6w Dv4eVSQyAFvmtV1nm0OivhIOUvA3CTS1nRCh6v387JEKp6D7BMOtW7S4YCdja+rHDI2O x6iQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=qx01HvuG0xZ04g5Qs1emA81XcCk2ClpOFDJT/IqUaUE=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=pagiZo4+gCvk5qRVFqoxXPRaaVE1ongqj08Sn6YWIbKSuuY0aYpccM6e43y1L3u6p9 J0Nk3UqiXUuzs8jDnTuAitUGwd4dWeflO2GT+FpTNrYZv8JuriDJyPdyzSiNZA6S8u4v xmykAURhBs2jw4Lsql9jUJcF+T6mKngKLiusPd9eKv4vyphZ7z7P/uJzlta+BiBg8tLo e50LQHsFYGqrDhqPcFGMM9OOkGX4+JuzaeJfWi8u6MpTGNFR08WgNOUg6B7iQlnl+VeK Gje+ha9xtFKVKaMNK4E3c8zP8rmezjcBMczxK+VIisRkNLCGXuC8rnylwKipBKxtKmVn uM0A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=fgO6asKJ; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12199-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12199-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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b=fgO6asKJ67uEFxYYXUVxzmsou9sp7JmdpAYsLl2vhOWiOgx0k/AVDzVtXdq3ar1QCI9aEq5h4xa1gY+7lfeucosH4M8VM65shLEEWIPKo3jRngJ3AFMZiCawSA800uTg3A1UpE/gRP8vAbscjRPNd42vIOw++GpTiavCDP5tk6A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:05 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:05 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 03/16] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Wed, 27 Dec 2023 13:27:14 -0500 Message-Id: <20231227182727.1747435-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: b6e641f5-cfe8-485b-120b-08dc07099146 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Signed-off-by: Frank Li --- Notes: Change from v4 to v5: - Add Mani's Reviewed-by tag - Fixed MQ_EP's flags Chagne from v3 to v4: - none Change from v2 to v3: - add Philipp's Reviewed-by tag Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. drivers/pci/controller/dwc/pci-imx6.c | 108 ++++++++++---------------- 1 file changed, 41 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 4d620249f3d52..294f61a9c6fd9 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,6 +61,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) #define IMX6_PCIE_FLAG_HAS_PHY BIT(3) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -661,18 +663,10 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + reset_control_assert(imx6_pcie->pciephy_reset); + reset_control_assert(imx6_pcie->apps_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); - break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -693,6 +687,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -706,14 +702,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; case IMX7D: - reset_control_deassert(imx6_pcie->pciephy_reset); - /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -745,11 +737,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -796,16 +784,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -819,16 +802,11 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1287,36 +1265,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1438,31 +1404,39 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, }, [IMX8MQ] = { .variant = IMX8MQ, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, From patchwork Wed Dec 27 18:27:15 2023 Content-Type: text/plain; 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b=CChl6rWYme68bDkgcuNBSDMT/MFXYj8fXVbbQ3KSr+YZ1GhsbGKodEEex7fVz3Wbad/WCNuA44NuIxI9kBU0ulMfJyY/I1AFiXwTe2h9QvXGvG1XI3+ta1qEdKFRdfqJtgoYHamMJT3W+p2MHuk+ODYaZDYpQLkzgz34ihlkQ5k= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:10 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:10 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 04/16] dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ Date: Wed, 27 Dec 2023 13:27:15 -0500 Message-Id: <20231227182727.1747435-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: 897c047d-ba04-4f56-d7e4-08dc07099477 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Adds "linux,pci-domain" as required proptery for iMX8MQ to indicate pci controller index. This adjustment paves the way for eliminating the hardcoded check on the base register for acquiring the controller_id. ... if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; ... The controller_id is crucial and utilized for certain register bit positions. It must align precisely with the controller index in the SoC. An auto-incremented ID don't fit this case. The DTS or fuse configurations may deactivate specific PCI controllers. Signed-off-by: Frank Li Reviewed-by: Rob Herring --- Notes: Change from v5 to v6 - rework commit message to explain why need required and why auto increase id not work Change from v4 to v5 - new patch at v5 .../bindings/pci/fsl,imx6q-pcie-common.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index d91b639ae7ae7..8f39b4e6e8491 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -265,6 +265,17 @@ allOf: - const: apps - const: turnoff + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-pcie + - fsl,imx8mq-pcie-ep + then: + required: + - linux,pci-domain + additionalProperties: true ... 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If there are more than 2 slots, compared logic will become complex. "linux,pci-domain" already exist at dts since commit: commit (c0b70f05c87f3b arm64: dts: imx8mq: use_dt_domains for pci node). So it is safe to remove compare basic address code: ... if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; ... Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v3 to v4 - remove compare basic address logic Change from v2 to v3 - none Change from v1 to v2 - fix of_get_pci_domain_nr return value check logic drivers/pci/controller/dwc/pci-imx6.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 294f61a9c6fd9..332c392f8e5bc 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -40,7 +41,6 @@ #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) -#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) @@ -1279,13 +1279,14 @@ static int imx6_pcie_probe(struct platform_device *pdev) "Failed to get PCIEPHY reset control\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - default: - break; - } + /* Using linux,pci-domain as PCI slot id */ + imx6_pcie->controller_id = of_get_pci_domain_nr(node); + /* If there are not "linux,pci-domain" in dts file, means only 1 controller */ + if (imx6_pcie->controller_id == -EINVAL) + imx6_pcie->controller_id = 0; + else if (imx6_pcie->controller_id < 0) + return dev_err_probe(dev, imx6_pcie->controller_id, + "linux,pci-domain have wrong value\n"); /* Grab turnoff reset */ imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); From patchwork Wed Dec 27 18:27:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183540 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1599621dyb; Wed, 27 Dec 2023 10:30:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9vaIRuvI4YbOwgv7y+HjDRFP2cPYXyDmjNsxYw9v4PXQIU53ipQ3tuXOSnmzePnrt172N X-Received: by 2002:a17:906:144f:b0:a27:59a2:93ff with SMTP id q15-20020a170906144f00b00a2759a293ffmr261595ejc.161.1703701801480; Wed, 27 Dec 2023 10:30:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701801; cv=pass; d=google.com; s=arc-20160816; b=qTFD4Iw/oHYZN6h0w3fFh1X6eMhU2OC+fiqhn7Wrwr+LPybeIKfTmp040nOK6d7c9P 2Fm7b/7GAL9vHwTmR4ewvmtJtNY/PVRuYwdrhQImFr3lLk/QLMpkhU7CjKVx5FtWegPd krfkVhT0Fd1I3CGwFm/r2GXiJvjetm530l2QGxSdCJgU/g9soHVa2HpvHvQthfc9K0+J Lvn4me6h6aKE+KtrWziBZUx1VVtu+ZP7+kem4U3Ek68V4OK0bRArVV+IXCioGE9lJ8EN 4kFdR1U08h8H1tbRIzSKD002PG+ilZshWQV+GLgUkSIoWTvPTq04tI9CgWxBXgXqtQo8 mHNQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=K0z9pcHLjdXiH6wD7qmDtLqSR+u24DFRcxKpgzuOjSs=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=rIwlN5s4phg0icWjhX6YHDVOZwN6WQGz+fAZBYM3rq/rA4c/Qdjl2D0YaAsE27L7tx v5/2lTXzDey3lHMnqYRrTsQsWXt+sBg1ECSltZu1UomCcUbnsczrjtnIjsRpw+VxIBG2 TwEibSTBryqfXe1m94II4+/lKzepj7JLkK5UQCvyAgQ/O9fJqwflQsAyFKV/UBgfHUYa du8Qtc5tcFwsAbmtfdgz91yQI2Lspobwx9RapDw/29SFnexfXfjjO/Bxh7lvyKGxnlhR Yh8+Q6+O443uFzr7a/l8a/iovO+bU6ZLYAqOxchisLmHjTN4usNyY/0ZRjy+SMO9xYzx MG3Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=CcjyTLLu; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12202-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12202-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++++--------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 332c392f8e5bc..588bfb616260e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -75,6 +75,8 @@ struct imx6_pcie_drvdata { int dbi_length; const char *gpr; const char *clk_names[IMX6_PCIE_MAX_CLKS]; + const u32 ltssm_off; + const u32 ltssm_mask; }; struct imx6_pcie { @@ -775,18 +777,11 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) static void imx6_pcie_ltssm_enable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; - switch (imx6_pcie->drvdata->variant) { - case IMX6Q: - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, - IMX6Q_GPR12_PCIE_CTL_2); - break; - default: - break; - } + if (drvdata->ltssm_mask) + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, + drvdata->ltssm_mask); reset_control_deassert(imx6_pcie->apps_reset); } @@ -794,17 +789,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) static void imx6_pcie_ltssm_disable(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; - switch (imx6_pcie->drvdata->variant) { - case IMX6Q: - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, 0); - break; - default: - break; - } + if (drvdata->ltssm_mask) + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, + drvdata->ltssm_mask, 0); reset_control_assert(imx6_pcie->apps_reset); } @@ -1385,6 +1374,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX6SX] = { .variant = IMX6SX, @@ -1393,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}, + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX6QP] = { .variant = IMX6QP, @@ -1402,6 +1395,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, + .ltssm_off = IOMUXC_GPR12, + .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, }, [IMX7D] = { .variant = IMX7D, From patchwork Wed Dec 27 18:27:18 2023 Content-Type: text/plain; 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b=E0rxngrkuTxOs272ubqlVHHz13F13LfsDOeRgmgB/fQZdTwSO+D99lsM95pY3uI0lhHGEXyV/a1PIRxx73NSFTRxxQNpB91+VAOsmsyB1KuenlevU/6rx6CKs011bv4dj3ChSUx1X9bJS/FAFwG5OWiLyV5Eh8M+lnQqA9F2VrQ= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:26 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:26 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 07/16] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask Date: Wed, 27 Dec 2023 13:27:18 -0500 Message-Id: <20231227182727.1747435-8-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a9706ab-457c-4b87-a1b5-08dc07099de4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: Change from v2 to v3 - none Change from v1 to v2 - use ffs() to fixe build error. drivers/pci/controller/dwc/pci-imx6.c | 60 ++++++++++++++++++--------- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 588bfb616260e..717e8fa030deb 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -68,6 +68,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_MAX_CLKS 6 +#define IMX6_PCIE_MAX_INSTANCES 2 struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -77,6 +78,8 @@ struct imx6_pcie_drvdata { const char *clk_names[IMX6_PCIE_MAX_CLKS]; const u32 ltssm_off; const u32 ltssm_mask; + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; }; struct imx6_pcie { @@ -174,32 +177,25 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { - unsigned int mask, val, mode; + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + unsigned int mask, val, mode, id; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) + if (drvdata->mode == DW_PCIE_EP_TYPE) mode = PCI_EXP_TYPE_ENDPOINT; else mode = PCI_EXP_TYPE_ROOT_PORT; - switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - if (imx6_pcie->controller_id == 1) { - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, - mode); - } else { - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - } - break; - default: - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - break; - } + id = imx6_pcie->controller_id; + + /* If mode_mask[id] is zero, means each controller have its individual gpr */ + if (!drvdata->mode_mask[id]) + id = 0; + + mask = drvdata->mode_mask[id]; + /* FIELD_PREP mask have been constant */ + val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) @@ -1376,6 +1372,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6SX] = { .variant = IMX6SX, @@ -1386,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}, .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6QP] = { .variant = IMX6QP, @@ -1397,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX7D] = { .variant = IMX7D, @@ -1405,6 +1407,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1412,6 +1416,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM] = { .variant = IMX8MM, @@ -1420,6 +1428,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP] = { .variant = IMX8MP, @@ -1428,6 +1438,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, @@ -1436,6 +1448,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1443,6 +1459,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1450,6 +1468,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, }; 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b=Ajq+igAtQLweR98V3Wr5soikvRCUCb08o/lJm830zZ+iqcEA2h7KVicHJghxHqLD4T76iAZkkFI81hkRnAqCHJbOtCZNeYHb4HUVKKib3PEK/XxxYuhRTq7S6XkHuYgCQZ/X9VESLEO4eSUrZZGPp/4GXxdEO3vc26bUe+nbjpY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:32 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:32 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 08/16] PCI: imx6: Simplify switch-case logic by involve init_phy callback Date: Wed, 27 Dec 2023 13:27:19 -0500 Message-Id: <20231227182727.1747435-9-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: ed89c456-39ce-47a5-7b77-08dc0709a10a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: change from v1 to v4: - none drivers/pci/controller/dwc/pci-imx6.c | 135 ++++++++++++++------------ 1 file changed, 71 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 717e8fa030deb..d66a2db53bdb7 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -69,6 +69,9 @@ enum imx6_pcie_variants { #define IMX6_PCIE_MAX_CLKS 6 #define IMX6_PCIE_MAX_INSTANCES 2 + +struct imx6_pcie; + struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -80,6 +83,7 @@ struct imx6_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + int (*init_phy)(struct imx6_pcie *pcie); }; struct imx6_pcie { @@ -323,76 +327,69 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) return 0; } -static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) { - switch (imx6_pcie->drvdata->variant) { - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - /* - * The PHY initialization had been done in the PHY - * driver, break here directly. - */ - break; - case IMX8MQ: - case IMX8MQ_EP: - /* - * TODO: Currently this code assumes external - * oscillator is being used - */ + /* + * TODO: Currently this code assumes external + * oscillator is being used + */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); + /* + * Regarding the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the + * VREG_BYPASS should be cleared to zero. + */ + if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) regmap_update_bits(imx6_pcie->iomuxc_gpr, imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_REF_USE_PAD, - IMX8MQ_GPR_PCIE_REF_USE_PAD); - /* - * Regarding the datasheet, the PCIE_VPH is suggested - * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the - * VREG_BYPASS should be cleared to zero. - */ - if (imx6_pcie->vph && - regulator_get_voltage(imx6_pcie->vph) > 3000000) - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_VREG_BYPASS, - 0); - break; - case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX8MQ_GPR_PCIE_VREG_BYPASS, + 0); + + return 0; +} + +static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + return regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); - break; - case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_RX_EQ_MASK, - IMX6SX_GPR12_PCIE_RX_EQ_2); - fallthrough; - default: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, +} + +static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); - /* configure constant input signal to the pcie ctrl and phy */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); - break; - } + /* configure constant input signal to the pcie ctrl and phy */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6Q_GPR12_LOS_LEVEL, 9 << 4); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN1, + imx6_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, + imx6_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, + imx6_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_FULL, + imx6_pcie->tx_swing_full << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_LOW, + imx6_pcie->tx_swing_low << 25); + return 0; +} - imx6_pcie_configure_type(imx6_pcie); +static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); + + return imx6_pcie_init_phy(imx6_pcie); } static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) @@ -903,7 +900,11 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) } imx6_pcie_assert_core_reset(imx6_pcie); - imx6_pcie_init_phy(imx6_pcie); + + if (imx6_pcie->drvdata->init_phy) + imx6_pcie->drvdata->init_phy(imx6_pcie); + + imx6_pcie_configure_type(imx6_pcie); ret = imx6_pcie_clk_enable(imx6_pcie); if (ret) { @@ -1374,6 +1375,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6_pcie_init_phy, }, [IMX6SX] = { .variant = IMX6SX, @@ -1386,6 +1388,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6sx_pcie_init_phy, }, [IMX6QP] = { .variant = IMX6QP, @@ -1399,6 +1402,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx6_pcie_init_phy, }, [IMX7D] = { .variant = IMX7D, @@ -1409,6 +1413,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .init_phy = imx7d_pcie_init_phy, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1420,6 +1425,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM] = { .variant = IMX8MM, @@ -1452,6 +1458,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, From patchwork Wed Dec 27 18:27:20 2023 Content-Type: text/plain; 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Acked-by: Rob Herring Signed-off-by: Frank Li Acked-by: Manivannan Sadhasivam --- Notes: Change from v6 to v7 - rewrite git commit message by using simple words Change from v5 to v6 - rewrite git commit message and explain why remove it safely. - Add Rob's Ack Change from v1 to v4 - new patch at v4 .../bindings/pci/fsl,imx6q-pcie-common.yaml | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index 8f39b4e6e8491..a284a27c5e873 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -150,22 +150,6 @@ allOf: - {} - const: pcie_phy - const: pcie_aux - - if: - properties: - compatible: - not: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx8mq-pcie - - fsl,imx6sx-pcie-ep - - fsl,imx8mq-pcie-ep - then: - properties: - clocks: - maxItems: 3 - clock-names: - maxItems: 3 - if: properties: From patchwork Wed Dec 27 18:27:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183544 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1600308dyb; Wed, 27 Dec 2023 10:31:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/4fi0NPYepVxyLSrgzfmr6822o1H9MIiN1OVOxBCcUOaKvY6sy4282X/znJu+xnwLxol3 X-Received: by 2002:a17:906:5187:b0:a26:f5e1:ea96 with SMTP id y7-20020a170906518700b00a26f5e1ea96mr2053488ejk.131.1703701869374; Wed, 27 Dec 2023 10:31:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701869; cv=pass; d=google.com; s=arc-20160816; b=sA5YoUzrT0NYTpS8gDfO5kDmqIgjemaBK8y6tTh2EI6ujgjJIJHtXxtKyKVyCTXQwX kqrVUFMwZg50c954/fd+QQhtjuloQWsa9CbuzJ44R7i+9lOwmiZeIFCdZS0zV6ZVN3Hw UGZepISOuNwQdtzjf6p5FsnGlaLhjV6zCw7EqSswlq92/XOOs9JO9LswWfdG4pm+C6mH yqRejFvvEaFEcAcfSO0Grqs1K1yTm7ZCnvcUlDvSaxNXexjjcSBF9mSd6Bd0Ue4WXOgt RZxga+HHrCR5T93DVRAhBrfNus1tw19X9J1JhN4DWRwvStHOe2RaJqADkfHIKjld1rRG w75w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kzT9xQDWHyPkja52vLXfmsmvSsExDWiRMIup4s/pdkY=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=qrR3Mh3RldoeBV24/J34VCTCDniOOD0XRxY66+S4nCf0w+BXYEfg1+++q61YWLBZtR r+wFPvUlSbXk7HaQ/4BS7kmYlTc+Q8vlYQu9NBeCaC1jrXcKdayiMRf80hMpicmT0iqQ vgmY7InBR4REZCJSWyAC37DyAqJeGSPp8bBV6ydEvYnvHFl3gf/CeuOVJLnTihV2Kq9V J9rkWJS56bKfbUcBKNsECz4twBmXcG3Mbn/Rl60jgxAHddc5/oc4kw7zRGSszfKlZG89 XMGxy82/i5C0L+hG2ccMzgCRDWzqKL5QL+kGzSGhpLeQHxCZYa/0T9q9EHqCnxhCnQ7b 32cQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=JrKaOuiD; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12206-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12206-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Needn't duplciate here. Add 'if' check for existed compatible string to restrict reg and reg-names. This prepare to add new compatible string with difference reg-names sets. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li Acked-by: Manivannan Sadhasivam --- Notes: Change from v6 to v7 - add Krzysztof's review tag Change from v5 to v6 - Add if check for existed compatible string Change from v4 to v5 - add Rob's Acked Change from v1 to v4: - new patch at v4 .../bindings/pci/fsl,imx6q-pcie.yaml | 30 ++++++++++++------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 81bbb8728f0f9..eeca6b7b540f9 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -30,16 +30,6 @@ properties: - fsl,imx8mm-pcie - fsl,imx8mp-pcie - reg: - items: - - description: Data Bus Interface (DBI) registers. - - description: PCIe configuration space region. - - reg-names: - items: - - const: dbi - - const: config - clocks: minItems: 3 items: @@ -90,6 +80,26 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: dbi + - const: config + - if: properties: compatible: From patchwork Wed Dec 27 18:27:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183550 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1605234dyb; Wed, 27 Dec 2023 10:42:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IF/CaoniU/8mfgR96lUhOTXsQNgLifRiEpS3HPUiLT5XTbyhEi8nHdF4/iDoJZFYj2xIAst X-Received: by 2002:a05:6a21:a5a1:b0:195:e329:c0cb with SMTP id gd33-20020a056a21a5a100b00195e329c0cbmr3880243pzc.50.1703702528965; Wed, 27 Dec 2023 10:42:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703702528; cv=pass; d=google.com; s=arc-20160816; b=gkZq7AHvPXud3oqR5xK7kRRGY8ztcJPtFLNxcL5sCfy/2MCst4XXy1Jdl/Oe+oOVqf +FxaJ84ob+LJtPgG7fsPsXs6Q24dufPJlOfJ4R5NEVr/5KBIL3elSrxwXfICeuKDvnwT CiHLyGPFvjFv5BRBvJxnSTOz0qA9ETke7Y58qSTqkcoR9BX2Zgh0rUsV3AVQRq2z3hrp uucaMbaX6n7e7/5o77oUhGEYP4orGkGA1oqs8GeLypqrWQZ4X00zVOEFb4E9a25kHoRv wYz6iaoolNGY+S97OBmKS3qyv9hMtwQWVmPIUkBT1U8Uro6QBuHz6lCgMGwCdqWEZ6J/ hpPQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=JbWvqYteYvr1zWHZKqAAJdl2+jva0a7FHdVtrlJj7y8=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=WYZRsI5NFVTBQI2+EZslksyAJcAB5EOsNTMxu1eObyPe4APEg9kProSIGmeK0WZeUc YVbgrq7vzcIiLseBJ2m5E3q0nTJrm7uzl42N6CBs43Y8EA3jmhz0iUFY+XHGVytELo3X G0oi36XwjDNdk7nDLPv1NLSIGRhAysa7TPJGQGtQrPQziHGy3vrpWXtT9Wgkjsq4VKgB cMPwngk5W2D5gsUtuVhYqbJY7iPsWxkP/BzhYDVKjBmfw9uY32ZDpCraIOVX4UR6rM/l nMOi6eWc3t5UU86vm3vFjY5uY0lg5pOlO1gvdVUY1Is3ZgZuynbYrTmtZ5mSVJYvQtYR UN1g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b="M/WXM2n0"; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12207-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12207-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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b=M/WXM2n0NHXDsxTLeqZVsODyaMbmW76ymg2ahzncyP7YnIl5o0jju3xPY+RAjH59bhJDVsWExlXduBLp+G2oiy4rz3S9y1UbVcNgnPlSObD7wSVWEjMcVg87vZHHwiX0O8mSwyvzpSf3Uc8aAZtL9SuDOvk4q2LJ0MQ2uIHuwWg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:48 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:47 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 11/16] dt-bindings: imx6q-pcie: Add imx95 pcie compatible string Date: Wed, 27 Dec 2023 13:27:22 -0500 Message-Id: <20231227182727.1747435-12-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c2d6d39-4fa5-4663-a77e-08dc0709aa79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add "atu" and "app" to reg-names. Signed-off-by: Richard Zhu Signed-off-by: Frank Li Reviewed-by: Rob Herring --- Notes: Change from v6 to v7 - Added my sign off Change from v5 to v6 - move atu and app after config Change from v2 to v3 - Remove krzy's ACK tag - Add condition check for imx95, which required more reg-names then old platform, so need Krzy review again, Change from v1 to v2 - add Krzy's ACK tag .../bindings/pci/fsl,imx6q-pcie-common.yaml | 1 + .../bindings/pci/fsl,imx6q-pcie.yaml | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index a284a27c5e873..1b63089ff0aee 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -207,6 +207,7 @@ allOf: - fsl,imx6sx-pcie - fsl,imx6q-pcie - fsl,imx6qp-pcie + - fsl,imx95-pcie - fsl,imx6sx-pcie-ep - fsl,imx6q-pcie-ep - fsl,imx6qp-pcie-ep diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index eeca6b7b540f9..8b8d77b1154b5 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -29,6 +29,7 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie + - fsl,imx95-pcie clocks: minItems: 3 @@ -100,6 +101,23 @@ allOf: - const: dbi - const: config + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: dbi + - const: config + - const: atu + - const: app + - if: properties: compatible: @@ -121,6 +139,7 @@ allOf: compatible: enum: - fsl,imx8mq-pcie + - fsl,imx95-pcie then: properties: clocks: From patchwork Wed Dec 27 18:27:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183549 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1604941dyb; Wed, 27 Dec 2023 10:41:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHRF71k4Uz6if9mcjpgxDbTwjFLlNd+RS4foYvhmm2jadh6RKaNyVP5XYPOYtPToS1DxUXj X-Received: by 2002:a05:6e02:15c2:b0:35d:59a2:6909 with SMTP id q2-20020a056e0215c200b0035d59a26909mr13829304ilu.54.1703702488783; Wed, 27 Dec 2023 10:41:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703702488; cv=pass; d=google.com; s=arc-20160816; b=vF7w8pfUKIjj4MnWHfltH+pqOL9EAZH+32IHAsbXh5AKB+W49Uh81SYxvvxERBW6eK XRIuPfvvgjREWz0Rt8zTjIM7qeTi6+12TpAt/jABvlbuNwLrn6F66VWA9MpfKcHzsLnX jintxfuqDgG1a2cT+VYzCtk4z8fsPPaYm3cw+iKUa4PNixLy3/NO+SIp/7ggMMDcy16x bBQOaT7GzlRcdVLT//wop3BeM/dp0TUmI8nKYbL/I7q5uAJvFSEnYfOiYVYd0tQDR2hQ sEL2UWCjFFPVZkXTf9f1HyAsD00DiWrK0uydmUmk41mg32Ga8C3k3LRqFHeFE1PoLEYi iFgA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Z4dgn8M+Jk4NmcR2dQdTU9AyWvLkmV12/ZAFatSQuWg=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=xqDKrEnx48qCBdFE/v3+M9Tw3WiKHVGAG0mWUUy4U1iQ+yqdHFamcwVxj9RdAliH4r dlB/5s+/XjUq+tUaJFo3ipOzV7EVoRYZ5CupTYvugV4xnguRUPym25iKdCnr8NR6IER2 9KgpSGBUrWVwAjjiPRjEa0CFfoF+DS93vOJWJqhGOoIGdYGyN5hXqmUhEQGxmot6Y/37 lR8WzY7Sk/9GFh67SxwnauOn6B40flPwZHuS8jL1D+04mK43gsjvondqhRcXrut+wpaT mSAyJTAX61pxRooivP72fdQ7HVMPu8IlHR42Hiemp15U9/+zxzHxX7RS1jkb90+R15jx 5CeQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=XbsupIrF; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12208-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12208-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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b=XbsupIrFvDKzvAd5+co88prEJ2nQA2TQA2F15CuukUdNlyLk+ToFWk1ta8RbiJp9h+tvrXX8zdyqp2wTuNDoptZvabcUnvJVcwE334ZlPiVZ7rh3OLSz0qMg6cda9S+TzH6XZirwi60ZCCmHRsoeTVCTcM6bdosd9OiPWva76vA= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:53 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:53 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 12/16] PCI: imx6: Add iMX95 PCIe support Date: Wed, 27 Dec 2023 13:27:23 -0500 Message-Id: <20231227182727.1747435-13-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: 63f1a733-7a25-423f-816c-08dc0709ad9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- Notes: Change from v1 to v3 - none drivers/pci/controller/dwc/pci-imx6.c | 90 +++++++++++++++++++++++++-- 1 file changed, 85 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index d66a2db53bdb7..9e60ab6f1885a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -42,6 +42,25 @@ #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) +#define IMX95_PCIE_PHY_GEN_CTRL 0x0 +#define IMX95_PCIE_REF_USE_PAD BIT(17) + +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10 +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30) + +#define IMX95_PCIE_SS_RW_REG_0 0xf0 +#define IMX95_PCIE_REF_CLKEN BIT(23) +#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) + +#define IMX95_PE0_GEN_CTRL_1 0x1050 +#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) + +#define IMX95_PE0_GEN_CTRL_3 0x1058 +#define IMX95_PCIE_LTSSM_EN BIT(0) + +#define IMX95_PE0_PM_STS 0x1064 +#define IMX95_PCIE_PM_LINKST_IN_L2 BIT(14) + #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) enum imx6_pcie_variants { @@ -52,6 +71,7 @@ enum imx6_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX95, IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, @@ -63,6 +83,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_PHY BIT(3) #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) +#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } +static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) +{ + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_PHY_CR_PARA_SEL, + IMX95_PCIE_PHY_CR_PARA_SEL); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_PHY_GEN_CTRL, + IMX95_PCIE_REF_USE_PAD, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_CLKEN, + IMX95_PCIE_REF_CLKEN); + + return 0; +} + static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; @@ -579,6 +618,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; case IMX7D: + case IMX95: break; case IMX8MM: case IMX8MM_EP: @@ -696,10 +736,19 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + u32 val; reset_control_deassert(imx6_pcie->pciephy_reset); switch (imx6_pcie->drvdata->variant) { + case IMX95: + /* Polling the MPLL_STATE */ + if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + IMX95_PCIE_PHY_MPLLA_CTRL, val, + val & IMX95_PCIE_PHY_MPLL_STATE, + 10, 10000)) + dev_err(dev, "PCIe PLL lock timeout\n"); + break; case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle @@ -1281,12 +1330,32 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(imx6_pcie->turnoff_reset); } + if (imx6_pcie->drvdata->gpr) { /* Grab GPR config register range */ - imx6_pcie->iomuxc_gpr = - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) { - dev_err(dev, "unable to find iomuxc registers\n"); - return PTR_ERR(imx6_pcie->iomuxc_gpr); + imx6_pcie->iomuxc_gpr = + syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); + if (IS_ERR(imx6_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + "unable to find iomuxc registers\n"); + } + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { + void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); + + if (IS_ERR(off)) + return dev_err_probe(dev, PTR_ERR(off), + "unable to find serdes registers\n"); + + static struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + + imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(imx6_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + "unable to find iomuxc registers\n"); } /* Grab PCIe PHY Tx Settings */ @@ -1447,6 +1516,16 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, + [IMX95] = { + .variant = IMX95, + .flags = IMX6_PCIE_FLAG_HAS_SERDES, + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | @@ -1488,6 +1567,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, + { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, From patchwork Wed Dec 27 18:27:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183547 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1601248dyb; Wed, 27 Dec 2023 10:32:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IGkb8jfKgmW8Me08V4+/UYIbg9w9Lvz68J5NRaByMzQLXKqyz2Y0pXmNuWBkFg1HRnlmvy/ X-Received: by 2002:a17:90a:bf08:b0:28b:d426:633 with SMTP id c8-20020a17090abf0800b0028bd4260633mr5101709pjs.96.1703701978886; Wed, 27 Dec 2023 10:32:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701978; cv=pass; d=google.com; s=arc-20160816; b=Bl3KwMWDAFZK80WBLn+CgGAMqBYERXmuOs3k3bigulWEaiyukk1WfSvuGencH/uPDl 82esI5O6cLPUd9FHXtn0dT5UARufxAbax0Ku4XBHnQKy9H2lSN8PTcjAx1bPG90nV1z4 Zg/AQ91c4ca3djmch33ZEH0iFeCm4smwXA2bNakRX5mcHIk1qDrTdwg+Jg36QX+dC8sO ZJuRxvZ8CcWsphHP5oaWUnxbL/sPosJVMPnIFCiyTdVpXFeCZEkriA4j3jYgC5sjKclL 9RXFB50OYJOII5z7d6iuefIcibxUkEml/UR4vjTrhax2YzS/MTRbwM9ljOB7TXszxhk6 IazA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pouqXGwboygEHGEyEH0UcBGMdn3xWvJFgCWv7qfcMzg=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=EbZSqL8g2eHOTG5M8NhEwZRF8+NjpL9AOBCKx+XXdvr6PZbJSZtYusYcyQ1+abnMwc 3Y7PXVrrc4cEK+i/k4tIhpXqnP3YCqEIm7BTst1Vrvoq30sSLOWHxjJB0TUw3SEGkbFD IXPCTplu3xHpNqDj9RKkoNx4Lva6rXvN9n+68tT5l+v/Pi7tWxapalTcHPSfqMyWTWOt bU08iq0HVpKRL4I0UngKYr37j7ybV6M6ONCV8tHQ8gPoMXHSFV4zYJPu0uwEQzKC8fIa bsc5AngdgP3HwGiGsdhscxnLVrotvwk4/eFYYXig5xKPQ9GdCodktHe3yCzuiP/B07Yn ZjPw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b="e/QdcYeI"; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12209-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12209-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fCnbbb39zlxNL9IHmBiOxmmOFakr+IqIZSNgXEqK7UZsapjaOK63gyC912TgYQFA9wiw0/tJaem8x5NFm5IKklY0ySDsElED/2jAzYRfOoy8lsJLfOq/e4POG0yukyuSOp0En17/OICfotDy/yuJXQ8bJjI+jAFiBb2yAf4Gs77mgFEuJ/NT40YMxA02DvlFguW0w9GS5OxsoZPP5+6LpK20tS9oJuqewcUtFN0ZwR6eAsEbm09wGTU55ngwAQkEjStFs4bR9/rcg1MJc9qh3h3inFX+mBsjkROXNoLT3CbBSxeomi+ruPaRHmO2E4Z5H6eVNt02cZCOlGA2Njl6vNwQFhd+KEHrlGRm/iMaJIQp9LxZsu0pg+HJl9POtpsi0nnlSDZGI+ef0ILU9zPN19YCJU1k+w4n7JGSxLZQrYHp2lvMVaYIZ/W2xcxIbSQyXPm7afjixIMXu3gYzTBU0lNKEM0EGYIk1PyOIU7yHcS4JDHw7Kt5vt0sK69pEJqi/W5/O3ER//bM+yWD883uY4GxplRTp3OfBnDUVRSlGqLfTNQQxPDRHql8+YUOoDI+yfwglgzN+G989abUBtu/QTGscpGlBGGSxSOBVaEUXi4DrR1CUSn3M7LGRA0UOBMSWLUb2YVhEhlZelMn7vblcy4SI22uUPtj+9TVJAWE0+bN9r43myl0txRcbndtxMPn8Op/hCTsFSBgSPKG9j0To1DMJ7L/ijNSjtg44C2k1/8STorJIC7WXDxECOCxGwT65BYhb9r04T0/c9uMlbcbRvUdj9yJM7ZPPeiauBFTVmImmP1LNJCbLRjN2mwWo+bGMs5hG4UTrop62yWJDqzfF1aXH1Il0mDrhBM0uI5rW2mhVLqp7gjzOP+z+GkdzQRDTjQNX0WBvmbnNlJgU6XbJIt45WlXC/4VeH2CUX4T1Z2ZVOpQPQD6aCksP9t631rTcSEsk+07NBw3Lb0A7sfqy7zg8Si7niEywY8ZE/080zGevhDF8xdLSwn60Qm4DMo/ubTWcgn0qlqCqWQ2Kz3NeFW0x+Th0z38uH3qhWCs/MPhTCot0b/IWeLK3l4Sw132GBWbJZs/GlqVA2vPzRouvN5YGPpbwS/wMEyOKXvdut5mzK8NgPAIIMIFYbnQYty8FMXpPCPSlfq/Q6UTEE/62j6oEm0ys5JqXyCweSt0BO3fdXv67IOxQhbLiwWhrwnZMfoU9337+Nte9PUTEhX67fb9eE/2u2pRDNcXkNCv+N4pc75Sh+MZ8AEBY/S4rAeGLkOEV/Alq2eSlv7ZA6E0pcRQlu+X4IAm0K3girviajH0TaYMiDuRocHLF4SV2u/9WhKaw4rTYK5mWEBLoWqidqX5xzpB2R0cu3eRdBRXkhsNQ/qmrKGl3/ZkGvlmsS43wJ1S5Q4CSj5R6gc5v+yvSX/0CbgCdbCJLyKA2BEmNNzk98TNU60oal8uiEzLEZuBoaQqPIPm/OI+zFs69v4McZcyWUTJszgkC2PELxZ3uCfSS38VXnjT/q0DB/nKa6ZlKiSR87r/GkN8ZwMIuloRHHlfuTf96NApvJVivzowgwc= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2147a8d3-9d2a-48df-5b84-08dc0709b0c5 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Dec 2023 18:28:58.4517 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BbbWFmsxdDyDS7Ce0g/HqvoIUpfY3eTv+KFFnIr//vDpEUy+ll4j5wYN0dN/lbwIBWDEYQRDcR7HeR6wgAVg9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9050 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786461006271262911 X-GMAIL-MSGID: 1786461006271262911 The common dw_pcie_ep_init() already do the same thing. Needn't platform driver do it again. Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v1 to v3 - new patches drivers/pci/controller/dwc/pci-imx6.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 9e60ab6f1885a..4b2b9aafad1b4 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1080,7 +1080,6 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, int ret; unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; - struct resource *res; struct dw_pcie *pci = imx6_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = pci->dev; @@ -1099,14 +1098,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pcie_dbi2_offset = SZ_4K; break; } - pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); - if (!res) - return -EINVAL; - ep->phys_base = res->start; - ep->addr_size = resource_size(res); - ep->page_size = SZ_64K; + pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; ret = dw_pcie_ep_init(ep); if (ret) { From patchwork Wed Dec 27 18:27:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183548 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1604607dyb; Wed, 27 Dec 2023 10:40:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IFL0/dAJQz034xb7MQdtnh/GxyMgecTyr4rYnr8JBKpUEiZuFp0WSHcAGFwHLcahZNO55kh X-Received: by 2002:a05:6a00:d6d:b0:6d9:a87c:4a3a with SMTP id n45-20020a056a000d6d00b006d9a87c4a3amr1971735pfv.68.1703702441080; Wed, 27 Dec 2023 10:40:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703702441; cv=pass; d=google.com; s=arc-20160816; b=qmrNzUoo3n6oIq0h2Oxw1ltXdcsLEhgYW4FPnU9I3LEhklDpG1yOIa2dUQsZXUDXGz vQbvqTkfu8PEJpdyiW65QEw6RN7hV4kUDxTwoUoOl7lmVdG0gvzv2AFBu1xNfVuG7wsh atP+RTEcm0gfoxdikXM8HQZS9GDVtQw0hHZS6mT0snFZIDg5BOrJ/7koV6JIans/oRi+ bPBSKcxiAIpb0jlmKMVGSj9rBmNLU6pu0TNARSHGrKxZBEGGlLMngSqOQM9STreFoiXo H0J50P468lPYxO6NHjEA2wCY3fzjIuovx3NEzZZHHPjZfqEmUaP4RILEtER1G0U1ZVKb qS9w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=7YQHpyLDTwT3wFqJLJaY+UXcCMsgHUVOZ1xcNx2P6fU=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=JZ5NP6ZGWJiNK/0gF/eoeJVJRSU4H8Tj+dDoB/duNpeilfO5LFGJ5UQ8WotXVXxYsi QEffc3e6GIm/mp1UNxIFhpGEz1bhr/0h75yhX/J704sTorw1MHWOErJeWgS9PVVDA9lZ UkPLcpBQuzbP8ARlC+AY2LZe6X4l7c2mjrx2zHJFI2rbv9HSXNXMMNJc0Uz3kYX2pnJ4 wN/6yvtPxcx31TVyDq8tsWNb/efCUbmzgPEtL/qZfANyMEa0Z64C6q52qlm6owIhQzH1 JmHOYArXXf58UO6c5y85Z47gIDOJDIkBGIt43OUsmDCfQGebKTfC7bNrHCSMfmzPoEJ4 KR9w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=DX7tn6mD; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12210-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12210-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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b=DX7tn6mDunehZo450N/sAXCGyL1DydmdeD195lbVfEp9EetDeMtZwd4pIwUbRoLDitbNaR7KAOxtce4N7CeEWSBcve3Y4H1PJH3c0X6TtlsZ6DnpaDAzrxMeRMFMJZB0qshsiAkbliauHsKFcujSfrX6lDKyAVG+uw7Jjyh7hBo= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8271.eurprd04.prod.outlook.com (2603:10a6:102:1ca::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:29:03 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:29:03 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 14/16] PCI: imx6: Add epc_features in imx6_pcie_drvdata Date: Wed, 27 Dec 2023 13:27:25 -0500 Message-Id: <20231227182727.1747435-15-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8271:EE_ X-MS-Office365-Filtering-Correlation-Id: f07a7711-c5bf-454b-4841-08dc0709b3fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This introduces the addition of epc_features in imx6_pcie_drvdata to accommodate these differences. It's important to note that there are no functional changes in this commit; instead, it lays the groundwork for supporting i.MX95 EP functions. Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v5 to v6 - add missed maxitems. - add comments about reuse linux,pci-domain as controller id. linux,pci-domain have not defined at PCI endpoint side. Change from v1 to v3 - new patch at v3 drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 4b2b9aafad1b4..6a58fd63a9dd2 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -104,6 +104,7 @@ struct imx6_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + const struct pci_epc_features *epc_features; int (*init_phy)(struct imx6_pcie *pcie); }; @@ -1065,7 +1066,10 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { - return &imx8m_pcie_epc_features; + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + + return imx6_pcie->drvdata->epc_features; } static const struct dw_pcie_ep_ops pcie_ep_ops = { @@ -1530,6 +1534,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, }, [IMX8MM_EP] = { @@ -1540,6 +1545,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1549,6 +1555,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .epc_features = &imx8m_pcie_epc_features, }, }; From patchwork Wed Dec 27 18:27:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183545 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1601047dyb; Wed, 27 Dec 2023 10:32:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IFnvHwCc6zo3QGHXDzR4phNMHpb1Km5vkpvBpmX7eMB0mvg+QTDlWfiKRmcHlxQw1vGs4Lf X-Received: by 2002:a05:6214:4105:b0:67f:7c81:a5d3 with SMTP id kc5-20020a056214410500b0067f7c81a5d3mr12598282qvb.36.1703701952358; Wed, 27 Dec 2023 10:32:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701952; cv=pass; d=google.com; s=arc-20160816; b=WValeW/QeMY/M79OjD6EVmR4hlVoqRzZkyS1GzxutH0n7A03RNK/D21C1iBo/JqI1I 5gJYlopdjc8P3T4RuTdDpSBFRSpIVoUEvoPrsuMvBBVsPCdq9MkooyJFhMj7pWhaykem C3J3B9388KVDIjqXVCDsgLmhSvNBg+WEptgjEs+UvJUuhzf/AzEdvjSoek2Rmt2u/pey ibfQc/4F8RXNzAjX26cT5HoHG2JYjLv135Kl6kh83yBWTyh9rnA268HMLTeQoaoMkfol I+oMeG4vrLP6vArcqVSMiC5AmrSShs5y73T0VLIwRwKzXPcdF0Mb8+ity9zhvoLGavGL OlgQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=KqwMa6eMbLnQJ2/DnJpJInA1vRcpd1Bx4zYAn3HEDQw=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=Sr7eBvnYiZpHnj/iUe4MUO8oM7Zf2ySzj4h+5QiRWJZmKh/4UWaX+8WgNwNplCPjwl 1+aB6aeab6StcmbsqHiOsXziWugniVHwMSYa1LS2NP4hqbP9h1qYP4CtOnhaVr8z3/+f XlVQ1Zoadr3bBayq/engiQUJWyjGqj51vSJkxJUX1tR6tcEfcX19wY0tVDdtkXuYJhxt M6IpOVEF1exbL4A5zOnBqQFnawpfMYgY9CesTbcsnY2tv/UJ2TKY6YpK2YkU/oyxRVae 8ljkNm3BZS0HudqZ5i6VJZ9Z9pLV29/i+RpK9QM9soo1fk/iYeeDGK26OdbVdzYFowRi v71w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=gDw2mRSX; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12211-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12211-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Add reg-name: "atu", "dbi2", "dma" and "app". Reuse PCI linux,pci-domain as controller id at endpoint. Signed-off-by: Frank Li Reviewed-by: Rob Herring --- Notes: Change from v1 to v3 - new patches at v3 .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 57 ++++++++++++++++--- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index ee155ed5f1811..f4d6ae5dab785 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -22,14 +22,7 @@ properties: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep - - reg: - minItems: 2 - - reg-names: - items: - - const: dbi - - const: addr_space + - fsl,imx95-pcie-ep clocks: minItems: 3 @@ -62,11 +55,48 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + items: + - const: dbi + - const: addr_space + + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + reg: + minItems: 6 + maxItems: 6 + reg-names: + items: + - const: dbi + - const: atu + - const: dbi2 + - const: app + - const: dma + - const: addr_space + - if: properties: compatible: enum: - fsl,imx8mq-pcie-ep + - fsl,imx95-pcie-ep then: properties: clocks: @@ -87,6 +117,17 @@ allOf: - const: pcie_bus - const: pcie_aux +# reuse PCI linux,pci-domain as controller id at Endpoint + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + linux,pci-domain: true + required: + - linux,pci-domain unevaluatedProperties: false From patchwork Wed Dec 27 18:27:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 183546 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1601181dyb; Wed, 27 Dec 2023 10:32:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdc1FEEZrKDl7apLXtmGd0fzIpIjXT9IVV+Sah8SDFoH7W7lHt1PMxYKMZK4PtC5UBfpwJ X-Received: by 2002:ac8:5f08:0:b0:421:ad0b:fe55 with SMTP id x8-20020ac85f08000000b00421ad0bfe55mr18845194qta.53.1703701970265; Wed, 27 Dec 2023 10:32:50 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701970; cv=pass; d=google.com; s=arc-20160816; b=YY7FMmsDwYQ5xzAL1cihuVoquoHxGUbVTmB0+2w+/oQopTYnSgpoi8dSPbzWM/6vlu Z5wKCxJVRMeiGDvQJO3h8yNfoKztJvrucYsDirUw3Ip8GBdEUiZeJxTcbimsqdQ1t0xH yAhhiTjfFr1bxiRSoqCN5oS2PV3Vv+i3vcoyJZ5pgDFNuxH2ZNdDQa0g4+AAO1T2VSXl 3FJSMUO3vsWmFu4/2G3ICCX1GlroSQQ/2rUWywAfdA+/5RuUPRVPM7DA/wX/LCXyTBrs 0f3hOrMqnMY8HCW1LtUNdchArjRYCkRW/bQCZ7MsTsCrc8LSFTwx8lzWppl6/qPW7UrJ iq2w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=q8vo+UQ9KtGvOP++Or5qDRIkrFEKvxts5Qo6V24QQ9o=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=fTZAsS6CbpOLQjF4ohRBs+ztFGKkiKfbzIGNK/mknN28s9R2p2Ci0PfmjaVtKEJuUd 6ZuaRkPuAgKBqElr2DspaJFuwzA+Q9Bzz3CAa00hx3//mLPlqm1d0PimBJ7AM7IVtuMH tuSAF/DWS7tO8EUm3DSR3MXfNP4xFzPs4UHnf1DzNINE7iIS2Rwgh6z1OfrZL/+tbDLh NXT/c0PzhcU3sOed+KzVLmRl+ZubNJQl2mX+vpga59IL3tXd3RHkfOiLqGkntLSpPmPs CuWHKFfB7LBLLbFKiOfaOkB89AYhpEdrnS5ZIcrSU9uJQ7v8dM6R7QHDlfEjinO7fMiR B1ZA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=dik2c5+l; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12212-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12212-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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b=dik2c5+lvc7D/sNIx/LbnKs5mJxhTZv7QGyAVZrPHVx2AcNaai5u9EIqokWqBBppiGPxs9w/GuSnsulp9HQIBIWhQ5X8Th3T0naT+pDRh4V1tupPLPt0enja+mFOKkvafHfxECCJ6LWOpFJMxo/qodIw5sjI5ltfwWpqeGWcvLo= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB8271.eurprd04.prod.outlook.com (2603:10a6:102:1ca::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:29:15 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:29:14 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 16/16] PCI: imx6: Add iMX95 Endpoint (EP) function support Date: Wed, 27 Dec 2023 13:27:27 -0500 Message-Id: <20231227182727.1747435-17-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB8271:EE_ X-MS-Office365-Filtering-Correlation-Id: 90c2cc65-335d-421b-fc67-08dc0709ba49 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Internal bus bridge for PCI support 64bit dma address in iMX95. So set call dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - change align to 4k for imx95 Change from v1 to v3 - new patches at v3 drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 6a58fd63a9dd2..00ec59867c17b 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -75,6 +75,7 @@ enum imx6_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX95_EP, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -84,6 +85,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) break; case IMX7D: case IMX95: + case IMX95_EP: break; case IMX8MM: case IMX8MM_EP: @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { .align = SZ_64K, }; +/* + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme + * ================================================================================================ + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size + * BAR4 | Enable | 32-bit | 1M | Programmable Size + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size + */ +static const struct pci_epc_features imx95_pcie_epc_features = { + .msi_capable = true, + .bar_fixed_size[1] = SZ_64K, + .align = SZ_4K, +}; + static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; + /* + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed + * after all dts added "dbi2" reg. + */ + if (imx6_pcie->drvdata->variant == IMX95_EP) + pci->dbi_base2 = NULL; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n"); @@ -1355,6 +1383,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) "unable to find iomuxc registers\n"); } + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", &imx6_pcie->tx_deemph_gen1)) @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, }, + [IMX95_EP] = { + .variant = IMX95_EP, + .flags = IMX6_PCIE_FLAG_HAS_SERDES | + IMX6_PCIE_FLAG_SUPPORT_64BIT, + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + .epc_features = &imx95_pcie_epc_features, + .mode = DW_PCIE_EP_TYPE, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, {}, };