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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id f4-20020a63de04000000b00588e8421fa8sm7626237pgg.84.2023.12.25.00.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Dec 2023 00:45:26 -0800 (PST) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com Cc: Kito Cheng Subject: [PATCH] RISC-V: Fix misaligned stack offset for interrupt function Date: Mon, 25 Dec 2023 16:45:21 +0800 Message-Id: <20231225084521.78251-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786243022070151783 X-GMAIL-MSGID: 1786243022070151783 `interrupt` function will backup fcsr register, but it fixed to SImode, it's not big issue since fcsr only used 8 bits so far, however the offset should still using UNITS_PER_WORD to prevent the stack offset become non 8 byte aligned, it will cause problem for RV64. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the offset of fcsr. gcc/testsuite/ChangeLog: * gcc.target/riscv/interrupt-misaligned.c: New. --- gcc/config/riscv/riscv.cc | 4 ++- .../gcc.target/riscv/interrupt-misaligned.c | 29 +++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d867c0a03f0..c2b24d3db5a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6790,7 +6790,9 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, || (TARGET_ZFINX && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM))))) { - unsigned int fcsr_size = GET_MODE_SIZE (SImode); + /* Always assume FCSR occupy UNITS_PER_WORD to prevent stack + offset misaligned later. */ + unsigned int fcsr_size = UNITS_PER_WORD; if (!epilogue) { riscv_save_restore_reg (word_mode, regno, offset, fn); diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c new file mode 100644 index 00000000000..b5f8e6c2bbe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */ + +/* Make sure no stack offset are misaligned. +** interrupt: +** ... +** sd\tt0,40\(sp\) +** frcsr\tt0 +** sw\tt0,32\(sp\) +** sd\tt1,24\(sp\) +** fsd\tft0,8\(sp\) +** ... +** lw\tt0,32\(sp\) +** fscsr\tt0 +** ld\tt0,40\(sp\) +** ld\tt1,24\(sp\) +** fld\tft0,8\(sp\) +** ... +*/ + + +void interrupt(void) __attribute__((interrupt)); +void interrupt(void) +{ + asm volatile ("# clobber!":::"t0", "t1", "ft0"); +} + +/* { dg-final { check-function-bodies "**" "" } } */