From patchwork Sat Dec 23 11:55:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 182952 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp1629135dyi; Sat, 23 Dec 2023 03:57:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IH0urvoncIX+VAuRSoZt9YOnj2dAZyTcBeCK5s8Hw8wiPaHwvOpvQwtcxItl322IDFHoszd X-Received: by 2002:a05:6808:1993:b0:3b9:ee89:5427 with SMTP id bj19-20020a056808199300b003b9ee895427mr3585876oib.22.1703332626427; Sat, 23 Dec 2023 03:57:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703332626; cv=none; d=google.com; s=arc-20160816; b=xmKhqUlots410pZR5LDwNB16oUmUO4zc/RWi4uGG5pb/9eamfMR8LJ1zCI70/WTzxU 1201Fg0TWWNlwbRP61/stzgwlA12Kw5nwVAfsWEGuMCMHfiMVaXnB3z49MYopFJ1/Z1m Z7CdXLrSW0iLjaFs/f3Ry75dAYAVw7oY9qVH5PhLkxFtholY9iZyqXrybFIzvWr4Ohzj XE95C/jm4QGqbBuU/Jg49BEEEZ846HDYb3MnGNBmQVgG38AL5et4nDfWzCB8eJ+W8sLd db5nAjWKpY2mcNtWi6gzT2CqNOjyRCmU843niON1XZhujl2C4jIXibjP6dY1VClK63qy C2xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=s6BgZXk2Z2EdsOWLkN8A9CQXodyxdbtKQobwp6o/jO0=; fh=prVInD1SXw1M2j1g1IotpZO4gKqwzYtiUs1linLtXcs=; b=OZOqxnW3Idpz0kVf9pAXlJEpL8aGPGMtbaph9aPImqlU8p7nqWskb1alwa4Wg1JKQ+ rg8fqsUkCobERxjh/EqjPNmM3Lww42XOHThLWSiC8gaIh8BZvh2oS9UhQK7xrPGfmXlP QIKKi5RQxGqCkAC3eGLXpZcITdyxoP1hw23XNAtoPrX3wfpQENMfNFjP/iZuzAGtwKWO G3ZqlKU3m2P+NdPhqNCnpITCtMYC+Vs1J45uBZMfLsuKQRYGLaSn8rFq1hMLDA2zN6iA y2DRLAkEza5b/HlCWgKpC/Q6Nfa0FgENMARzIxf/4Uz1M5QBxrCKqE/7mhBMb+DwFvM8 BrAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IrholNb9; spf=pass (google.com: domain of linux-kernel+bounces-10397-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10397-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id x8-20020aa793a8000000b006ce7e1a786fsi4767055pff.169.2023.12.23.03.57.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 03:57:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-10397-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IrholNb9; spf=pass (google.com: domain of linux-kernel+bounces-10397-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10397-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 86AF1B229BD for ; Sat, 23 Dec 2023 11:56:37 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0F57DDF5E; Sat, 23 Dec 2023 11:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="IrholNb9" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6590CA6A for ; Sat, 23 Dec 2023 11:55:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40d4e529f24so6663675e9.2 for ; Sat, 23 Dec 2023 03:55:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703332542; x=1703937342; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=s6BgZXk2Z2EdsOWLkN8A9CQXodyxdbtKQobwp6o/jO0=; b=IrholNb9ZoAcBNcmv2gAfyK5ESqT9fQ/wOMZ9WJ2vuquVVQf51MRWqQ5FwihobvSBv 7enzSr+WrurTp9V0qYBBEMwt2WoAUAsks7LGK9bFGBDVhqrqsa5v3ddP0GF3b1diCCNg A/VfF2wYy7gQlJ2q+ykKX+F7UjaFAXvZ3FcXLzmhHaEMzW3LFnqs7r6ma7LoeI+CL5m8 RO6feIxQ9q/yHqXYIdxrOHfOlP/bQTMLq62dARnWXKLRSoxn0Z3uhiX38cEH+qLozwXh joTYwiNkNQ9evwMRcerxsqOnsyMfuKvOfyQ8DsYrYdclZaWmxXgFf7cDcoHJF5Px3+3v EBNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703332542; x=1703937342; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s6BgZXk2Z2EdsOWLkN8A9CQXodyxdbtKQobwp6o/jO0=; b=LvhrRejf7nUt+aE8XuoMeCnwV5HgjEeGdJQyO485lWEuEWv6hFuroU1iSrujWydiHM 3aXzoMvY6bFeTVBK1gGSXxrP+J0nUWA3ACHW3TFYi5GO/AFt4eJ8/zFb+wCXfAMVNnpJ wdrCCSYrmCCyWnW1HnYVOOIuDY9KlQIepcIrlTrmXXRfy8jQO1NjH2EhU7n8Fa9PqQEa 9SCQ1nNsQ+ExJrUXRcjvD4x8Di3hxWRL+0gTNtRIX5SpOzsSLObwkfh7Hiqau3UGH+03 cItYPDJLntKmLApxuAJ+PGGTRLFo/X4Dfp7XUjqGp+pCey794YGp25ZCZxs+Yhwi51EK ohwg== X-Gm-Message-State: AOJu0YzYl5pFWSy4aKSvZ7hDU8weMhmdifF2zXeOS7h1Br67sRflwJ8b xBaK5EiknIIGbCF4n28Yu12nNG0Y6SzEOnavkF5k3duN8nM= X-Received: by 2002:a05:600c:3f94:b0:40d:34ec:8809 with SMTP id fs20-20020a05600c3f9400b0040d34ec8809mr1048362wmb.270.1703332542096; Sat, 23 Dec 2023 03:55:42 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id r10-20020adfce8a000000b00336781490dcsm6351525wrn.69.2023.12.23.03.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 03:55:41 -0800 (PST) From: Abel Vesa Date: Sat, 23 Dec 2023 13:55:21 +0200 Subject: [PATCH v2 1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231223-x1e80100-phy-pcie-v2-1-223c0556908a@linaro.org> References: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org> In-Reply-To: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1569; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Cjd737+0WvbPLfzwP1kvLLPld4NW6uZ8Tvfpkvgqv2U=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlhsq2k0cPV01Jw/I8SkjK5Ygnbi5XDM2jUyHL9 bS05EY/5RWJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZYbKtgAKCRAbX0TJAJUV Vmi5D/9f1U4t+GjBZxjU8iax36NUu3PaOld9Whjbrtds0OLfkX4Nof2QRKGeTud00FYbpSXcv6X HEGPebTsn3LZIkDvB3CadQlFZEWVH2mNVGMsmNvuSi+Rp+JgRLbLdF2a08My/MCu8g/Qy8nyw0v BOte3qBVbceO4CcXbpysQgjVlQE4OEFMCNCmnInFSbvrmXrnoQs7awAeqRwfpQG0XvrRfIE7SdJ Ume6hn+wGy0mZb1dPEjV7EZGesWXMeC3xk5DYjSwLGxGP9x8izsqcI1UGuM0R8EZ+CTASipIp99 4JpRXt0DqaavGLhRC1EhV6x3hmNPlO/UNPCQmqGo8KzYi/tE2aK/Tx49BRXoWbjn1cizI0I2Ezs 0K09HAsfYsivgqRHSrFKf+bPmg1rlj4e+Bmq9m/GMWhVprdMDpl3fdvX1p/vW/3e9srRzZPtkej U4PyNI1bt68c66+7JDohm/xL6AaNhn9JtVXT1/oWt99UFIZ/QPS/2ZmHtd15OqmX3pp8S4zibgG OpjQDDiY82tfotlBJDojtCMvDqQ/LXQDhcEfVVKydoaiZFwhoRrtAhYoHYIGdxeG2zBC+d1OJBS R8rzwZXNZacCHgTp5UyBD8kA7haNNYkSLtFX6Bs1HXWx+Kqy62Vub97kDGI8VzfsS919E2jXNId FgidTucH4UwCLGA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786073711923110779 X-GMAIL-MSGID: 1786073711923110779 Document the QMP PCIe PHYs on the X1E80100 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 6c03f2d5fca3..ba966a78a128 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -38,6 +38,8 @@ properties: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy reg: minItems: 1 @@ -151,6 +153,8 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy then: properties: clocks: @@ -194,6 +198,8 @@ allOf: enum: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy then: properties: resets: From patchwork Sat Dec 23 11:55:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 182951 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp1629068dyi; Sat, 23 Dec 2023 03:56:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IER4P/kqIid/kaxSHbVBFsPZvFKIKIbCpNwTHHkn3P8g99F6cMGvED2XuNE+PLlwu3MgvSd X-Received: by 2002:a17:907:76b8:b0:a23:360f:f8c4 with SMTP id jw24-20020a17090776b800b00a23360ff8c4mr1469508ejc.41.1703332610972; Sat, 23 Dec 2023 03:56:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703332610; cv=none; d=google.com; s=arc-20160816; b=kjyrXbKa1OGfF80ngD/SgvgjGR4/SH97eLkl3jF3inRHewTHSVF3YToiC0wBXpuW2T ElXE7KxUefptR6WZ14F37EmJ0LudMZIBNzcBho2/MROUrWIezrymLS5LboJNwSG+fuPH C8yQssyMtQrG3oAL1UTgV90N+c6C2vMlyOhXgnztFyaD+tW3WiO6OoSNR7UmJdcr/8wX viFy2Fd6zu7WKSChy2u8OO0C6u7/mPhA2ZHqt7+QPuP6XySpezkIWMEQukCfnWwraFqZ dcVgpsg7eUL2xFSEHIbvveuQFilOKjb1YCKO7f9QhVUHQLGyCzFdb6R3XlXZ8Z8iXr9l Y41g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=xjW+JyAXSaCJAvexLw3wdIiNQdXbZqOYyV5y427gtuA=; fh=LcHVvcgzQietLEoGfXAGsOeHpn7byHe9480dVkDqu+A=; b=xeioYDqKLKnfoa5NCNv3Faqnjljr+kWeSgtEMAg8chKGkv4Z/JY4tiLz4shEYUs8bw rFcpcYtPTmkZAHj5Gml6KJ40u8HR+y+gGn1XY/5Eu7jLmjXqUE+9tHnMIA0WZzQGNzNy rH2s7LvAhAyT1fF1nZNnJtwphijy4A+bzUt6NXpcmih5pblYgT2tAHpLISyhKDxCpK0T Qfe6K4i5lzvSWbw6zYye40eEwNndN8Z6RN+R0vovVqrH2CitlsYTUangNiEZ3UK/w92Z LbTtRomx+7i8wA2rf+XpWDwzEkxDX//0yMfZIG+1FXXmnGQ2hrNDmM/cMu4PNnO27sPA 55mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=okBt+G+9; spf=pass (google.com: domain of linux-kernel+bounces-10398-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10398-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id l22-20020a1709061c5600b00a26b37b2331si1621006ejg.260.2023.12.23.03.56.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 03:56:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-10398-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=okBt+G+9; spf=pass (google.com: domain of linux-kernel+bounces-10398-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10398-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 964881F21450 for ; Sat, 23 Dec 2023 11:56:50 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 464CCF515; Sat, 23 Dec 2023 11:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="okBt+G+9" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DDC4D278 for ; Sat, 23 Dec 2023 11:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3333b46f26aso2341968f8f.1 for ; Sat, 23 Dec 2023 03:55:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703332543; x=1703937343; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xjW+JyAXSaCJAvexLw3wdIiNQdXbZqOYyV5y427gtuA=; b=okBt+G+9KyCCqvSfp2IKkDimHvJnuqNG6j3DUEoeyN0Jtegamm1dnaopo39NC7CCRg 6duwRXeNP224ht72ATnYmRGhHYe9CDszuUnD/jsR4UhahG1rxtBBjDIPQziM8wudvBJm 9/vSRShKgoTWBUmufx2f+1iaVIRl6QhKrpLqvb6XIleXlfCV7htiGhFyiJ2gxR0dlovc i/E+LVfSzfbtG7f9Ze4WxISrjoNQDdbFLH2OR/oWJE8Me5mj2CG2mQGTHAzFv+XetO7j ZONdG26zqePzkSC3elqBulfRr0OYYftVxN8zj9zt/9JCg3x9pdQE7uudtYaT6vbfhGBO j5nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703332543; x=1703937343; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xjW+JyAXSaCJAvexLw3wdIiNQdXbZqOYyV5y427gtuA=; b=ukeD6QdbHj8z2Eae2BqnQHTbXrsB9F/mMHTilVI14wBly1efegZgffLCWZmhD1IrFW HaTUrIWA/lB0q0ogM6/UWUuNS31C3ihXU/iN5qMZ2BLRkEX99kUgkbAG3ciQROjA3muY jHL3OCxk7P7z5Br6JQ+gf9UHUZUVEcboou/VK9TQZ8sUhVOt/Bsws3PFEztE2x9fDZ4x cdJzALqgnYykx4q0xeuGd5Ur9A6dg1g0v7XUZqbPUJOciJNTRMXwtKTKiAFAn3QtTgHk hdeJTFRlydKWeXcFHdmlm7/+do45wxlqasvRlUuP0vzHinMTCnHFNsPPYjMybLuZaFxb mAIQ== X-Gm-Message-State: AOJu0YyZfOUfCqObYfjM1+sDVNDdywJFa+3S1sSNJZOi2lRV5i7UAUdr 8bl4+Sovu1rnoYgtkfxREipElr9wtIib0w== X-Received: by 2002:adf:ee47:0:b0:336:8690:7488 with SMTP id w7-20020adfee47000000b0033686907488mr1292111wro.107.1703332543445; Sat, 23 Dec 2023 03:55:43 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id r10-20020adfce8a000000b00336781490dcsm6351525wrn.69.2023.12.23.03.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 03:55:43 -0800 (PST) From: Abel Vesa Date: Sat, 23 Dec 2023 13:55:22 +0200 Subject: [PATCH v2 2/3] phy: qcom: qmp-pcie: Add QMP v6 registers layout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231223-x1e80100-phy-pcie-v2-2-223c0556908a@linaro.org> References: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org> In-Reply-To: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2434; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=aQTJdCbIPDB/z7LFSFKZkLMGwHpEIeQuU+oxAP8tlJE=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlhsq4LM1fJC70vKYIm9i0vEjT4NhgnQDYs6vLr REEP8JuS3OJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZYbKuAAKCRAbX0TJAJUV Vmx4D/9Mx4NgoddlhLOFINCkZvKJb8WYWsdHlrx/J8FwU9RZX6p1qGJXdz6OFTKqENY+zr5zixN LACRcushLS7dlIzUgbCFN7Y+78S2zYkhDZMQU8CTbQm78jPTw8q1ovvOFWP3fKL2vc0sUh+tKcO i+PWKK1aeuY30k7h4VH+UbEEI8viSWs0w2anWl5SHRWFmcK6UVk8xcvOx83dwHm1SH6TdfyvoFR 5O2J1OmAzkK8Tees9HSPGNPs8kucTiwiFoeeyvWPQJSnEttrqLtMVw6OsHbUUEeVRBRlm+OAcvF qbTcAaxMoM2KOX8x0AmfirEKyCcNxCuPROZXXIX71PkeX8PJuSC1N7RsfhuE+HTHnesRWmSM1VV j+sWhBIgbAVqesDFVb2zDEB/FyI0XC6kmaeGiD9nRLySViRR0qbZTpv0MjrLLJLhP+/W9VN2CeF XuoEeiDWa0JuY2JM38yAQwGiR5rX4UuGaKhhGSj3H0mdAxkENER5TTU/xQBgWHuyK0oW4UJW6Ee zilLsAyBUQF2Y04qoHtw/pLAUGLZHbfwBPQOgUpNGqF+8s6MxBsMs0bYqr3K/VzUWH4HxfcJjtv SjTyVHymAG99fkY5G/d9Bj+jODSPre+qXUGbkfYnWLR7KnvZwaHknwRL/CjZzNGgBeThn9/vbHr THDqvxmL2v4sO/A== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786073695473639044 X-GMAIL-MSGID: 1786073695473639044 For consistency, add the QMP v6 registers layout even though they are the same as v5. Also switch all QMP v6 PHYs to use this new layout. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2af7115ef968..03a4898a7e6f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -116,6 +116,13 @@ static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, }; +static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -2936,7 +2943,7 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS_4_20, @@ -3069,7 +3076,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, @@ -3099,7 +3106,7 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, From patchwork Sat Dec 23 11:55:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 182953 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp1629148dyi; Sat, 23 Dec 2023 03:57:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IFPrs63kFWM3N5UJXMyZWrHArRcH3G9UTReHqD++Xcskpn1e+g111T5MRiAMukoC6APgDwR X-Received: by 2002:a05:6402:3098:b0:54c:b719:9f9f with SMTP id de24-20020a056402309800b0054cb7199f9fmr1431947edb.66.1703332629028; Sat, 23 Dec 2023 03:57:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703332629; cv=none; d=google.com; s=arc-20160816; b=mTzk8suosh1wm83JcLL+6wD+SRGNVW1kE5ncozLIov44Oi1UwLsl0BWJT4utntVfrO f9jK/0hSxKJAFOsPt3YFNZQYsxPDl3yXt5xeI97l2Q5dJMRpIOdTybJpH/PDFxHsDYEn W8S7Kq7s4GW4LORMzNK98j1/oLChhFQn68+8tlFIQ9GGvgzaIoQ4bgcnd5ghUo9mueT4 g1KcRaySbXTBEjq48PKFxj8ZaA1H9na7cRDK/e5RNz/M096PorgINBWP6A2dQI+fV+uI EBA5ZhYRMikq9lTuySte2hTnNvilq74I6wZFafPlYyO0frNZfnBZSVTEQTtLeoE2kl1c TYDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=rOpouraVubHr7E8NIXUEVARu6E+LdqST9+cplPZyKmg=; fh=LcHVvcgzQietLEoGfXAGsOeHpn7byHe9480dVkDqu+A=; b=K+sc7ijS+Tb3eRhHmPuBerR2K5ZWbJomsDZz4yFS1M33WSxlGLNe6Q3qFDWndaOPoT WXZUrAUBaGpCMK/aCJDmHOJOQaOXCvRSN80gPj134Npuxa6EZ9jYoNlEHyL9az5jmv69 yDC1eAgAgwp4n+wxoT4IyQ3xI5Z0HH2GwQVUx3e1LVKET//nql/ewhwda/CtCWSfD4IE OgwZJ06+TMP4/G0ldb71wvCQe+HX2HPDv1jgpfJd7YfK+XmVhoEvTkqyfrK7GjBVAD7+ vo/9bqNMZLKu8tUe1s4MSsH0HwimONbqJL75lPiOpscGdcDl3Y78jrrEO2rYTHYIlVYx w5ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dn4QgIgG; spf=pass (google.com: domain of linux-kernel+bounces-10399-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10399-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id x8-20020a05640226c800b005548e0ac193si509817edd.137.2023.12.23.03.57.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 03:57:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-10399-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dn4QgIgG; spf=pass (google.com: domain of linux-kernel+bounces-10399-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10399-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 77E981F21712 for ; Sat, 23 Dec 2023 11:57:08 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 54AAB11CA3; Sat, 23 Dec 2023 11:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dn4QgIgG" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0C7DD520 for ; Sat, 23 Dec 2023 11:55:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-336746c7b6dso2194123f8f.0 for ; Sat, 23 Dec 2023 03:55:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703332545; x=1703937345; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rOpouraVubHr7E8NIXUEVARu6E+LdqST9+cplPZyKmg=; b=dn4QgIgGmL/B7miYaTyy+eUL8fwXfrTVWbfXbV/96nun4debG8gtMtseu+5RNW4qT1 s9676jFW5HraKotEFal0MNo3S5WLCZJF8P3vibiJK+ZuvLSRB6UknyCb7d6J+aQkf2sU 0ypb6ADGYZFC0csSYN7J3n93/UDzym7yOj59p7kDro+6dAxwOym2B9rDFupo6OUJYIJ5 ixgy2Xurgg248uMCpr/5oyLyz3B7JKHU9afvndsvVckA57jzcCzAaRkQ1CEeGlcd4I1G FI/QaGjwMA7+UpYwZhb5jNtV1lXJjooyp+1/WdObdpauP9+K/lo7rdaFMKiaOjIXKJEw mmrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703332545; x=1703937345; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rOpouraVubHr7E8NIXUEVARu6E+LdqST9+cplPZyKmg=; b=icoQ9K+vWK3aKEFMTTqQu5fX0bO3wLYdeVcj7DOH5GeNGZMkARBxXc/D5r+g5jJxQh aSM2J70wHGDvkg1A7Qd6j5eLqWdOi4EEb9fovzhpkeowhXbGZhkGBgVeuUWPGQtgqOV8 88dW3/Nc3M9V1ueMCKA65eXv4Ad4xWozILn7lqAsKmReD2vJyvsMOC1XKuXgRqcZNCMo oFmPCj4i+MCc+3KwHW/e1ceawG92d3eBOKfisIyPpM4wZclZoFFAsZv92JOROisQWSe6 4yZEvawcfoUHjbob5SWZyI4k0PWjRXy7acxZ/kyl51Reht8oyA/h/sOo15ghOwLQd02q 3ImQ== X-Gm-Message-State: AOJu0YwEORA6eobrw3rcIydz9X3XUeI3n88a/LvtFkBvwVjuXu1rFDuN IHacbSnuZ2lLg28mokKbtsJE1dxXaX3LMQ== X-Received: by 2002:a5d:5f8e:0:b0:336:75e5:c6d6 with SMTP id dr14-20020a5d5f8e000000b0033675e5c6d6mr2215844wrb.68.1703332544838; Sat, 23 Dec 2023 03:55:44 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id r10-20020adfce8a000000b00336781490dcsm6351525wrn.69.2023.12.23.03.55.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 03:55:44 -0800 (PST) From: Abel Vesa Date: Sat, 23 Dec 2023 13:55:23 +0200 Subject: [PATCH v2 3/3] phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231223-x1e80100-phy-pcie-v2-3-223c0556908a@linaro.org> References: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org> In-Reply-To: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10603; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=YuZXnGgD1tFgmlzMrm3n8YH5E13zKRgYkBcmDqtvukg=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlhsq523c8i05Z6mfrh2qV6c6+V9n+ZYHthBODB koQ9G+vtSeJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZYbKuQAKCRAbX0TJAJUV VnslD/908A1p7XLEnmmtm4wUqZLfYNu0YDi2EVfiQxV5a5aCZIrgYy8qtxj18VMMug7b1xhxOcu rgs6XDB5wRw6tIYDTBsHBlkjtuqtLtqhB19IDll2x0xNkGsy7meFAGZFrPX1On63emomoP2mkyU st08sw1bvAcgSeRVPS05GdDjD9EQ8bZfcCNxyFGXAFiuEr8eaeHzrvhxexqACohmx7l6QMNL+xX 12gXoKDDbyX//lZB+slcekxFFvMxYTMi8M5ZnQvgCjLJT8jq5NKDfQmBcrhZR8e2Pr6xm3PWGW+ HWZoKD6jaajr0j/K2kLRuK59k40ugRqlvVI3sieg2P6/VoFDsitKjLVjJllIKm3PnpiA5ZBxNqi 64/TLfkx0v7INM4aKiBClmWqlrQJBlIuCgrUg0xSU/2JEzJ2U/i3XHEFZ2N/uW9+EeEl+cHG8zH BNZayaZVZ/DA7lZMtlpDcZZCyI/RzkFARXXqCKbkevdCFAGLFXtYFS5Nm6o8/f88M0I8qVSBvAn tL2lmBhJ5ZmJoweLVk/kKG4+zPIDVCTFXUXZLpDTwbmsC861EiI7k0OF9ZMOEOO/ag8pXQGpqAl lyg1sO1XHW7PUfGI/TfGfsO9FTqSbZZ+aQCtorW1EQOqBYr3sFaQHNcTqxORAPsTr86uJ+XydG7 APO27o7Zfog3VCA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786073715078953652 X-GMAIL-MSGID: 1786073715078953652 Add the X1E80100 G3 and G4 configurations. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 173 +++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 03a4898a7e6f..3ba302a7285c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -989,6 +989,143 @@ static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), }; +static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), +}; + +static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), +}; + +static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), +}; + +static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), +}; + +static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), +}; + +static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), +}; + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), @@ -3190,6 +3327,36 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), + .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), + .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), + .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + static void qmp_pcie_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, @@ -3892,6 +4059,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", .data = &sm8650_qmp_gen4x2_pciephy_cfg, + }, { + .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", + .data = &sm8550_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", + .data = &x1e80100_qmp_gen4x2_pciephy_cfg, }, { }, };