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bh=hbdPMPGBWozpmFUaZkCdhiZ0Fh092WlwkYQcWOwj7p8=; b=v4qdnPjF4EnSxtZ167Q0ECyWbxAgBFg0GHOqE1KAq3u+GadYIEXLRWUUnJ6Nh98Qbs g1qtOLU7+oWZJ89qiobv8gfKSfI24g8CaU2/1RDYQeigaHw7iey9JMHUE175VgYcgGYk 6LOJm2HSIMtNIZA/qq6gy1gTXStdxX15nLmh7EZJhIzFY5uH23Xz+eqHgTNx/ZyRdcgS KyL/9EsGPeEFI5r6iHo7mWe84fk4olPM8E+43MOJzVr9T0lgsVjy96qxAY5K0lsc/c4E OR+h6Ncvou2WJ0s+Y7oYqC+m+0S65nN8yy61SHG84JTRnHiJP8ag4y1ZRKc/xM27kW50 yXeg== X-Gm-Message-State: AOJu0YxjsMKgF8K1DGhHO6/3qr3gSQ1oPYTlkoYIQpzQIdLRW0g8OnZR eucBT06VDD34s+jeOWlXZ2nJKewWk/ZlQQ== X-Received: by 2002:a2e:a499:0:b0:2cc:a253:e72e with SMTP id h25-20020a2ea499000000b002cca253e72emr518179lji.60.1703243842587; Fri, 22 Dec 2023 03:17:22 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:c099:e596:3179:b0fa]) by smtp.googlemail.com with ESMTPSA id f8-20020adffcc8000000b003366b500047sm4054069wrs.50.2023.12.22.03.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 03:17:22 -0800 (PST) From: Jerome Brunet To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao , Rob Herring Subject: [PATCH v4 1/6] dt-bindings: pwm: amlogic: fix s4 bindings Date: Fri, 22 Dec 2023 12:16:49 +0100 Message-ID: <20231222111658.832167-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231222111658.832167-1-jbrunet@baylibre.com> References: <20231222111658.832167-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785980679666591796 X-GMAIL-MSGID: 1785980679666591796 s4 has been added to the compatible list while converting the Amlogic PWM binding documentation from txt to yaml. However, on the s4, the clock bindings have different meaning compared to the previous SoCs. On the previous SoCs the clock bindings used to describe which input the PWM channel multiplexer should pick among its possible parents. This is very much tied to the driver implementation, instead of describing the HW for what it is. When support for the Amlogic PWM was first added, how to deal with clocks through DT was not as clear as it nowadays. The Linux driver now ignores this DT setting, but still relies on the hard-coded list of clock sources. On the s4, the input multiplexer is gone. The clock bindings actually describe the clock as it exists, not a setting. The property has a different meaning, even if it is still 2 clocks and it would pass the check when support is actually added. Also the s4 cannot work if the clocks are not provided, so the property no longer optional. Finally, for once it makes sense to see the input as being numbered somehow. No need to bother with clock-names on the s4 type of PWM. Fixes: 43a1c4ff3977 ("dt-bindings: pwm: Convert Amlogic Meson PWM binding") Reviewed-by: Rob Herring Signed-off-by: Jerome Brunet --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 67 ++++++++++++++++--- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml index 527864a4d855..a1d382aacb82 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -9,9 +9,6 @@ title: Amlogic PWM maintainers: - Heiner Kallweit -allOf: - - $ref: pwm.yaml# - properties: compatible: oneOf: @@ -43,12 +40,8 @@ properties: maxItems: 2 clock-names: - oneOf: - - items: - - enum: [clkin0, clkin1] - - items: - - const: clkin0 - - const: clkin1 + minItems: 1 + maxItems: 2 "#pwm-cells": const: 3 @@ -57,6 +50,55 @@ required: - compatible - reg +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm + - amlogic,meson8b-pwm + - amlogic,meson-gxbb-pwm + - amlogic,meson-gxbb-ao-pwm + - amlogic,meson-axg-ee-pwm + - amlogic,meson-axg-ao-pwm + - amlogic,meson-g12a-ee-pwm + - amlogic,meson-g12a-ao-pwm-ab + - amlogic,meson-g12a-ao-pwm-cd + then: + # Historic bindings tied to the driver implementation + # The clocks provided here are meant to be matched with the input + # known (hard-coded) in the driver and used to select pwm clock + # source. Currently, the linux driver ignores this. + properties: + clock-names: + oneOf: + - items: + - enum: [clkin0, clkin1] + - items: + - const: clkin0 + - const: clkin1 + + # Newer IP block take a single input per channel, instead of 4 inputs + # for both channels + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-s4-pwm + then: + properties: + clocks: + items: + - description: input clock of PWM channel A + - description: input clock of PWM channel B + clock-names: false + required: + - clocks + additionalProperties: false examples: @@ -68,3 +110,10 @@ examples: clock-names = "clkin0", "clkin1"; #pwm-cells = <3>; }; + - | + pwm@1000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x1000 0x10>; + clocks = <&pwm_src_a>, <&pwm_src_b>; + #pwm-cells = <3>; + }; From patchwork Fri Dec 22 11:16:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 182633 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp990022dyi; Fri, 22 Dec 2023 03:18:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IF0nvFEnXye5HvQfgrRjroQvxVqcEmOY5Dy3nuZS3AAoPdayBOR1fBXlDFttj/uDFDfsI8B X-Received: by 2002:a17:906:b88a:b0:a19:a19a:eaac with SMTP id hb10-20020a170906b88a00b00a19a19aeaacmr594192ejb.101.1703243896313; Fri, 22 Dec 2023 03:18:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703243896; cv=none; d=google.com; s=arc-20160816; b=0P6XHYau+9KuARK27m3+gl7FUGoWtqpmx4VckMW4aXoRhySKu5dOdJDUHMs4t8zN4i XmeBZ9SuphbltOVZiXkzxVr7qKw1TZ6sCIPb57OqBxzhuFx5ADvHONLDZLsxxWWZ78BX zl3CjBvdaF66yKRwFuYxu7LTYamxOERJAPh/yBW8qWy2f5xMcCVZZr6uqGk8F6YRWcVt 6w33rXLJhjLOytdayQkTPoVmCuIroYDl6REQf/qNXrXz4XgDtGj7iYo8lrLCeMkun47x P2tifQrthH+OKpsK77BkFSr8HPwdHu9mNl0gnaA9T3/ml2It3a9BofvJF4RwHZnxLfQd 3cnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=UA472qIZSqNES0rFti6bcuMYBLF91YXl05BR5PTQI+4=; fh=2aiQaFmMxr/QDQUBgVVkbK+3ADRUnOteOvF/xtBRB/I=; b=vKh6KWfIvwZzf3c2QVcMHL3+G+AFIDfRkPU8QJTnq05muRsLsSFr/lNV4Lx+5GEdSv RvylFBx5WRTZYg3g8CIKi1mN8ogwD8qI4sVzbE6jUY0Wj54D3t2/YrxEE6QxpwOLdEHe OgS1zdeT2PFTGAOI/J46hx/JXyzC32ywgJrhVNNt0nhAYndr3kTfF1zVTsEkIsGQ2K9C gqltjyNixUNRxPLk+RY14LzEAONjUZ9vNWICWGiU7dvjgfLRZpQdFRQsGCKVLWLSgoKm EiAtiRM7EApehv9vz1CnzP1/9qGthPEQqVmdvOLh1jmd4pLqrgkYTVbSyK1EFV2LnOie YvAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=MSzGikbp; spf=pass (google.com: domain of linux-kernel+bounces-9647-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-9647-ouuuleilei=gmail.com@vger.kernel.org" Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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This does not enable new HW. It is meant to fix a bad DT ABI for the currently supported HW. The original clock bindings describe which input the PWM channel multiplexer should pick among its possible parents, which are hard-coded in the driver. As such, it is a setting tied to the driver implementation and does not describe the HW. The new bindings introduce here describe the clocks input of the PWM block as they exist. The old compatible is deprecated but kept to maintain ABI compatibility. The SoC specific compatibles introduced match the SoC families supported by the original bindings. Signed-off-by: Jerome Brunet --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 50 +++++++++++++++++-- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml index a1d382aacb82..eece390114a3 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -21,23 +21,35 @@ properties: - amlogic,meson-g12a-ee-pwm - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd - - amlogic,meson-s4-pwm + deprecated: true - items: - const: amlogic,meson-gx-pwm - const: amlogic,meson-gxbb-pwm + deprecated: true - items: - const: amlogic,meson-gx-ao-pwm - const: amlogic,meson-gxbb-ao-pwm + deprecated: true - items: - const: amlogic,meson8-pwm - const: amlogic,meson8b-pwm + deprecated: true + - const: amlogic,meson8-pwm-v2 + - items: + - enum: + - amlogic,meson8b-pwm-v2 + - amlogic,meson-gxbb-pwm-v2 + - amlogic,meson-axg-pwm-v2 + - amlogic,meson-g12-pwm-v2 + - const: amlogic,meson8-pwm-v2 + - const: amlogic,meson-s4-pwm reg: maxItems: 1 clocks: minItems: 1 - maxItems: 2 + maxItems: 4 clock-names: minItems: 1 @@ -58,7 +70,6 @@ allOf: compatible: contains: enum: - - amlogic,meson8-pwm - amlogic,meson8b-pwm - amlogic,meson-gxbb-pwm - amlogic,meson-gxbb-ao-pwm @@ -68,11 +79,14 @@ allOf: - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd then: - # Historic bindings tied to the driver implementation + # Obsolete historic bindings tied to the driver implementation # The clocks provided here are meant to be matched with the input # known (hard-coded) in the driver and used to select pwm clock # source. Currently, the linux driver ignores this. + # This is kept to maintain ABI backward compatibility. properties: + clocks: + maxItems: 2 clock-names: oneOf: - items: @@ -81,6 +95,27 @@ allOf: - const: clkin0 - const: clkin1 + # Newer binding where clock describe the actual clock inputs of the pwm + # block. These are necessary but some inputs may be grounded. + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm-v2 + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock 0 of the pwm block + - description: input clock 1 of the pwm block + - description: input clock 2 of the pwm block + - description: input clock 3 of the pwm block + clock-names: false + required: + - clocks + # Newer IP block take a single input per channel, instead of 4 inputs # for both channels - if: @@ -110,6 +145,13 @@ examples: clock-names = "clkin0", "clkin1"; #pwm-cells = <3>; }; + - | + pwm@2000 { + compatible = "amlogic,meson8-pwm-v2"; + reg = <0x1000 0x10>; + clocks = <&xtal>, <0>, <&fdiv4>, <&fdiv5>; + #pwm-cells = <3>; + }; - | pwm@1000 { compatible = "amlogic,meson-s4-pwm"; From patchwork Fri Dec 22 11:16:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 182635 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp990283dyi; Fri, 22 Dec 2023 03:18:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IFoTSsUcW5u7JyylWTDrddStKTtvMoo8qIKZRD5dacCw+uawDJBywat+El5ToTD8B+jHUxa X-Received: by 2002:a05:622a:184:b0:425:4043:1db3 with SMTP id s4-20020a05622a018400b0042540431db3mr1467586qtw.134.1703243926070; Fri, 22 Dec 2023 03:18:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703243926; cv=none; d=google.com; s=arc-20160816; b=L8yl0ILz1T/TD7tGClwJpWJ1DwGtK3wmyTi2hEQw/v5n3vt/MWQzoW7ES8b8qQ8mZk yoE4n4URah+Ae1mBIfEVtkdH9IQHxwJ32FBOB0LPqd1RWdPjcCtxqZNMGlhf4zXHB20Y 3HD9Xhwd5UnW3zxWiTkKxVKEAxKjWxY9dmWWIrJyxDsvFTGLjXU9kl5qpqHWrHQQArjA qbxzW9U0fVMO50GWzpAschlJ2fDNIZ+e2JIgQjwcAz6/IMqKT+lfAKBnZSj6klPog2Mt JT3ZVuNliS9xFaolAhBA1bw6jzTHk8MCfuo44C4O0tRfF/nM408stMP524QBfRTbdPyj 1JDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vZCJsoLyOmkKAX7ht3HFrFwteoJzV+g0RP8tYskDzk0=; fh=2aiQaFmMxr/QDQUBgVVkbK+3ADRUnOteOvF/xtBRB/I=; b=ohujD1lriOtAws4xCKo1RQxJmsMmpzQFuGlfNNJTXZRoDXvbu0P+nQ4090PqDtROOs 3Bdi1cGWFSRc5FwQWCi2x/Yt8qK4Q7imoCaEcBuGmbsKMlzBFzmWc/QQy4ir0pxkgI6a YBiOXD416TXYo1Y2xeqnw4A8xU+hXJ0yYFhIhVa/2cvred8H/7JFhdGO8bANcBe8YVQX YN6yfL9eIoXmmhpXQFHWako5BmtlgqR5ZbvASsBPkKZCFoEHAwzdkkEWikbS32lxoNIQ dBAR/5CcTePZ24UbOrXuFr4S6LvOyvuDendsNFJiPhWX8PssdMGAKzid3lLIil2W3eDb IK+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=vJjotAoy; spf=pass (google.com: domain of linux-kernel+bounces-9649-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-9649-ouuuleilei=gmail.com@vger.kernel.org" Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Some inputs may be grounded, like in the AO domain of some SoCs. Drop the parent number parameter and make this is constant. This is also done to make addition of generic meson8 compatible easier. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 2971bbf3b5e7..ef50c337f444 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -60,7 +60,7 @@ #define MISC_A_EN BIT(0) #define MESON_NUM_PWMS 2 -#define MESON_MAX_MUX_PARENTS 4 +#define MESON_NUM_MUX_PARENTS 4 static struct meson_pwm_channel_data { u8 reg_offset; @@ -98,7 +98,6 @@ struct meson_pwm_channel { struct meson_pwm_data { const char * const *parent_names; - unsigned int num_parents; }; struct meson_pwm { @@ -343,7 +342,6 @@ static const char * const pwm_meson8b_parent_names[] = { static const struct meson_pwm_data pwm_meson8b_data = { .parent_names = pwm_meson8b_parent_names, - .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), }; /* @@ -351,12 +349,11 @@ static const struct meson_pwm_data pwm_meson8b_data = { * The last 2 are grounded */ static const char * const pwm_gxbb_ao_parent_names[] = { - "xtal", "clk81" + "xtal", "clk81", NULL, NULL, }; static const struct meson_pwm_data pwm_gxbb_ao_data = { .parent_names = pwm_gxbb_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; static const char * const pwm_axg_ee_parent_names[] = { @@ -365,7 +362,6 @@ static const char * const pwm_axg_ee_parent_names[] = { static const struct meson_pwm_data pwm_axg_ee_data = { .parent_names = pwm_axg_ee_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), }; static const char * const pwm_axg_ao_parent_names[] = { @@ -374,7 +370,6 @@ static const char * const pwm_axg_ao_parent_names[] = { static const struct meson_pwm_data pwm_axg_ao_data = { .parent_names = pwm_axg_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), }; static const char * const pwm_g12a_ao_ab_parent_names[] = { @@ -383,16 +378,14 @@ static const char * const pwm_g12a_ao_ab_parent_names[] = { static const struct meson_pwm_data pwm_g12a_ao_ab_data = { .parent_names = pwm_g12a_ao_ab_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), }; static const char * const pwm_g12a_ao_cd_parent_names[] = { - "xtal", "g12a_ao_clk81", + "xtal", "g12a_ao_clk81", NULL, NULL, }; static const struct meson_pwm_data pwm_g12a_ao_cd_data = { .parent_names = pwm_g12a_ao_cd_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), }; static const struct of_device_id meson_pwm_matches[] = { @@ -434,13 +427,13 @@ MODULE_DEVICE_TABLE(of, meson_pwm_matches); static int meson_pwm_init_channels(struct meson_pwm *meson) { - struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {}; + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; struct device *dev = meson->chip.dev; unsigned int i; char name[255]; int err; - for (i = 0; i < meson->data->num_parents; i++) { + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { mux_parent_data[i].index = -1; mux_parent_data[i].name = meson->data->parent_names[i]; } @@ -456,7 +449,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) init.ops = &clk_mux_ops; init.flags = 0; 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Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index ef50c337f444..15c44185d784 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -101,7 +101,6 @@ struct meson_pwm_data { }; struct meson_pwm { - struct pwm_chip chip; const struct meson_pwm_data *data; struct meson_pwm_channel channels[MESON_NUM_PWMS]; void __iomem *base; @@ -114,7 +113,7 @@ struct meson_pwm { static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip) { - return container_of(chip, struct meson_pwm, chip); + return dev_get_drvdata(chip->dev); } static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) @@ -146,6 +145,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, const struct pwm_state *state) { struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; + struct device *dev = pwm->chip->dev; unsigned int cnt, duty_cnt; unsigned long fin_freq; u64 duty, period, freq; @@ -168,19 +168,19 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, fin_freq = clk_round_rate(channel->clk, freq); if (fin_freq == 0) { - dev_err(meson->chip.dev, "invalid source clock frequency\n"); + dev_err(dev, "invalid source clock frequency\n"); return -EINVAL; } - dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); + dev_dbg(dev, "fin_freq: %lu Hz\n", fin_freq); cnt = div_u64(fin_freq * period, NSEC_PER_SEC); if (cnt > 0xffff) { - dev_err(meson->chip.dev, "unable to get period cnt\n"); + dev_err(dev, "unable to get period cnt\n"); return -EINVAL; } - dev_dbg(meson->chip.dev, "period=%llu cnt=%u\n", period, cnt); + dev_dbg(dev, "period=%llu cnt=%u\n", period, cnt); if (duty == period) { channel->hi = cnt; @@ -191,7 +191,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, } else { duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC); - dev_dbg(meson->chip.dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt); + dev_dbg(dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt); channel->hi = duty_cnt; channel->lo = cnt - duty_cnt; @@ -214,7 +214,7 @@ static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) err = clk_set_rate(channel->clk, channel->rate); if (err) - dev_err(meson->chip.dev, "setting clock rate failed\n"); + dev_err(pwm->chip->dev, "setting clock rate failed\n"); spin_lock_irqsave(&meson->lock, flags); @@ -425,10 +425,10 @@ static const struct of_device_id meson_pwm_matches[] = { }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -static int meson_pwm_init_channels(struct meson_pwm *meson) +static int meson_pwm_init_channels(struct device *dev) { struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; - struct device *dev = meson->chip.dev; + struct meson_pwm *meson = dev_get_drvdata(dev); unsigned int i; char name[255]; int err; @@ -438,7 +438,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) mux_parent_data[i].name = meson->data->parent_names[i]; } - for (i = 0; i < meson->chip.npwm; i++) { + for (i = 0; i < MESON_NUM_PWMS; i++) { struct meson_pwm_channel *channel = &meson->channels[i]; struct clk_parent_data div_parent = {}, gate_parent = {}; struct clk_init_data init = {}; @@ -519,28 +519,35 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) static int meson_pwm_probe(struct platform_device *pdev) { struct meson_pwm *meson; + struct pwm_chip *chip; int err; + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); if (!meson) return -ENOMEM; + platform_set_drvdata(pdev, meson); + meson->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(meson->base)) return PTR_ERR(meson->base); spin_lock_init(&meson->lock); - meson->chip.dev = &pdev->dev; - meson->chip.ops = &meson_pwm_ops; - meson->chip.npwm = MESON_NUM_PWMS; + chip->dev = &pdev->dev; + chip->ops = &meson_pwm_ops; + chip->npwm = MESON_NUM_PWMS; meson->data = of_device_get_match_data(&pdev->dev); - err = meson_pwm_init_channels(meson); + err = meson_pwm_init_channels(&pdev->dev); if (err < 0) return err; - err = devm_pwmchip_add(&pdev->dev, &meson->chip); + err = devm_pwmchip_add(&pdev->dev, chip); if (err < 0) return dev_err_probe(&pdev->dev, err, "failed to register PWM chip\n"); From patchwork Fri Dec 22 11:16:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 182636 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp990401dyi; Fri, 22 Dec 2023 03:19:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IESbvbePYV+kFUy2Prby7OKwdwM8UzU5D/r6lw7tgb0A+TBZdwS+HMYNp2x0VD4Mhd8ocoD X-Received: by 2002:a17:90b:1915:b0:28b:f365:aa8a with SMTP id mp21-20020a17090b191500b0028bf365aa8amr618717pjb.73.1703243940519; Fri, 22 Dec 2023 03:19:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703243940; cv=none; d=google.com; s=arc-20160816; b=RyE+blvVCk8edtlB+wq2+u4GJ9JzwS40xofTdC/TONm1a9KNIntoTsENb3ZHx/FQKh DWjX+Ghr4DNQrTRLC6OT1NRslLmVmB9bo6nW0dgWwHqQBntSWXYXLQqvUUr2KOvgINv3 oA66KpVm58lvmDzzNesod8gc1eEh9wKdpBDOxaGvAM5JTQQ7KERlrEmxYKTwmmUM5xv8 2PJk5Ty5df+MUq95TF7o306XPrDXC42BsQC8yXNjEGoCU2UkKE+5CwWbVShilUj6mbVK ujrk5+V5nihl9u8TlJOlD9idlQEHb507SjtM+LtN1iExqDCH16UoZ6YaV9a04mCW4p5D kslQ== ARC-Message-Signature: i=1; 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There is no need to carry this around in the device data. Just let devres deal with it. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 67 ++++++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 28 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 15c44185d784..fb113bc8da29 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -90,9 +90,6 @@ struct meson_pwm_channel { unsigned int hi; unsigned int lo; - struct clk_mux mux; - struct clk_divider div; - struct clk_gate gate; struct clk *clk; }; @@ -442,6 +439,13 @@ static int meson_pwm_init_channels(struct device *dev) struct meson_pwm_channel *channel = &meson->channels[i]; struct clk_parent_data div_parent = {}, gate_parent = {}; struct clk_init_data init = {}; + struct clk_divider *div; + struct clk_gate *gate; + struct clk_mux *mux; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); @@ -451,63 +455,70 @@ static int meson_pwm_init_channels(struct device *dev) init.parent_data = mux_parent_data; init.num_parents = MESON_NUM_MUX_PARENTS; - channel->mux.reg = meson->base + REG_MISC_AB; - channel->mux.shift = - meson_pwm_per_channel_data[i].clk_sel_shift; - channel->mux.mask = MISC_CLK_SEL_MASK; - channel->mux.flags = 0; - channel->mux.lock = &meson->lock; - channel->mux.table = NULL; - channel->mux.hw.init = &init; + mux->reg = meson->base + REG_MISC_AB; + mux->shift = meson_pwm_per_channel_data[i].clk_sel_shift; + mux->mask = MISC_CLK_SEL_MASK; + mux->flags = 0; + mux->lock = &meson->lock; + mux->table = NULL; + mux->hw.init = &init; - err = devm_clk_hw_register(dev, &channel->mux.hw); + err = devm_clk_hw_register(dev, &mux->hw); if (err) return dev_err_probe(dev, err, "failed to register %s\n", name); + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i); init.name = name; init.ops = &clk_divider_ops; init.flags = CLK_SET_RATE_PARENT; div_parent.index = -1; - div_parent.hw = &channel->mux.hw; + div_parent.hw = &mux->hw; init.parent_data = &div_parent; init.num_parents = 1; - channel->div.reg = meson->base + REG_MISC_AB; - channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift; - channel->div.width = MISC_CLK_DIV_WIDTH; - channel->div.hw.init = &init; - channel->div.flags = 0; - channel->div.lock = &meson->lock; + div->reg = meson->base + REG_MISC_AB; + div->shift = meson_pwm_per_channel_data[i].clk_div_shift; + div->width = MISC_CLK_DIV_WIDTH; + div->hw.init = &init; + div->flags = 0; + div->lock = &meson->lock; - err = devm_clk_hw_register(dev, &channel->div.hw); + err = devm_clk_hw_register(dev, &div->hw); if (err) return dev_err_probe(dev, err, "failed to register %s\n", name); + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); init.name = name; init.ops = &clk_gate_ops; init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; gate_parent.index = -1; - gate_parent.hw = &channel->div.hw; + gate_parent.hw = &div->hw; init.parent_data = &gate_parent; init.num_parents = 1; - channel->gate.reg = meson->base + REG_MISC_AB; - channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; - channel->gate.hw.init = &init; - channel->gate.flags = 0; - channel->gate.lock = &meson->lock; + gate->reg = meson->base + REG_MISC_AB; + gate->bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; + gate->hw.init = &init; + gate->flags = 0; + gate->lock = &meson->lock; - err = devm_clk_hw_register(dev, &channel->gate.hw); + err = devm_clk_hw_register(dev, &gate->hw); if (err) return dev_err_probe(dev, err, "failed to register %s\n", name); - channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL); + channel->clk = devm_clk_hw_get_clk(dev, &gate->hw, NULL); if (IS_ERR(channel->clk)) return dev_err_probe(dev, PTR_ERR(channel->clk), "failed to register %s\n", name); From patchwork Fri Dec 22 11:16:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 182638 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2483:b0:fb:cd0c:d3e with SMTP id q3csp990540dyi; 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bh=WLdzLfSEEVamw81pFt4PJ3qeYp2a8WvdFrJ9tUWJ7PY=; b=kOpBlCRrtVTlGnbBMKUcmd4v4UQaPJMdSr/dr570gsafG8fYUzNfWLdn427Ly4BMuH LX3163HWgVpQz3uU8TLClMS8V5PB/5FHaJNQj1YAZhr8EYDljIicY3F+qWlOoCnKGwZ3 TuKhdR7Ve0iUYsD+OJXwDPYUNylEVvmRc+P+RjLuyJ56se3afozZGVGhYgzxibwHHJBM 2RaMADZV0G/hq4mnpQED/KTyo2qwvle6bNeHONjTSUm5Xa+czk44/o0Y4xgLfINaGGuA M/xGUpLDZjp3/Q1H4n7aEfqm1g1oTOysn/oIkxWU28X0m57nNBZ8m+gvxf0t8Acf2Hqk igoA== X-Gm-Message-State: AOJu0Yz2iVOzAf5ft65iOTq32PY6DGP+D2oxPqhaJAWuLg08CuO63AbC Rqt8GdIv4tX0jfGh3EuSoMWb9IPGtHxEjQ== X-Received: by 2002:a2e:2407:0:b0:2cc:2678:6d35 with SMTP id k7-20020a2e2407000000b002cc26786d35mr573523ljk.6.1703243846824; Fri, 22 Dec 2023 03:17:26 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:c099:e596:3179:b0fa]) by smtp.googlemail.com with ESMTPSA id f8-20020adffcc8000000b003366b500047sm4054069wrs.50.2023.12.22.03.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 03:17:26 -0800 (PST) From: Jerome Brunet To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao Subject: [PATCH v4 6/6] pwm: meson: add generic compatible for meson8 to sm1 Date: Fri, 22 Dec 2023 12:16:54 +0100 Message-ID: <20231222111658.832167-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231222111658.832167-1-jbrunet@baylibre.com> References: <20231222111658.832167-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785980734948848005 X-GMAIL-MSGID: 1785980734948848005 Introduce a new compatible support in the Amlogic PWM driver. The PWM HW is actually the same for all SoCs supported so far. A specific compatible is needed only because the clock sources of the PWMs are hard-coded in the driver. It is better to have the clock source described in DT but this changes the bindings so a new compatible must be introduced. When all supported platform have migrated to the new compatible, support for the legacy ones may be removed from the driver. The addition of this new compatible makes the old ones obsolete, as described in the DT documentation. Adding a callback to setup the clock will also make it easier to add support for the new PWM HW found in a1, s4, c3 and t7 SoC families. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 240 ++++++++++++++++++++++++---------------- 1 file changed, 143 insertions(+), 97 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index fb113bc8da29..9c0a8a6e4f48 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -95,6 +95,7 @@ struct meson_pwm_channel { struct meson_pwm_data { const char * const *parent_names; + int (*channels_init)(struct device *dev); }; struct meson_pwm { @@ -333,108 +334,14 @@ static const struct pwm_ops meson_pwm_ops = { .get_state = meson_pwm_get_state, }; -static const char * const pwm_meson8b_parent_names[] = { - "xtal", NULL, "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_meson8b_data = { - .parent_names = pwm_meson8b_parent_names, -}; - -/* - * Only the 2 first inputs of the GXBB AO PWMs are valid - * The last 2 are grounded - */ -static const char * const pwm_gxbb_ao_parent_names[] = { - "xtal", "clk81", NULL, NULL, -}; - -static const struct meson_pwm_data pwm_gxbb_ao_data = { - .parent_names = pwm_gxbb_ao_parent_names, -}; - -static const char * const pwm_axg_ee_parent_names[] = { - "xtal", "fclk_div5", "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_axg_ee_data = { - .parent_names = pwm_axg_ee_parent_names, -}; - -static const char * const pwm_axg_ao_parent_names[] = { - "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" -}; - -static const struct meson_pwm_data pwm_axg_ao_data = { - .parent_names = pwm_axg_ao_parent_names, -}; - -static const char * const pwm_g12a_ao_ab_parent_names[] = { - "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" -}; - -static const struct meson_pwm_data pwm_g12a_ao_ab_data = { - .parent_names = pwm_g12a_ao_ab_parent_names, -}; - -static const char * const pwm_g12a_ao_cd_parent_names[] = { - "xtal", "g12a_ao_clk81", NULL, NULL, -}; - -static const struct meson_pwm_data pwm_g12a_ao_cd_data = { - .parent_names = pwm_g12a_ao_cd_parent_names, -}; - -static const struct of_device_id meson_pwm_matches[] = { - { - .compatible = "amlogic,meson8b-pwm", - .data = &pwm_meson8b_data - }, - { - .compatible = "amlogic,meson-gxbb-pwm", - .data = &pwm_meson8b_data - }, - { - .compatible = "amlogic,meson-gxbb-ao-pwm", - .data = &pwm_gxbb_ao_data - }, - { - .compatible = "amlogic,meson-axg-ee-pwm", - .data = &pwm_axg_ee_data - }, - { - .compatible = "amlogic,meson-axg-ao-pwm", - .data = &pwm_axg_ao_data - }, - { - .compatible = "amlogic,meson-g12a-ee-pwm", - .data = &pwm_meson8b_data - }, - { - .compatible = "amlogic,meson-g12a-ao-pwm-ab", - .data = &pwm_g12a_ao_ab_data - }, - { - .compatible = "amlogic,meson-g12a-ao-pwm-cd", - .data = &pwm_g12a_ao_cd_data - }, - {}, -}; -MODULE_DEVICE_TABLE(of, meson_pwm_matches); - -static int meson_pwm_init_channels(struct device *dev) +static int meson_pwm_init_clocks_legacy(struct device *dev, + struct clk_parent_data *mux_parent_data) { - struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; struct meson_pwm *meson = dev_get_drvdata(dev); unsigned int i; char name[255]; int err; - for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { - mux_parent_data[i].index = -1; - mux_parent_data[i].name = meson->data->parent_names[i]; - } - for (i = 0; i < MESON_NUM_PWMS; i++) { struct meson_pwm_channel *channel = &meson->channels[i]; struct clk_parent_data div_parent = {}, gate_parent = {}; @@ -527,6 +434,145 @@ static int meson_pwm_init_channels(struct device *dev) return 0; } +static int meson_pwm_init_channels_legacy(struct device *dev) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; + struct meson_pwm *meson = dev_get_drvdata(dev); + int i; + + dev_warn_once(dev, "using obsolete compatible, please consider updating dt\n"); + + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { + mux_parent_data[i].index = -1; + mux_parent_data[i].name = meson->data->parent_names[i]; + } + + return meson_pwm_init_clocks_legacy(dev, mux_parent_data); +} + +static int meson_pwm_init_channels_meson8b_v2(struct device *dev) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; + int i; + + /* + * NOTE: Instead of relying on the hard coded names in the driver + * as the legacy version, this relies on DT to provide the list of + * clocks. + * For once, using input numbers actually makes more sense than names. + * Also DT requires clock-names to be explicitly ordered, so there is + * no point bothering with clock names in this case. + */ + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) + mux_parent_data[i].index = i; + + return meson_pwm_init_clocks_legacy(dev, mux_parent_data); +} + +static const char * const pwm_meson8b_parent_names[] = { + "xtal", NULL, "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_meson8b_data = { + .parent_names = pwm_meson8b_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +/* + * Only the 2 first inputs of the GXBB AO PWMs are valid + * The last 2 are grounded + */ +static const char * const pwm_gxbb_ao_parent_names[] = { + "xtal", "clk81", NULL, NULL, +}; + +static const struct meson_pwm_data pwm_gxbb_ao_data = { + .parent_names = pwm_gxbb_ao_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_g12a_ao_ab_parent_names[] = { + "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_g12a_ao_ab_data = { + .parent_names = pwm_g12a_ao_ab_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_g12a_ao_cd_parent_names[] = { + "xtal", "g12a_ao_clk81", NULL, NULL, +}; + +static const struct meson_pwm_data pwm_g12a_ao_cd_data = { + .parent_names = pwm_g12a_ao_cd_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const struct meson_pwm_data pwm_meson8_v2_data = { + .channels_init = meson_pwm_init_channels_meson8b_v2, +}; + +static const struct of_device_id meson_pwm_matches[] = { + { + .compatible = "amlogic,meson8-pwm-v2", + .data = &pwm_meson8_v2_data + }, + /* The following compatibles are obsolete */ + { + .compatible = "amlogic,meson8b-pwm", + .data = &pwm_meson8b_data + }, + { + .compatible = "amlogic,meson-gxbb-pwm", + .data = &pwm_meson8b_data + }, + { + .compatible = "amlogic,meson-gxbb-ao-pwm", + .data = &pwm_gxbb_ao_data + }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, + { + .compatible = "amlogic,meson-g12a-ee-pwm", + .data = &pwm_meson8b_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-ab", + .data = &pwm_g12a_ao_ab_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-cd", + .data = &pwm_g12a_ao_cd_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, meson_pwm_matches); + static int meson_pwm_probe(struct platform_device *pdev) { struct meson_pwm *meson; @@ -554,7 +600,7 @@ static int meson_pwm_probe(struct platform_device *pdev) meson->data = of_device_get_match_data(&pdev->dev); - err = meson_pwm_init_channels(&pdev->dev); + err = meson->data->channels_init(&pdev->dev); if (err < 0) return err;