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[2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id p31-20020a056a000a1f00b006ce921fc8f6si5277414pfh.187.2023.12.20.06.58.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 06:58:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-7096-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=8J7Y6tqk; spf=pass (google.com: domain of linux-kernel+bounces-7096-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7096-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id C7811287915 for ; Wed, 20 Dec 2023 14:58:54 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D3FC1405DB; Wed, 20 Dec 2023 14:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="8J7Y6tqk" X-Original-To: linux-kernel@vger.kernel.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 505BE3E466; Wed, 20 Dec 2023 14:58:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKAmXS2012278; Wed, 20 Dec 2023 15:57:55 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=d0/rsgmO/GK6El7aXTcbV+jmBIbAy5RKIXMeVlFeF38=; b=8J 7Y6tqkzguM7UnkU895zdVpGCTD78yZkw4YZeesU4wSK28IT6jGCbVIUej0Eyw1sO mCTl1vUrMimKUh9BS7iLm5QUdOVzCZFBqnsk78Ca1jjiQqHFPJkXShvUVGDqHow6 G28x2s0R4XC3cIMJhzxKlu16RJ+Doh689NzUTIoSH45WtY0dhgG/j5pRf/mXHbs6 DtLiZNey5t5NlHJtZiPx58ePa2C6er+eXQH+xYoBROZjO1hqjNT8ADN04GLP73Zy NUUGXdP9p7/8AtNDmznda0NDpLlRPs2ArPQOp9AqU9SAt52uiglnxG8oJqNhYlQm mYNRS+7OSER3d+8kUHig== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v13nhhqt2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:57:55 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 524C7100059; Wed, 20 Dec 2023 15:57:55 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4A07721B511; Wed, 20 Dec 2023 15:57:55 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:57:54 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 01/10] counter: stm32-timer-cnt: rename quadrature signal Date: Wed, 20 Dec 2023 15:57:17 +0100 Message-ID: <20231220145726.640627-2-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_08,2023-12-20_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785813362623287980 X-GMAIL-MSGID: 1785813362623287980 Drop the Quadrature convention in the signal name. On stm32-timer: - Quadrature A signal corresponds to timer input ch1, hence "Channel 1" - Quadrature B signal corresponds to timer input ch2, hence "Channel 2". So name these signals after their channel. I suspect it referred to the (unique) quadrature counter support earlier, but the physical input really is CH1/CH2. This will be easier to support other counter modes. Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- Changes in v2: - Drop the "Quadrature" convention from the signal name, as suggested by William --- drivers/counter/stm32-timer-cnt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 6206d2dc3d47..36d812ddf162 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -279,11 +279,11 @@ static const struct counter_ops stm32_timer_cnt_ops = { static struct counter_signal stm32_signals[] = { { .id = 0, - .name = "Channel 1 Quadrature A" + .name = "Channel 1" }, { .id = 1, - .name = "Channel 1 Quadrature B" + .name = "Channel 2" } }; From patchwork Wed Dec 20 14:57:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181667 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2694654dyi; Wed, 20 Dec 2023 06:58:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IFmZW2vL4qGd3+BAo+xUajKzyb9X61C8ip7ioGiTRizFMhfkUi9na0rixnDSXpBJvLPevhz X-Received: by 2002:a17:903:280c:b0:1d3:e250:eb68 with SMTP id kp12-20020a170903280c00b001d3e250eb68mr2583338plb.110.1703084331886; Wed, 20 Dec 2023 06:58:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084331; cv=none; d=google.com; s=arc-20160816; b=p8JoLAqJlYAhbWxudW4vP0xizW2hnjwN+4Y2xHa11EwQuD+nhqI8YRG4RgkqtzmR+Y RPS6MdT46a8wLvjSa5k66KBtfzG3MX0DshFSjnjRn53ErFT2OzaYkJPgTwT683/hjpIN wD3DpEwOUQXWh0HZo8aONLcQkkyFJaHWFvxtkPF+dUiVUFDhgMybbgmOM0PMg2evA0Fi bBtVgM3O/khMA7RwisVAJrL1sBgCiqxoO5S3jWlML8Kwh0k4A9hs6IkJ+kRRuYQX2V8J UDm96QbzDyVQ4xJ95qDA4gedCEsIilfMU5Bc/mJNR8gKTZ6ner04oozq4HL/T2rMevUq dulg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=su2Pq6yXzJ+By01elmOLMUH+D+u4lMRIHEYBe4cjT9E=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=dodH5NIt2QR9osUYI6hygpdbA9G0mYQmBAiUVq8cBIpoG68JIF4TlQpY97j6Yze7Xz +ej9qgExfPVTg5DdC54xeAa6ZdSQ3LYbzWKvyiAuZ3OLuQ/zK47xlaDdH3hw7RM1szlm TtGMCLOVPZEkBqL4TZZYLq++bkR6P8UR2VUohFTPLvaZ3zj36crYjC6ozso0ykhC95h2 XwMEnNqpqIN/64+uopciAwGeJtx4Lul71r/eQ4rf/18vkX126FPNTIbTC0AnSzDMyouN 7P3CegjdzNyJg8cvpgrUzvM996sdosXfYsDCGdAo1fIIYwgsGY645WBvWOmxNqkCU5t1 86qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=0fffFvbE; spf=pass (google.com: domain of linux-kernel+bounces-7095-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7095-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id jf14-20020a170903268e00b001d3e44faf1bsi2476998plb.242.2023.12.20.06.58.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 06:58:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-7095-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=0fffFvbE; spf=pass (google.com: domain of linux-kernel+bounces-7095-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7095-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id E2832287E1B for ; Wed, 20 Dec 2023 14:58:48 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 956F63FE43; Wed, 20 Dec 2023 14:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="0fffFvbE" X-Original-To: linux-kernel@vger.kernel.org Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4106F3E460; Wed, 20 Dec 2023 14:58:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKEBau8025826; Wed, 20 Dec 2023 15:57:58 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=su2Pq6yXzJ+By01elmOLMUH+D+u4lMRIHEYBe4cjT9E=; b=0f ffFvbESOaHOL7itMtJxoKAtLCkR179P7KSvvH1t1hnF+By3KkbeDKUT1obhC2Tvv DcbU81pGJDdLlF/1HerK1ne+Z9/eBNRgb4pW99yxF+SPcoetClOcCwL8WbJuYESV tPQ+4fLAfH5ErRMWkOlbWNxa9RxNT6m+TWA3dSLDsPYs1poRQhmzcRNYHRqFMmm1 B2f9RD2pagzIXmMXb8Ofv5q+gh4R7ycdomCQXjOxBoJw2ivYINz+ibCdPfLhgDw/ /B0l8cxWrxK3otDWrdCUhu56q3Wvd7ceQx54lcikC3wR31dghhBo2adn+KYj2T9j eo8YOK3A1oMFHWSZjLuA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v3q80u4d7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:57:58 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 26FF8100057; Wed, 20 Dec 2023 15:57:58 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1DF8621B512; Wed, 20 Dec 2023 15:57:58 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:57:55 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 02/10] counter: stm32-timer-cnt: rename counter Date: Wed, 20 Dec 2023 15:57:18 +0100 Message-ID: <20231220145726.640627-3-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_08,2023-12-20_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785813356232085328 X-GMAIL-MSGID: 1785813356232085328 The STM32 timer may count on various sources or channels. The counter isn't specifically counting on channe1 1. So rename it to avoid a confusion. Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- drivers/counter/stm32-timer-cnt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 36d812ddf162..668e9d1061d3 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -302,7 +302,7 @@ static struct counter_synapse stm32_count_synapses[] = { static struct counter_count stm32_counts = { .id = 0, - .name = "Channel 1 Count", + .name = "STM32 Timer Counter", .functions_list = stm32_count_functions, .num_functions = ARRAY_SIZE(stm32_count_functions), .synapses = stm32_count_synapses, From patchwork Wed Dec 20 14:57:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181669 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2695011dyi; Wed, 20 Dec 2023 06:59:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IFBx0n+RdnToVWUEKlhvV/SMfA3QKNhDdr/Fl+8LsIjJyGM/yeoMSUKe9auh21jSpPM1aQE X-Received: by 2002:a17:90a:8d86:b0:286:c138:c2b7 with SMTP id d6-20020a17090a8d8600b00286c138c2b7mr13271653pjo.49.1703084376263; Wed, 20 Dec 2023 06:59:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084376; cv=none; d=google.com; s=arc-20160816; b=WbWEdNykjp+1slrhvMs/4KQ0mFFX6vE0Mrpdho3dZrutCIAbnrjNPKtIt4ebjazTib mhm74sJb3dOWkzxgBduBKtJqdVKeR0VmoRPSJr6HYQFFfFJcmg9A+vGV+ySf84hF1GZA reJDB1NjPydGe85E9+k4I7xnAgZDZYB+vd0wqVY7pQeYwcxBdpxRwFdpZWOiDW9RADjs 4fg+iZ9+FE82UZ9EKbYLBB7V+CroFcGHFL9y7wohEAbFBODTFk++SLdpGn8TLLdxfA4O 7CFAL2kwnbiWNUvt7ZVXC2qxmbgAjt7qm8Bae0669/bTXliqDASiSgm3XXNqv1sQRn+B pXkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=V9ljivPttp2rz/EBN+xGrc8EnIawGBMvk5JANbG9TY8=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=gv5mwGURnuwam6bZ17kOpqp0aT0flq9TBcjlNeIT/J48g4DKH6Jw4wHxN3QvzzZm6r fFa684p4HYr3aBrzjtBAyCdcIzJlUrXWokSAj56Cs3ZyKtLCuT7gu9X7ppOR6Mghd+nj 5WWic9yL21AcxYIJevR1R/ddBXOn9aQuzmyI/NshMN8Td/IWvFnPP+/4hfYdVoapXJpg 8dEw5fQDqvD1N7yVZ27ei48sK2AP87jpiqTU5b+0EFZNRplgF5Iz84pZJZCYKcyKdn+M 8fvBsZIlZEPKDEibtN367fJI0vJOlBoc4GQ+Glhryc9eEfSeG63nHF+AMbjNQM6qkMnx pHhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=GVG0yZJo; spf=pass (google.com: domain of linux-kernel+bounces-7098-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7098-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id a3-20020a17090a8c0300b0028bce459aaesi1644692pjo.184.2023.12.20.06.59.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 06:59:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-7098-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=GVG0yZJo; spf=pass (google.com: domain of linux-kernel+bounces-7098-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7098-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 681B9281718 for ; Wed, 20 Dec 2023 14:59:13 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2E73640C0D; Wed, 20 Dec 2023 14:58:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="GVG0yZJo" X-Original-To: linux-kernel@vger.kernel.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF2FA3E474; Wed, 20 Dec 2023 14:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKASCsi015122; Wed, 20 Dec 2023 15:57:57 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=V9ljivPttp2rz/EBN+xGrc8EnIawGBMvk5JANbG9TY8=; b=GV G0yZJo2HpQWxVho3iuC+MCaByn5qEXgfMzSfchradW6/gJeQS6N6SZQtvdfAQqRX T0eUUE+ZSTUNmZ52dMQ1WziMFfyf7p/JjN7GJ0KghqZisDz+5xy77NcIhnIYA3/y v9iSpHtMfc7Zqrg4JFAHixG3/JexhW/euoOnGhIj5G1zusC8Bb+zT06CFNdAJfpr Tx171HjiZ5/BG8l6LoNQoTJQzV4r2HbQiYa/PwBF5OeOmiHPyTUZBjXWg8EqnKEv 9LluO9cBBIZoVrg3Tg183Gse7vodT9Z5hRqJ+rF8rBiJr/34oJuRnR1uGPCYIQOC A6Hrrmt4iv29ie29u6Dw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v1pb4qwkn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:57:57 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 01E7A100057; Wed, 20 Dec 2023 15:57:57 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EBA3221B512; Wed, 20 Dec 2023 15:57:56 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:57:56 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 03/10] counter: stm32-timer-cnt: adopt signal definitions Date: Wed, 20 Dec 2023 15:57:19 +0100 Message-ID: <20231220145726.640627-4-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_08,2023-12-20_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785813402970085381 X-GMAIL-MSGID: 1785813402970085381 Adopt signals definitions to ease later signals additions. There are no intended functional changes here. Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- Changes in v3: New patch split from "counter: stm32-timer-cnt: introduce clock signal" --- drivers/counter/stm32-timer-cnt.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 668e9d1061d3..c34747d7857e 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -21,6 +21,9 @@ #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ TIM_CCER_CC2P | TIM_CCER_CC2NP) +#define STM32_CH1_SIG 0 +#define STM32_CH2_SIG 1 + struct stm32_timer_regs { u32 cr1; u32 cnt; @@ -247,14 +250,14 @@ static int stm32_action_read(struct counter_device *counter, return 0; case COUNTER_FUNCTION_QUADRATURE_X2_A: /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ - if (synapse->signal->id == count->synapses[0].signal->id) + if (synapse->signal->id == STM32_CH1_SIG) *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; else *action = COUNTER_SYNAPSE_ACTION_NONE; return 0; case COUNTER_FUNCTION_QUADRATURE_X2_B: /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ - if (synapse->signal->id == count->synapses[1].signal->id) + if (synapse->signal->id == STM32_CH2_SIG) *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; else *action = COUNTER_SYNAPSE_ACTION_NONE; @@ -278,11 +281,11 @@ static const struct counter_ops stm32_timer_cnt_ops = { static struct counter_signal stm32_signals[] = { { - .id = 0, + .id = STM32_CH1_SIG, .name = "Channel 1" }, { - .id = 1, + .id = STM32_CH2_SIG, .name = "Channel 2" } }; @@ -291,12 +294,12 @@ static struct counter_synapse stm32_count_synapses[] = { { .actions_list = stm32_synapse_actions, .num_actions = ARRAY_SIZE(stm32_synapse_actions), - .signal = &stm32_signals[0] + .signal = &stm32_signals[STM32_CH1_SIG] }, { .actions_list = stm32_synapse_actions, .num_actions = ARRAY_SIZE(stm32_synapse_actions), - .signal = &stm32_signals[1] + .signal = &stm32_signals[STM32_CH2_SIG] } }; From patchwork Wed Dec 20 14:57:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181671 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2695087dyi; Wed, 20 Dec 2023 06:59:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IGp0i4uRsRNhZ2ZcB83WW3JGCz7iSG8DnolxerereSTdFWydR4XCLS4eNmuMK3fnCNM8sB6 X-Received: by 2002:a17:902:9a49:b0:1d3:e133:7171 with SMTP id x9-20020a1709029a4900b001d3e1337171mr3227731plv.32.1703084383467; Wed, 20 Dec 2023 06:59:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084383; cv=none; d=google.com; s=arc-20160816; b=vpuiscsGCG1THvl8BINDlqBpDp8CATbc3aan3s7QGkvamkfLnptgBz2aH24/n19grV jRHWN9gVHRgvtdDJ8qfNLKFrdQVicPwqBIQ7Ia3ByBzRik+XYWsDEkXJsRmcZ/9Q4WQT c3113kzTrVtS9bGqCnv+VYn5HNOr5MSnvd2TznlyVrfwCf323X6fgQCvoLh+gCBAWERE KuMwRgZrnyGpy1+qWsOyy7AG5pUemzNuUSSWuAe8IJZEJVjNNTKM6WVT45jvXf170FKC IPIQwnxsq3CwVbR46iuUrPO3CNW3st7H3IL4+N3/i+GEM0++Q94a7gVppmclL5PBrN9I cS7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=g6KFG95QTDX3DDGTxlBut801yEYbV9MUDWmT6tLu8gg=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=d134nh3RTvScuvNFyTIxNBKyEF5qrvwXhmCJEuZUCQs8V4zGdyKrYVq+xUj9DXiuSZ cnJXJCCYOfSo+d3/BDDFFIC+pesvH7QrJ5dijVq2c1gji44+SyrT0YlVPInGQLQ8yqZQ +y9sSDfqm/WT03lAM21OeaG1gfkiaGOE/nQC/xUdly3ldmvmtk9Oh8+buQwyttRbmwDN 8+EwOK4wnoOzR0v4T7iAPPtr5FTOaAvUFOIwxA1ES9F6ainDOjNtg/1wYxz0invrmaXL /JzLYiCfLdoyZ1LFsNySDmE2/KHnXVvARFzt7xWye32aKNFDIOwFRtSnDGBpG2hYCqCx rIdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=L6DX30we; spf=pass (google.com: domain of linux-kernel+bounces-7099-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7099-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id p12-20020a170902e74c00b001d3c5d1834esi4720892plf.557.2023.12.20.06.59.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 06:59:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-7099-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=L6DX30we; spf=pass (google.com: domain of linux-kernel+bounces-7099-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7099-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id B1A512882FB for ; Wed, 20 Dec 2023 14:59:20 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3D15F3B78D; Wed, 20 Dec 2023 14:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="L6DX30we" X-Original-To: linux-kernel@vger.kernel.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE923E46E; Wed, 20 Dec 2023 14:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKAmXS3012278; Wed, 20 Dec 2023 15:57:57 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=g6KFG95QTDX3DDGTxlBut801yEYbV9MUDWmT6tLu8gg=; b=L6 DX30weht13vT7o/awcBqMslP7ZyeQPGDxQ7Z55Tlm2yTiFzPVUsT2NYZLFL5Luj/ WT6yHTIPp4v5XcZX+vIQTXXkfQ2OvW/qlDbxNGTrS2SUPrf9R3XNvYiS9VARyMve J/KyQPQ2mtzg+K7jPutJQYrsmvLIDH+/W7mUe5hQ43kvQS1wKvjHmp4V94N+PZhT ocVsemEA+Ikg5sjimxmGqZGMLwVlYuFhmKlk7pnZlprCbxVI7Yf1ym7ZYSvMxcad /DouPyutjeVuUYiQl9NgGxAz0LeZlmskry1v1fhlC4DkRar0lWJbQ+y1QVSrFFER dCsUKuhGTi8+IOmikxbw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v13nhhqt4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:57:57 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 37102100059; Wed, 20 Dec 2023 15:57:57 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2E31421B512; Wed, 20 Dec 2023 15:57:57 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:57:56 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 04/10] counter: stm32-timer-cnt: introduce clock signal Date: Wed, 20 Dec 2023 15:57:20 +0100 Message-ID: <20231220145726.640627-5-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_08,2023-12-20_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785813410604488235 X-GMAIL-MSGID: 1785813410604488235 Introduce the internal clock signal, used to count when in simple rising function. Also add the "frequency" extension to the clock signal. With this patch, signal action reports a consistent state when "increase" function is used, and the counting frequency: $ echo increase > function $ grep -H "" signal*_action signal0_action:none signal1_action:none signal2_action:rising edge $ echo 1 > enable $ cat count 25425 $ cat count 44439 $ cat ../signal2/frequency 208877930 Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- Changes in v3: - split the patch in 3 parts: signal definition becomes a pre-cursor patch, add the "prescaler" extension in its own patch. - Move the clock signal at the end of the signals array, so existing userspace programs that may rely on signal0 being "Channel 1" for example will remain compatible. --- drivers/counter/stm32-timer-cnt.c | 53 ++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index c34747d7857e..21a9c20c4281 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -23,6 +23,7 @@ #define STM32_CH1_SIG 0 #define STM32_CH2_SIG 1 +#define STM32_CLOCK_SIG 2 struct stm32_timer_regs { u32 cr1; @@ -226,6 +227,10 @@ static struct counter_comp stm32_count_ext[] = { stm32_count_ceiling_write), }; +static const enum counter_synapse_action stm32_clock_synapse_actions[] = { + COUNTER_SYNAPSE_ACTION_RISING_EDGE, +}; + static const enum counter_synapse_action stm32_synapse_actions[] = { COUNTER_SYNAPSE_ACTION_NONE, COUNTER_SYNAPSE_ACTION_BOTH_EDGES @@ -246,7 +251,10 @@ static int stm32_action_read(struct counter_device *counter, switch (function) { case COUNTER_FUNCTION_INCREASE: /* counts on internal clock when CEN=1 */ - *action = COUNTER_SYNAPSE_ACTION_NONE; + if (synapse->signal->id == STM32_CLOCK_SIG) + *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; + else + *action = COUNTER_SYNAPSE_ACTION_NONE; return 0; case COUNTER_FUNCTION_QUADRATURE_X2_A: /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ @@ -264,7 +272,10 @@ static int stm32_action_read(struct counter_device *counter, return 0; case COUNTER_FUNCTION_QUADRATURE_X4: /* counts up/down on both TI1FP1 and TI2FP2 edges */ - *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG) + *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + else + *action = COUNTER_SYNAPSE_ACTION_NONE; return 0; default: return -EINVAL; @@ -279,7 +290,30 @@ static const struct counter_ops stm32_timer_cnt_ops = { .action_read = stm32_action_read, }; +static int stm32_count_clk_get_freq(struct counter_device *counter, + struct counter_signal *signal, u64 *freq) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + + *freq = clk_get_rate(priv->clk); + + return 0; +} + +static struct counter_comp stm32_count_clock_ext[] = { + COUNTER_COMP_SIGNAL_U64("frequency", stm32_count_clk_get_freq, NULL), +}; + static struct counter_signal stm32_signals[] = { + /* + * Need to declare all the signals as a static array, and keep the signals order here, + * even if they're unused or unexisting on some timer instances. It's an abstraction, + * e.g. high level view of the counter features. + * + * Userspace programs may rely on signal0 to be "Channel 1", signal1 to be "Channel 2", + * and so on. When a signal is unexisting, the COUNTER_SYNAPSE_ACTION_NONE can be used, + * to indicate that a signal doesn't affect the counter. + */ { .id = STM32_CH1_SIG, .name = "Channel 1" @@ -287,7 +321,13 @@ static struct counter_signal stm32_signals[] = { { .id = STM32_CH2_SIG, .name = "Channel 2" - } + }, + { + .id = STM32_CLOCK_SIG, + .name = "Clock Signal", + .ext = stm32_count_clock_ext, + .num_ext = ARRAY_SIZE(stm32_count_clock_ext), + }, }; static struct counter_synapse stm32_count_synapses[] = { @@ -300,7 +340,12 @@ static struct counter_synapse stm32_count_synapses[] = { .actions_list = stm32_synapse_actions, .num_actions = ARRAY_SIZE(stm32_synapse_actions), .signal = &stm32_signals[STM32_CH2_SIG] - } + }, + { + .actions_list = stm32_clock_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions), + .signal = &stm32_signals[STM32_CLOCK_SIG] + }, }; static struct counter_count stm32_counts = { From patchwork Wed Dec 20 14:57:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181675 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2696339dyi; Wed, 20 Dec 2023 07:01:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IG2PvbJJpfDrXZAky08YCESEr5Rs7MuulTTH827YoOilFHkitE9meerbqiXkVgLkViXP19m X-Received: by 2002:a50:d087:0:b0:553:ee85:378a with SMTP id v7-20020a50d087000000b00553ee85378amr273951edd.127.1703084465821; Wed, 20 Dec 2023 07:01:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084465; cv=none; d=google.com; s=arc-20160816; b=w+aY80p2+p2grwFDypjKqDUIBcNdb/TQleaNzSDYOUZQ5zNvqDoScWMuULnHkyi9GS l6eAsFRP38yr4jpvPrnj/3hGYCA1cD6/mxw0bTZIpItloHKCBVtGZKoP1v2jDndBsE4s fjgC2noE/3EjD/p8BjZ/GrkfsmpPQd8xbiTRZGPDR4QTPqgjjZTGLu6z0yDcchlf9mK3 UWIRVpae382sEAtLkodxodWlDl2tnCh41NuI1Ga1mjN9nABYquuduml3LhowHe9ifXJN B5B1wczUQlpef7KA0fOmcHJsXGa0dYo5bXHvz7dGT3uuTfoD2XiySintPYYkXENclIhh MLEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=27s5gqZ8CpISwz9sEJ9KmbSXmWANFBZJ5F5PfijotM8=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=sHTbE56XOrrLBJo+FTQof3DHled48R2FDwfzZmohOJhGVhT+WXLvjeL0hgJcRAjn6O 1n8PEjgsaFZUZxu3FTtLK//l6SigO8C2dwB535+rxGHBW5Yc0RB9h+so2jwJGIJFN1yw XsyJSP4/S+J+A33tw81BqakKEN/4LaSMFfDTQVAec1/Bl2dPNM8kGKsdWSq04o8SIl/v IeIzuvapIFQn/9Nzqjlj1c+I+CJWpdzCHtnHxtJx2fjinoPbaHu+kZblKR4ld4O739Ct qsMKSM3nnCpVGELIo3qa88bpQvZGop7keFpAEYRSBCwddabOd0P1ETppN6TSwu2CYnBL cstg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=jmkLz3pe; spf=pass (google.com: domain of linux-kernel+bounces-7106-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7106-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id 22-20020a508e16000000b005538ad08b5dsi1738631edw.611.2023.12.20.07.01.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:01:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-7106-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=jmkLz3pe; spf=pass (google.com: domain of linux-kernel+bounces-7106-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7106-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 424731F24043 for ; Wed, 20 Dec 2023 15:01:00 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 53D9141236; Wed, 20 Dec 2023 14:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="jmkLz3pe" X-Original-To: linux-kernel@vger.kernel.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 301BE41741; Wed, 20 Dec 2023 14:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BKAKkOd026644; Wed, 20 Dec 2023 15:59:27 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=27s5gqZ8CpISwz9sEJ9KmbSXmWANFBZJ5F5PfijotM8=; b=jm kLz3peXIJp5C6TZiOexzA+OZKxXTWuRGD8rCxAQxXFjuptl+CrFh4AWQ+i0RvL5f LtLMEDhYcILupjq9+azz3zwCBpTM0NxT2GjIsw0FxWnfYj70X4OmLTSSU/AG/ouA QiMLglJGLQtINcCxhFQECmelzV4AKgRNsGZ5sm4+mGHP3MlFT1F5esfAxwYC8bCQ W8vdReyTzSRT+fo6BC2vDcC4pOnwQ0gQmIkdS5qZYzCQgHNWV1dtRf5dMgdj8O01 fRpv6Sc0PUIzXNRhMmaJrZ9c0X2F8FT5DwwUhXv5waS+CqCwHpVFzLa+19k5NUHr ni/7Mjhr6ObDm7DEpd+g== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v11w91wfe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:59:08 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0DDD3100059; Wed, 20 Dec 2023 15:59:08 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 00A9421B51D; Wed, 20 Dec 2023 15:59:08 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:59:07 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 05/10] counter: stm32-timer-cnt: add counter prescaler extension Date: Wed, 20 Dec 2023 15:57:21 +0100 Message-ID: <20231220145726.640627-6-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_08,2023-12-20_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785813497170806955 X-GMAIL-MSGID: 1785813497170806955 There's a prescaler in between the selected input signal used for counting (CK_PSC), and the counter input (CK_CNT). So add the "prescaler" extension to the counter. Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- Changes in v3: - New patch split from "counter: stm32-timer-cnt: introduce clock signal" --- drivers/counter/stm32-timer-cnt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 21a9c20c4281..bf2726dd7f12 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -220,11 +220,40 @@ static int stm32_count_enable_write(struct counter_device *counter, return 0; } +static int stm32_count_prescaler_read(struct counter_device *counter, + struct counter_count *count, u64 *prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + regmap_read(priv->regmap, TIM_PSC, &psc); + + *prescaler = psc + 1; + + return 0; +} + +static int stm32_count_prescaler_write(struct counter_device *counter, + struct counter_count *count, u64 prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + if (!prescaler || prescaler > MAX_TIM_PSC + 1) + return -ERANGE; + + psc = prescaler - 1; + + return regmap_write(priv->regmap, TIM_PSC, psc); +} + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), COUNTER_COMP_CEILING(stm32_count_ceiling_read, stm32_count_ceiling_write), + COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, + stm32_count_prescaler_write), }; static const enum counter_synapse_action stm32_clock_synapse_actions[] = { From patchwork Wed Dec 20 14:57:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181670 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2695029dyi; Wed, 20 Dec 2023 06:59:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IEUPRdlpnXf+4mwhlAzKmAyuEvZPsQvVU2ntYP4HzKukMWrbrprBCTapMJjO/CxK0Sq+A5s X-Received: by 2002:a2e:8855:0:b0:2cc:52a3:e7fb with SMTP id z21-20020a2e8855000000b002cc52a3e7fbmr4152118ljj.74.1703084378722; Wed, 20 Dec 2023 06:59:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084378; cv=none; d=google.com; s=arc-20160816; b=ikY2glHe70Z99hjeMESJaDjzvzky9aVniCgHggRWSoY3QEJohWrqvkd1mbPUT8dtEJ iZPuxd2BK94ZMDiOfk67+PlsQFPnXllDlGKo0DmaXBDG9mUxCBRWGjLEZRT2KF3VBrZ2 bBQH+7RntIU3vTrUD71SxIkqcL9cG4OjEb/5jphshcG1UyPH8szJAVkULx1AMP7rrO8m ncYVkw3Ioy7CjajEGk9qhoTnqFiMYiqmfsGDNFA7oPHYvfmkbo1jJsJoIzmyB0nC5gP1 BoEDQCMmJiShbW85gDciwvW2m1tAxqrC8MpSMV9XfpfBFooPwN0WBAzObb5J0BITxn9I XGFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=aGDnZpzUU9Vo6OuENOZWDVj2oc7Tl0EGM7EnZev4dXU=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=b7Chu8Ur4EAQBRPRZg1zR+DGSxli+LrbGUtdYcT8nuNq3sMt4iK38aivkIlQuNwFBA lNd2pot+fEeY8s0gPi+tA18HSArv8vqZJYRF25Ugiv8NOMuezPMbIP+Ld8IUIdT9IoDP hoZIZyhyyPvnhzswFZBi5l8ZSvecnFrGVarR2XuVmEUzcoAlIOHu7GgdmU0PGFqiL/ta S4zCTTLGSEhlCO7tqd02uc0IOZ47H7KWy3wXZe3oRMK9hYrXxErtAcmcDI0tr52utf5M vNvIgJtttrkpWXNCxrApe4kvnYVZauvGTh7fDUA4npYdvgmgWOZF1qvmk7SaezpyhhBn PFNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=4cemLYBa; spf=pass (google.com: domain of linux-kernel+bounces-7100-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7100-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Original driver was intended to be used only as quadrature encoder and simple counter on internal clock. So, add a check on encoder capability, so the driver may be probed for timer instances without encoder feature. This way, all timers may be used as simple counter on internal clock, starting from here. Encoder capability is retrieved by using the timer index (originally in stm32-timer-trigger driver and dt-bindings). The need to keep backward compatibility with existing device tree lead to parse aside trigger node. Signed-off-by: Fabrice Gasnier --- Changes in v3: - New patch split from: "counter: stm32-timer-cnt: populate capture channels and check encoder" - return -EOPNOTSUPP when encoder function isn't supported by the timer instance. --- drivers/counter/stm32-timer-cnt.c | 55 +++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index bf2726dd7f12..6933d42b16bf 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,8 @@ struct stm32_timer_cnt { u32 max_arr; bool enabled; struct stm32_timer_regs bak; + bool has_encoder; + u32 idx; }; static const enum counter_function stm32_count_functions[] = { @@ -111,12 +114,18 @@ static int stm32_count_function_write(struct counter_device *counter, sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; break; case COUNTER_FUNCTION_QUADRATURE_X2_A: + if (!priv->has_encoder) + return -EOPNOTSUPP; sms = TIM_SMCR_SMS_ENCODER_MODE_1; break; case COUNTER_FUNCTION_QUADRATURE_X2_B: + if (!priv->has_encoder) + return -EOPNOTSUPP; sms = TIM_SMCR_SMS_ENCODER_MODE_2; break; case COUNTER_FUNCTION_QUADRATURE_X4: + if (!priv->has_encoder) + return -EOPNOTSUPP; sms = TIM_SMCR_SMS_ENCODER_MODE_3; break; default: @@ -388,6 +397,48 @@ static struct counter_count stm32_counts = { .num_ext = ARRAY_SIZE(stm32_count_ext) }; +/* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */ +#define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7)) + +static const char * const stm32_timer_trigger_compat[] = { + "st,stm32-timer-trigger", + "st,stm32h7-timer-trigger", +}; + +static int stm32_timer_cnt_probe_encoder(struct platform_device *pdev, + struct stm32_timer_cnt *priv) +{ + struct device *parent = pdev->dev.parent; + struct device_node *tnode = NULL, *pnode = parent->of_node; + int i, ret; + + /* + * Need to retrieve the trigger node index from DT, to be able + * to determine if the counter supports encoder mode. It also + * enforce backward compatibility, and allow to support other + * counter modes in this driver (when the timer doesn't support + * encoder). + */ + for (i = 0; i < ARRAY_SIZE(stm32_timer_trigger_compat) && !tnode; i++) + tnode = of_get_compatible_child(pnode, stm32_timer_trigger_compat[i]); + if (!tnode) { + dev_err(&pdev->dev, "Can't find trigger node\n"); + return -ENODATA; + } + + ret = of_property_read_u32(tnode, "reg", &priv->idx); + if (ret) { + dev_err(&pdev->dev, "Can't get index (%d)\n", ret); + return ret; + } + + priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(priv->idx)); + + dev_dbg(&pdev->dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no"); + + return 0; +} + static int stm32_timer_cnt_probe(struct platform_device *pdev) { struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); @@ -409,6 +460,10 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) priv->clk = ddata->clk; priv->max_arr = ddata->max_arr; + ret = stm32_timer_cnt_probe_encoder(pdev, priv); + if (ret) + return ret; + counter->name = dev_name(dev); counter->parent = dev; counter->ops = &stm32_timer_cnt_ops; From patchwork Wed Dec 20 14:57:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181672 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2695420dyi; Wed, 20 Dec 2023 07:00:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IGv3Mrx5N1/D6A+QuZScobjyL8evzg0aCWQDd6N2B//EYZ8KA1GLwFv/bX9Do8qKyx9rIpr X-Received: by 2002:a17:906:73d7:b0:a26:8eb9:8a3d with SMTP id n23-20020a17090673d700b00a268eb98a3dmr714409ejl.5.1703084408433; Wed, 20 Dec 2023 07:00:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084408; cv=none; d=google.com; s=arc-20160816; b=RCqWP500Tt8dRjiBy1XiaqNqJGKGcMFkq8ndBzaOi9UJdDmHKDD3eHkcjoADh2btVI am/HBBKERtQ5jnpuBl5rjRoD4HSxuaImAtvE90F5ag+b6OsD/6Yf1oOFLgTO8dbBydOx y1re4aj2uOOLtYTI+5ndVx1I4UyBcG4bCu2gFelehOddfTG8wSIJ40zamzNiB/4WtV7G Q9XL1GLwxPkbERY0xm/BtC+2NK3diptZLiqUMfzPJ25miCdfSHIvZh+LiO3zPHoVrlC7 LONj1L8QdhL7BBbj7rM/b++apCe8L6M1LSq5ApVINiWouhgk01fejw9YLfuQ6+2Z0Wud 1maQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=IlOpFy1jN9ZOWAsrgsbza2MKAqlVofANmjpRVKJzMP8=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=EwocmZMWdsYWTtp3ofcl1N29IUnXrqkThP6mtEBKYGo+zBD88Bror/bTXzdvneGq/J 2rFN3PPzGHe6Zmkt2kuAuntvGpjWtaKC4QIRSPxZU+BvfmEh7CPfMHx/6fCDr82bTOvZ 7iHoI34g1+csmpBMIlh6Wk5LOSjfS6NnSPIR2DSNj5xfmhVYpjHxdF0vP64tOR6Dgdvr CGPYuiAGt8WatrSe/u3uJwxBbLAgVH/OPblbvX36o/OwDsI7R5e5myfHO/nQrl1Bmmgg dKcMfuAHbavGiP1BREeFadbgwaVJE48KooiuVDl5wcoqjsaZ3vOFClugY5EKBuNPFdp/ GyLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=WqoSYPmr; spf=pass (google.com: domain of linux-kernel+bounces-7102-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7102-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Statically add them, despite some timers doesn't have them. Rather rely on stm32_action_read that will report "none" action for these currently. Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- Changes in v3: - New patch split from: "counter: stm32-timer-cnt: populate capture channels and check encoder" --- drivers/counter/stm32-timer-cnt.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 6933d42b16bf..55eb6af34750 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -25,6 +25,8 @@ #define STM32_CH1_SIG 0 #define STM32_CH2_SIG 1 #define STM32_CLOCK_SIG 2 +#define STM32_CH3_SIG 3 +#define STM32_CH4_SIG 4 struct stm32_timer_regs { u32 cr1; @@ -366,6 +368,14 @@ static struct counter_signal stm32_signals[] = { .ext = stm32_count_clock_ext, .num_ext = ARRAY_SIZE(stm32_count_clock_ext), }, + { + .id = STM32_CH3_SIG, + .name = "Channel 3" + }, + { + .id = STM32_CH4_SIG, + .name = "Channel 4" + }, }; static struct counter_synapse stm32_count_synapses[] = { @@ -384,6 +394,16 @@ static struct counter_synapse stm32_count_synapses[] = { .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions), .signal = &stm32_signals[STM32_CLOCK_SIG] }, + { + .actions_list = stm32_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_synapse_actions), + .signal = &stm32_signals[STM32_CH3_SIG] + }, + { + .actions_list = stm32_synapse_actions, + .num_actions = ARRAY_SIZE(stm32_synapse_actions), + .signal = &stm32_signals[STM32_CH4_SIG] + }, }; static struct counter_count stm32_counts = { From patchwork Wed Dec 20 14:57:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181673 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2695838dyi; Wed, 20 Dec 2023 07:00:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IGmiWwx5IqiyAm7fzM9yTiAgc1quszMOdLFi5NWUeT+zPgUfnATFuaZYXSx2ODCsU9mDLMB X-Received: by 2002:a17:902:d550:b0:1d3:ef33:d0ae with SMTP id z16-20020a170902d55000b001d3ef33d0aemr805522plf.114.1703084433034; Wed, 20 Dec 2023 07:00:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084433; cv=none; d=google.com; s=arc-20160816; b=WNbmJDhLUHIb6aqkvlF+vpp7ZT+J0vfFFhrbK4+l7nl4LdG+A0ht2iiclX4+sU9uvY JPc2UqODnxgjoUon4TE3P702llRI2Rg2eodHsm1i2XjDKoYo/3YAm339imNgAUoG0j9g rap3bdbGm7tZjwWvsGVSaUBKyWjtSpJ+U0GlL/c+pI95tPHKUuinzf4pGA8Dlzw6qtwY N2MzbVKayH930riPnZSow5/uSj79CDUG+kDMuu86rKOygpvoGkKbeqlGP5jmfTZGIWpr MGX1mjJv/TLXI0dmdtC97Kd8PF/0pHe2mHOa+UP0YslL3ic6lg9sn1LsJl27dL/yZwgs AywQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=xp/c+t2tNZhdwFtDsDw7WOFKDiPnT7aLbJzsg/uPGbU=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=JG3C485hAsRb4rGej4NqGaof2OMTVutGh05yCxthepOw7ZBw9Bhu9XTc7AuOxJuHsJ 2uu6hPYVmKDmf2q8QXTHZXUT1VK9x2sRKcgfp7vT07LxVmK5VqE6XFaMuopCjfTXnHRo t3yLeaFtaJhZTOW0o1xzH1LIxzIO/81NPWVdIbzJsSRogpvS45svOanultrZ9fm4W9K2 6y67Gvu+Yr7SSjxsHKtB80jCYwMEmkpknKG8+dBruGHO8GJ6D8Kc1CGA335/+uFhnxGV Dnm19wF9sVHkD2TLBPFBf2RXtzMO7/ZsdDwGgZbT36MlnuTm2EDneeNJNOnbksfx6UJR LcSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=ow37LzVW; spf=pass (google.com: domain of linux-kernel+bounces-7101-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7101-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id jf14-20020a170903268e00b001d3e44faf1bsi2476998plb.242.2023.12.20.07.00.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:00:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-7101-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=ow37LzVW; spf=pass (google.com: domain of linux-kernel+bounces-7101-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7101-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 57349288888 for ; Wed, 20 Dec 2023 15:00:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6209F40BE5; Wed, 20 Dec 2023 14:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="ow37LzVW" X-Original-To: linux-kernel@vger.kernel.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F9413E466; Wed, 20 Dec 2023 14:59:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BKAQ6fK020548; Wed, 20 Dec 2023 15:59:12 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=xp/c+t2tNZhdwFtDsDw7WOFKDiPnT7aLbJzsg/uPGbU=; b=ow 37LzVWvaya8fQSmAHh7y02MQed+lC2CFI1uTwI/U68pNoCr7Zm0vdlvWzlokKF6n V7ujIqtCFKdDHMMHux+lXMaU/PR7eZa63qgpfiYyyWdP90Czlqm9AfGipIXK9qRJ t/gg4nDLRSn3q1pio+WKI8Nr2SsHWgf97X34YtDbccG/qn//X7pctkk5X1Uxdohy MjVRwj6KW+FC1QJshx1u4p97a4ajVEVr0nI3zausHHhPbWmef8tP57WeCjLh1MQf sm2rcg0u9NqzK2wZEaO+ggbIv6d3hINwuZdb2cjqaCkXLCre6GN14b453nIWNEc8 2YgBziwRiUoDjUKHbiMA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v144225p9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:59:12 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 20886100057; Wed, 20 Dec 2023 15:59:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 153DC21B51F; Wed, 20 Dec 2023 15:59:11 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:59:10 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 08/10] counter: stm32-timer-cnt: probe number of channels from registers Date: Wed, 20 Dec 2023 15:57:24 +0100 Message-ID: <20231220145726.640627-9-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_09,2023-12-20_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785813462708622926 X-GMAIL-MSGID: 1785813462708622926 Probe the number of capture compare channels, by writing CCER register bits and read them back. Take care to restore the register original value. This is a precursor patch to support capture channels. Signed-off-by: Fabrice Gasnier --- Changes in v3: - New patch split from: "counter: stm32-timer-cnt: populate capture channels and check encoder" --- drivers/counter/stm32-timer-cnt.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 55eb6af34750..b5dc4378fecf 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -43,6 +43,7 @@ struct stm32_timer_cnt { struct stm32_timer_regs bak; bool has_encoder; u32 idx; + unsigned int nchannels; }; static const enum counter_function stm32_count_functions[] = { @@ -417,6 +418,20 @@ static struct counter_count stm32_counts = { .num_ext = ARRAY_SIZE(stm32_count_ext) }; +static void stm32_timer_cnt_detect_channels(struct platform_device *pdev, + struct stm32_timer_cnt *priv) +{ + u32 ccer, ccer_backup; + + regmap_read(priv->regmap, TIM_CCER, &ccer_backup); + regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); + regmap_read(priv->regmap, TIM_CCER, &ccer); + regmap_write(priv->regmap, TIM_CCER, ccer_backup); + priv->nchannels = hweight32(ccer & TIM_CCER_CCXE); + + dev_dbg(&pdev->dev, "has %d cc channels\n", priv->nchannels); +} + /* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */ #define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7)) @@ -484,6 +499,8 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) if (ret) return ret; + stm32_timer_cnt_detect_channels(pdev, priv); + counter->name = dev_name(dev); counter->parent = dev; counter->ops = &stm32_timer_cnt_ops; From patchwork Wed Dec 20 14:57:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 181674 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2696058dyi; Wed, 20 Dec 2023 07:00:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkbjuffFVjgxzQtb9JN3uTpd9wVqPJRI4e/rNhYBOFvbINrQZQKjP+gsdAXKuVmD17LYl4 X-Received: by 2002:a17:902:da90:b0:1d3:adef:a49d with SMTP id j16-20020a170902da9000b001d3adefa49dmr4253644plx.117.1703084447593; Wed, 20 Dec 2023 07:00:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703084447; cv=none; d=google.com; s=arc-20160816; b=pu3GgaEwTezIsmqARemn6BsMMP+hg4UWKeBjsERGjnbLB3OpkCLoHE/Z6R5oX4rpob jTDf9yS77Hhq3Ak8nDlp8BdmdwE1/sJpIGuM6V1NQYO6Udod+puSnolDQNEU3OWaKuJU eW8AqPQx9WsauyA3bCfRVZmbqYtAiyOkYedNnvnRbfk/thWSOJVj7QIRmo9m4CxluXvx rfFQlfaOzf/plafs7cMEN3aLLs25HM0NMC3HkI8YTDo46q7A/Q28vbl2Xtr51aNbECca spHMwRQu9c1Lybhxc7LbmfUA+Ip/xQjQilQR8gqAVRnVuPkEEoVUvdlFDakxiaLdxI/9 APfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=x6nQQ71xtku6SiZZzFF5O30s9wsVUqCHS/O30UoRmzg=; fh=ozwKRq0p8tj2zy4oAJzh3eawPsCHg5fP2FoTNn7f1y4=; b=LoLkqKCmuJbpqHxpwtAeCjh87urOT0itPE2UyV8kAC9dyp64q21RfML41bOT3UGhMi cr6+X366m/h4OP9r6GVdad/ReABo8Z1p6MAi5UH0TPcoIpMZI3xJyFgtbRJoa/kxFJUp ErRDISoD9wlnpDjcpc14S/XKqR7m2oJpaddqE/dYoFNHmn8PK0Yv5U0FrshfaBE4VwPG jZDglS9CgzYVPSh9WumokeesVtHkz/guqWyUVv/1mwrFxULMdTZ/mVWB6M0FoIKIB38S v65nQx/EsftRHGPj7ewgIruXmBExopXSbuHMzIckqP7Fd8lBVmkUjGbOR91Pn8vClyj8 F5vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=f73ksnNa; spf=pass (google.com: domain of linux-kernel+bounces-7103-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-7103-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Also add the related validation and configuration routine. Register and enable interrupts to push events. STM32 Timers can have either 1 global interrupt, or 4 dedicated interrupt lines. Request only the necessary interrupt, e.g. either global interrupt that can report all event types, or update interrupt only for overflow event. Acked-by: Lee Jones Signed-off-by: Fabrice Gasnier --- Changes in v3: - patch split from: "counter: stm32-timer-cnt: add support for events", to focus on the overflow events only here. Move the capture event support to a separate patch. - simplify the patch, by removing diversity introduced by the number of possible channels. All channels are now exposed instead. Report an error when trying to access a channel that doesn't exist. Changes in v2: - fix warnings (kernel test robot) - fix a typo - add collected ack from Lee --- drivers/counter/stm32-timer-cnt.c | 132 +++++++++++++++++++++++++++++- include/linux/mfd/stm32-timers.h | 13 +++ 2 files changed, 144 insertions(+), 1 deletion(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index b5dc4378fecf..d13e4c427965 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -8,6 +8,7 @@ * */ #include +#include #include #include #include @@ -44,6 +45,9 @@ struct stm32_timer_cnt { bool has_encoder; u32 idx; unsigned int nchannels; + unsigned int nr_irqs; + u32 *irq; + atomic_t nb_ovf; }; static const enum counter_function stm32_count_functions[] = { @@ -259,6 +263,29 @@ static int stm32_count_prescaler_write(struct counter_device *counter, return regmap_write(priv->regmap, TIM_PSC, psc); } +static int stm32_count_nb_ovf_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + + *val = atomic_read(&priv->nb_ovf); + + return 0; +} + +static int stm32_count_nb_ovf_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + + if (val != (typeof(priv->nb_ovf.counter))val) + return -ERANGE; + + atomic_set(&priv->nb_ovf, val); + + return 0; +} + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), @@ -266,6 +293,7 @@ static struct counter_comp stm32_count_ext[] = { stm32_count_ceiling_write), COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, stm32_count_prescaler_write), + COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write), }; static const enum counter_synapse_action stm32_clock_synapse_actions[] = { @@ -323,12 +351,57 @@ static int stm32_action_read(struct counter_device *counter, } } +static int stm32_count_events_configure(struct counter_device *counter) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + struct counter_event_node *event_node; + u32 val, dier = 0; + + list_for_each_entry(event_node, &counter->events_list, l) { + switch (event_node->event) { + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: + /* first clear possibly latched UIF before enabling */ + regmap_read(priv->regmap, TIM_DIER, &val); + if (!(val & TIM_DIER_UIE)) + regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); + dier |= TIM_DIER_UIE; + break; + default: + /* should never reach this path */ + return -EINVAL; + } + } + + regmap_write(priv->regmap, TIM_DIER, dier); + + return 0; +} + +static int stm32_count_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + + /* Interrupts are optional */ + if (!priv->nr_irqs) + return -EOPNOTSUPP; + + switch (watch->event) { + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: + return 0; + default: + return -EINVAL; + } +} + static const struct counter_ops stm32_timer_cnt_ops = { .count_read = stm32_count_read, .count_write = stm32_count_write, .function_read = stm32_count_function_read, .function_write = stm32_count_function_write, .action_read = stm32_action_read, + .events_configure = stm32_count_events_configure, + .watch_validate = stm32_count_watch_validate, }; static int stm32_count_clk_get_freq(struct counter_device *counter, @@ -418,6 +491,35 @@ static struct counter_count stm32_counts = { .num_ext = ARRAY_SIZE(stm32_count_ext) }; +static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) +{ + struct counter_device *counter = ptr; + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ + u32 sr, dier; + + regmap_read(priv->regmap, TIM_SR, &sr); + regmap_read(priv->regmap, TIM_DIER, &dier); + /* + * Some status bits in SR don't match with the enable bits in DIER. Only take care of + * the possibly enabled bits in DIER (that matches in between SR and DIER). + */ + dier &= TIM_DIER_UIE; + sr &= dier; + + if (sr & TIM_SR_UIF) { + atomic_inc(&priv->nb_ovf); + counter_push_event(counter, COUNTER_EVENT_OVERFLOW_UNDERFLOW, 0); + dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n"); + /* SR flags can be cleared by writing 0, only clear relevant flag */ + clr &= ~TIM_SR_UIF; + } + + regmap_write(priv->regmap, TIM_SR, clr); + + return IRQ_HANDLED; +}; + static void stm32_timer_cnt_detect_channels(struct platform_device *pdev, struct stm32_timer_cnt *priv) { @@ -480,7 +582,7 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct stm32_timer_cnt *priv; struct counter_device *counter; - int ret; + int i, ret; if (IS_ERR_OR_NULL(ddata)) return -EINVAL; @@ -494,6 +596,8 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) priv->regmap = ddata->regmap; priv->clk = ddata->clk; priv->max_arr = ddata->max_arr; + priv->nr_irqs = ddata->nr_irqs; + priv->irq = ddata->irq; ret = stm32_timer_cnt_probe_encoder(pdev, priv); if (ret) @@ -511,6 +615,32 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); + /* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */ + if (priv->nr_irqs == 1) { + /* All events reported through the global interrupt */ + ret = devm_request_irq(&pdev->dev, priv->irq[0], stm32_timer_cnt_isr, + 0, dev_name(dev), counter); + if (ret) { + dev_err(dev, "Failed to request irq %d (err %d)\n", + priv->irq[i], ret); + return ret; + } + } else { + for (i = 0; i < priv->nr_irqs; i++) { + /* Only take care of update IRQ for overflow events */ + if (i != STM32_TIMERS_IRQ_UP) + continue; + + ret = devm_request_irq(&pdev->dev, priv->irq[i], stm32_timer_cnt_isr, + 0, dev_name(dev), counter); + if (ret) { + dev_err(dev, "Failed to request irq %d (err %d)\n", + priv->irq[i], ret); + return ret; + } + } + } + /* Reset input selector to its default input */ regmap_write(priv->regmap, TIM_TISEL, 0x0); diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index ca35af30745f..9eb17481b07f 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -41,6 +41,11 @@ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ #define TIM_DIER_UIE BIT(0) /* Update interrupt */ +#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ +#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ +#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ +#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ +#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ #define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ #define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ @@ -49,6 +54,7 @@ #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ +#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ #define TIM_EGR_UG BIT(0) /* Update Generation */ #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ @@ -60,16 +66,23 @@ #define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ #define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ #define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ +#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ +#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ +#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ +#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ +#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ +#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ +#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) #define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ #define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ From patchwork Wed Dec 20 14:57:26 2023 Content-Type: text/plain; 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Captured counter value for each channel can be retrieved through CCRx register. STM32 timers can have up to 4 capture channels (on input channel 1 to channel 4), hence need to check the number of channels before reading the capture data. The capture configuration is hard-coded to capture signals on both edges (non-inverted). Interrupts are used to report events independently for each channel. Signed-off-by: Fabrice Gasnier --- Changes in v3: - patch split from: "counter: stm32-timer-cnt: add support for events", to focus on the capture events only here. - only get relevant interrupt line --- drivers/counter/stm32-timer-cnt.c | 134 +++++++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 3 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index d13e4c427965..0b131ca71de6 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -263,6 +263,40 @@ static int stm32_count_prescaler_write(struct counter_device *counter, return regmap_write(priv->regmap, TIM_PSC, psc); } +static int stm32_count_cap_read(struct counter_device *counter, + struct counter_count *count, + size_t ch, u64 *cap) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 ccrx; + + if (ch >= priv->nchannels) + return -EOPNOTSUPP; + + switch (ch) { + case 0: + regmap_read(priv->regmap, TIM_CCR1, &ccrx); + break; + case 1: + regmap_read(priv->regmap, TIM_CCR2, &ccrx); + break; + case 2: + regmap_read(priv->regmap, TIM_CCR3, &ccrx); + break; + case 3: + regmap_read(priv->regmap, TIM_CCR4, &ccrx); + break; + default: + return -EINVAL; + } + + dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx); + + *cap = ccrx; + + return 0; +} + static int stm32_count_nb_ovf_read(struct counter_device *counter, struct counter_count *count, u64 *val) { @@ -286,6 +320,8 @@ static int stm32_count_nb_ovf_write(struct counter_device *counter, return 0; } +static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4); + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), @@ -293,6 +329,7 @@ static struct counter_comp stm32_count_ext[] = { stm32_count_ceiling_write), COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, stm32_count_prescaler_write), + COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array), COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write), }; @@ -351,11 +388,68 @@ static int stm32_action_read(struct counter_device *counter, } } +struct stm32_count_cc_regs { + u32 ccmr_reg; + u32 ccmr_mask; + u32 ccmr_bits; + u32 ccer_bits; +}; + +static const struct stm32_count_cc_regs stm32_cc[] = { + { TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1, + TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP }, + { TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2, + TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP }, + { TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3, + TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP }, + { TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4, + TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP }, +}; + +static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch, + bool enable) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 ccmr, ccer, sr; + + if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) { + dev_err(counter->parent, "invalid ch: %d\n", ch); + return -EINVAL; + } + + /* + * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2... + * Select both edges / non-inverted to trigger a capture. + */ + if (enable) { + /* first clear possibly latched capture flag upon enabling */ + regmap_read(priv->regmap, TIM_CCER, &ccer); + if (!(ccer & stm32_cc[ch].ccer_bits)) { + sr = ~TIM_SR_CC_IF(ch); + regmap_write(priv->regmap, TIM_SR, sr); + } + regmap_update_bits(priv->regmap, stm32_cc[ch].ccmr_reg, stm32_cc[ch].ccmr_mask, + stm32_cc[ch].ccmr_bits); + regmap_set_bits(priv->regmap, TIM_CCER, stm32_cc[ch].ccer_bits); + } else { + regmap_clear_bits(priv->regmap, TIM_CCER, stm32_cc[ch].ccer_bits); + regmap_clear_bits(priv->regmap, stm32_cc[ch].ccmr_reg, stm32_cc[ch].ccmr_mask); + } + + regmap_read(priv->regmap, stm32_cc[ch].ccmr_reg, &ccmr); + regmap_read(priv->regmap, TIM_CCER, &ccer); + dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis", + ch, ccmr, ccer); + + return 0; +} + static int stm32_count_events_configure(struct counter_device *counter) { struct stm32_timer_cnt *const priv = counter_priv(counter); struct counter_event_node *event_node; u32 val, dier = 0; + int i, ret; list_for_each_entry(event_node, &counter->events_list, l) { switch (event_node->event) { @@ -366,6 +460,12 @@ static int stm32_count_events_configure(struct counter_device *counter) regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); dier |= TIM_DIER_UIE; break; + case COUNTER_EVENT_CAPTURE: + ret = stm32_count_capture_configure(counter, event_node->channel, true); + if (ret) + return ret; + dier |= TIM_DIER_CC_IE(event_node->channel); + break; default: /* should never reach this path */ return -EINVAL; @@ -374,6 +474,15 @@ static int stm32_count_events_configure(struct counter_device *counter) regmap_write(priv->regmap, TIM_DIER, dier); + /* check for disabled capture events */ + for (i = 0 ; i < priv->nchannels; i++) { + if (!(dier & TIM_DIER_CC_IE(i))) { + ret = stm32_count_capture_configure(counter, i, false); + if (ret) + return ret; + } + } + return 0; } @@ -387,6 +496,12 @@ static int stm32_count_watch_validate(struct counter_device *counter, return -EOPNOTSUPP; switch (watch->event) { + case COUNTER_EVENT_CAPTURE: + if (watch->channel >= priv->nchannels) { + dev_err(counter->parent, "Invalid channel %d\n", watch->channel); + return -EINVAL; + } + return 0; case COUNTER_EVENT_OVERFLOW_UNDERFLOW: return 0; default: @@ -497,6 +612,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) struct stm32_timer_cnt *const priv = counter_priv(counter); u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ u32 sr, dier; + int i; regmap_read(priv->regmap, TIM_SR, &sr); regmap_read(priv->regmap, TIM_DIER, &dier); @@ -504,7 +620,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) * Some status bits in SR don't match with the enable bits in DIER. Only take care of * the possibly enabled bits in DIER (that matches in between SR and DIER). */ - dier &= TIM_DIER_UIE; + dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE); sr &= dier; if (sr & TIM_SR_UIF) { @@ -515,6 +631,15 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) clr &= ~TIM_SR_UIF; } + /* Check capture events */ + for (i = 0 ; i < priv->nchannels; i++) { + if (sr & TIM_SR_CC_IF(i)) { + counter_push_event(counter, COUNTER_EVENT_CAPTURE, i); + clr &= ~TIM_SR_CC_IF(i); + dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i); + } + } + regmap_write(priv->regmap, TIM_SR, clr); return IRQ_HANDLED; @@ -627,8 +752,11 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) } } else { for (i = 0; i < priv->nr_irqs; i++) { - /* Only take care of update IRQ for overflow events */ - if (i != STM32_TIMERS_IRQ_UP) + /* + * Only take care of update IRQ for overflow events, and cc for + * capture events. + */ + if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC) continue; ret = devm_request_irq(&pdev->dev, priv->irq[i], stm32_timer_cnt_isr,