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Signed-off-by: Hugues Fruchet --- .../media/st,stm32mp25-video-codec.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml new file mode 100644 index 000000000000..e167e3b1bec3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder + +maintainers: + - Hugues Fruchet + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware + decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1) + and a VENC video hardware encoder peripheral based on Verisilicon + VC8000NanoE IP (former Hantro H1). + +properties: + compatible: + enum: + - st,stm32mp25-vdec + - st,stm32mp25-venc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + video-codec@580d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x580d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + }; From patchwork Wed Dec 20 08:46:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 181537 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2501254dyi; Wed, 20 Dec 2023 00:47:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IHq2Uqr9rz5USKPpXd+/jSkjwEaHqNTPKaLuodLBW60yoZEVXAnynAknSphfB3lVgHuutGn X-Received: by 2002:a05:6808:1390:b0:3ae:4cab:526a with SMTP id c16-20020a056808139000b003ae4cab526amr24775856oiw.14.1703062070696; Wed, 20 Dec 2023 00:47:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703062070; cv=none; d=google.com; s=arc-20160816; b=vRqmoSeoC7XSFvbDZhZLc4YWm9WYAAy1sGa/DBBwCPb2a0T4SUmr8SUubjhdI7Avq0 VXnX4gb5pXLAC0PjgJIGpl41WAXUtfYQ4wK6Bw7dKk7oDnYOVbf0v6fCTldp1msC6vj3 CRauCKiGsfwGzhcr10HsOPLfMdnSt0BoESN6nBoIeesH5jxks42/mdkrydT/HZuCJHWS LGCV3qCRUsnG2aDRi3aWTogF8GwKSgGEQgLI4dTdSbTQkX7MwfPCF3gv3xSkGP7ASnV1 IgBkOBVr20AEml+hFxEgpJhVHxO/o6XTAYYJhUiL4Q1seC/LTkDBXqe7lV/jhvyDIrwZ X/Xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=SPIv/qYa1AJu68CwZt0kU95Lm7bAcMmh1OuglSPLCyI=; fh=ErwLDw9+98Mb4Q3i5RoHr7UOS7Ns3CK5YbB+qheGbUs=; b=ULJgo2D1orWBCYXRedAWOPQwqEpgILBmq2qMSgtoCeIl/x7LIOiuxcpYG1AYXqDk/F HE2Ff8pDN5ZecTnjw3ievxUjgxkIl399lmNf2fZ1VySd3hJ8rBbRF0BKaJk9/xrTo9Oj TFLVk1AJsAuf3lrhKqroBbyN+JAtC+f1HRDQA2Tm51M1ifKPG/netYGdWyd3dirZhU4U Lpur5QVmcbrge78PoEzTUJBZ3asZiNZ2FATZJ7WuxMAD87pcYJXtI7gG5NJLH44hNxHk OdNaewj9cgOb/KfQG8bA+1s2Qud0TQ6PcdyPB2yyatANLx0XCAreqjcufCENFAO9b+v3 3j4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=4Pw3q5FJ; spf=pass (google.com: domain of linux-kernel+bounces-6595-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6595-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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H264/VP8 decoding up to 4080x4080. No post-processor support. VDEC has its own reset/clock/irq. Signed-off-by: Hugues Fruchet Reviewed-by: Nicolas Dufresne --- drivers/media/platform/verisilicon/Kconfig | 14 ++- drivers/media/platform/verisilicon/Makefile | 3 + .../media/platform/verisilicon/hantro_drv.c | 3 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_vdec_hw.c | 92 +++++++++++++++++++ 5 files changed, 110 insertions(+), 3 deletions(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c diff --git a/drivers/media/platform/verisilicon/Kconfig b/drivers/media/platform/verisilicon/Kconfig index e65b836b9d78..7642ff9cf96c 100644 --- a/drivers/media/platform/verisilicon/Kconfig +++ b/drivers/media/platform/verisilicon/Kconfig @@ -4,7 +4,7 @@ comment "Verisilicon media platform drivers" config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || ARCH_STM32 || COMPILE_TEST depends on V4L_MEM2MEM_DRIVERS depends on VIDEO_DEV select MEDIA_CONTROLLER @@ -16,8 +16,8 @@ config VIDEO_HANTRO select V4L2_VP9 help Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image - encoding and decoding. + Rockchip, NXP i.MX8M and STM32MP25 SoCs, which accelerate video + and image encoding and decoding. To compile this driver as a module, choose M here: the module will be called hantro-vpu. @@ -52,3 +52,11 @@ config VIDEO_HANTRO_SUNXI default y help Enable support for H6 SoC. + +config VIDEO_HANTRO_STM32MP25 + bool "Hantro STM32MP25 support" + depends on VIDEO_HANTRO + depends on ARCH_STM32 || COMPILE_TEST + default y + help + Enable support for STM32MP25 SoCs. diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/platform/verisilicon/Makefile index 6ad2ef885920..5854e0f0dd32 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -39,3 +39,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ sunxi_vpu_hw.o + +hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \ + stm32mp25_vdec_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index a9fa05ac56a9..2db27c333924 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -733,6 +733,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_SUNXI { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_STM32MP25 + { .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index 7f33f7b07ce4..b7eccc1a96fc 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -406,6 +406,7 @@ extern const struct hantro_variant rk3568_vpu_variant; extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; +extern const struct hantro_variant stm32mp25_vdec_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c b/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c new file mode 100644 index 000000000000..aa8b0f751390 --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 VDEC video decoder driver + * + * Copyright (C) STMicroelectronics SA 2022 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include "hantro.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_vdec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_VP8_FRAME, + .codec_mode = HANTRO_MODE_VP8_DEC, + .max_depth = 2, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = FMT_MIN_WIDTH, + .max_width = FMT_FHD_WIDTH, + .step_width = MB_DIM, + .min_height = FMT_MIN_HEIGHT, + .max_height = FMT_FHD_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] = { + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .reset = hantro_g1_reset, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .reset = hantro_g1_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + +static const struct hantro_irq stm32mp25_irqs[] = { + { "vdec", hantro_g1_irq }, +}; + +static const char * const stm32mp25_clk_names[] = { "vdec-clk" }; + +const struct hantro_variant stm32mp25_vdec_variant = { + .dec_fmts = stm32mp25_vdec_fmts, + .num_dec_fmts = ARRAY_SIZE(stm32mp25_vdec_fmts), + .codec = HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops = stm32mp25_vdec_codec_ops, + .irqs = stm32mp25_irqs, + .num_irqs = ARRAY_SIZE(stm32mp25_irqs), + .clk_names = stm32mp25_clk_names, + .num_clocks = ARRAY_SIZE(stm32mp25_clk_names), +}; From patchwork Wed Dec 20 08:46:39 2023 Content-Type: text/plain; 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JPEG encoding up to 8176x8176. VENC has its own reset/clock/irq. Signed-off-by: Hugues Fruchet --- drivers/media/platform/verisilicon/Makefile | 3 +- .../media/platform/verisilicon/hantro_drv.c | 1 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_venc_hw.c | 147 ++++++++++++++++++ 4 files changed, 151 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_venc_hw.c diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/platform/verisilicon/Makefile index 5854e0f0dd32..3bf43fdbedc1 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -41,4 +41,5 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ sunxi_vpu_hw.o hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \ - stm32mp25_vdec_hw.o + stm32mp25_vdec_hw.o \ + stm32mp25_venc_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 2db27c333924..4d97a8ac03de 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -736,6 +736,7 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_STM32MP25 { .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, }, + { .compatible = "st,stm32mp25-venc", .data = &stm32mp25_venc_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index b7eccc1a96fc..70c72e9d11d5 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -407,6 +407,7 @@ extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_variant stm32mp25_vdec_variant; +extern const struct hantro_variant stm32mp25_venc_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c new file mode 100644 index 000000000000..9d220ff5f1a9 --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 VENC video encoder driver + * + * Copyright (C) STMicroelectronics SA 2022 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include +#include +#include + +#include "hantro.h" +#include "hantro_jpeg.h" +#include "hantro_h1_regs.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_venc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P, + .frmsize = { + .min_width = 96, + .max_width = FMT_4K_WIDTH, + .step_width = MB_DIM, + .min_height = 96, + .max_height = FMT_4K_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP, + .frmsize = { + .min_width = 96, + .max_width = FMT_4K_WIDTH, + .step_width = MB_DIM, + .min_height = 96, + .max_height = FMT_4K_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422, + .frmsize = { + .min_width = 96, + .max_width = FMT_4K_WIDTH, + .step_width = MB_DIM, + .min_height = 96, + .max_height = FMT_4K_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422, + .frmsize = { + .min_width = 96, + .max_width = FMT_4K_WIDTH, + .step_width = MB_DIM, + .min_height = 96, + .max_height = FMT_4K_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_JPEG, + .codec_mode = HANTRO_MODE_JPEG_ENC, + .max_depth = 2, + .header_size = JPEG_HEADER_SIZE, + .frmsize = { + .min_width = 96, + .max_width = FMT_4K_WIDTH, + .step_width = MB_DIM, + .min_height = 96, + .max_height = FMT_4K_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + +static irqreturn_t stm32mp25_venc_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vepu_read(vpu, H1_REG_INTERRUPT); + state = (status & H1_REG_INTERRUPT_FRAME_RDY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +static void stm32mp25_venc_reset(struct hantro_ctx *ctx) +{ +} + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_venc_codec_ops[] = { + [HANTRO_MODE_JPEG_ENC] = { + .run = hantro_h1_jpeg_enc_run, + .reset = stm32mp25_venc_reset, + .done = hantro_h1_jpeg_enc_done, + }, +}; + +/* + * Variants. + */ + +static const struct hantro_irq stm32mp25_venc_irqs[] = { + { "venc", stm32mp25_venc_irq }, +}; + +static const char * const stm32mp25_venc_clk_names[] = { + "venc-clk" +}; + +const struct hantro_variant stm32mp25_venc_variant = { + .enc_fmts = stm32mp25_venc_fmts, + .num_enc_fmts = ARRAY_SIZE(stm32mp25_venc_fmts), + .codec = HANTRO_JPEG_ENCODER, + .codec_ops = stm32mp25_venc_codec_ops, + .irqs = stm32mp25_venc_irqs, + .num_irqs = ARRAY_SIZE(stm32mp25_venc_irqs), + .clk_names = stm32mp25_venc_clk_names, + .num_clocks = ARRAY_SIZE(stm32mp25_venc_clk_names) +}; + From patchwork Wed Dec 20 08:46:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 181538 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2501569dyi; Wed, 20 Dec 2023 00:48:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IGO8KvYG3AB0nRx3qtb4VAjr88xqdXJAFJSnT2sxkSFaOwOKRKrHMGmwTM42mapNlWAeUd8 X-Received: by 2002:a05:622a:490:b0:425:4043:763a with SMTP id p16-20020a05622a049000b004254043763amr26958945qtx.98.1703062131370; Wed, 20 Dec 2023 00:48:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703062131; cv=none; d=google.com; s=arc-20160816; b=wOm5NmHctKNIxD/i124XhHS2nJ3cZaTRDn6Opgg6zBLmvAR1SUnmDrf+BOL6MzqUVb LI8+iUtA1EcR2vUMsjjBbHw2Cw5/i4NRQ3s/CQ9m+kXaJaFUItKBZQ6DR1eOk+FdKN3t LkwkC8B/ussBoCHRkpR01YJzNwY9FZ7SAZNdFS4qcvd3upR5hTgC23KoYlnLZGGgiN3D sz7Wnkk89plZtxkCzO1L/Fvitlikx4aqqrGtOrqCd6lsvAWD74tkSiUEcVKW0cFAvIzc qHicCuyw7x/FHJe8wMXNWHBsqUZNul5KvDzGVtRRaPAMwxKFWEWxB1fzIclxXHAUAtKO AyHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=iSjyXXBlLU8CmpUXVSZCKnI2Y7L6CFxxoTsOMTlPK98=; fh=ErwLDw9+98Mb4Q3i5RoHr7UOS7Ns3CK5YbB+qheGbUs=; b=X9LGAY27xpx1JqeoglsfMbUhxtjjw3HthOQBp9+WDKbl9TLQDD/YAPcqEgu3fiJtY6 lL3LMLHtZpgicUR/+5EGivoXjL2YtkhE4DYf3AzuvMEmAcnWluhOK/mtfkLo7wMcJIuE /wgnHlUFqPANpsG9TTveNzA+RTIDZLIW7TC0/J2nqQfaSMSs28e8U70HYXo3FqxA1P2B m7ijWvCZjkigdNfum5YPSbFMDtYkAeRtc8M92L3L+2gHMO34WIIJsaDLvDQ5rXcRp5TX xVxRSVQ1Q/aDStmauSOcEXomrlj4xC1IgEC4Up0rrnKx/aI/nZozTSBzWSMo+fPubk/J 6srg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=5J8MzLQa; spf=pass (google.com: domain of linux-kernel+bounces-6597-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6597-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 96859d098ef8..8fc7e9199499 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ ck_icn_ls_mcu: ck-icn-ls-mcu { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index e6fa596211f5..aea5096dac3c 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,4 +6,14 @@ #include "stm32mp253.dtsi" / { + soc@0 { + rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + }; + }; + }; }; From patchwork Wed Dec 20 08:46:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 181544 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2502293dyi; Wed, 20 Dec 2023 00:51:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IFALpMQhlBbeDwWILDd1nxiS42XVr/HKrIALltyeLVLR9XxUammI2tOMxkIbusVAYXUzaLb X-Received: by 2002:a17:903:244a:b0:1d0:ad0e:bef4 with SMTP id l10-20020a170903244a00b001d0ad0ebef4mr3638578pls.63.1703062265011; Wed, 20 Dec 2023 00:51:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703062264; cv=none; d=google.com; s=arc-20160816; b=kPhqfMvBqqJkm33Qn78Q2aC1p0hJcJGOGSwos9jw0hVxdNSEPoik4P84ZVJ+co6e52 DBMz4+NSp2OcLuDnuS5ulMZdUJhOc9i81zQFDudpJ/TbHjmXJOkCNRdezCe19+RkiVTJ AiDrqIEHKNxQUyMzFnWxQRznN74/1CokRd0U8XVjLRQgNO9WP5NJBn/u7FQt04jkUrHV c7Au5iFg5n0n3nZnmacBGEl+vxk7Bs+kB5akF/P2hB9GkZvZTKWMq40fZgWryKw05FuP T5UK24VFtB0FREdLcNmaEKFWAGhSbd5vrGEgdg8Y72NUpqQw9nDCVBHGO+U8WkG0dqj4 +Ulg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gOTJOkgkUXjyDgxkghIjHED6KsoYJ6xYXo9usGGB+Xk=; fh=ErwLDw9+98Mb4Q3i5RoHr7UOS7Ns3CK5YbB+qheGbUs=; b=e3hWRdUk+/OiUyZ9G26YXowAdMhJoLgeI+uHWzkUqporuw9KIDL7t4MNFDIft5oRsK kzd9k/nxybuPrWLQM9hijA1kmMppfrgiZn5d65OTspzayeNwMYHebmvxmxA1u+J7/f9t VL48/pg5aMJZI3LkXUE+UCcVx4lkFjQLW1YJaG+CYxghIW+Wc5DRxbCUmdJikP6E71YA /i74Fmci3ZSqETmR1kCJuPAW/HJxqYhFXj3+w77hQQCIpjCT/xSJPdME7zKaD0ECBsHC 4RdKYd4p1HU6FhonHGWM5YRP9MamPMTae9/dEfyEd7As0G6oR5quogRagV7c4k3f7Hh5 V4sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=pKWfcRA4; spf=pass (google.com: domain of linux-kernel+bounces-6602-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6602-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8fc7e9199499..5dd4f3580a60 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -58,6 +58,12 @@ ck_icn_p_vdec: ck-icn-p-vdec { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index aea5096dac3c..17f197c5b22b 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -14,6 +14,13 @@ vdec: vdec@480d0000 { interrupts = ; clocks = <&ck_icn_p_vdec>; }; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = ; + clocks = <&ck_icn_ls_mcu>; + }; }; }; };