From patchwork Wed Dec 20 06:50:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Chu X-Patchwork-Id: 181484 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2457379dyi; Tue, 19 Dec 2023 22:50:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIi6aQmy8CfbJ+XVWCmy+Ezgal+bPwXg8Ksm0Eu0thRUqgZiMqxyB19WTi/Tn/Y8V3see/ X-Received: by 2002:a05:6214:1c4c:b0:67f:2680:81f2 with SMTP id if12-20020a0562141c4c00b0067f268081f2mr10607051qvb.77.1703055018302; Tue, 19 Dec 2023 22:50:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703055018; cv=pass; d=google.com; s=arc-20160816; b=klZeDJbBdFv8sXUY8bRPptogUiVUJmxfw/XhbIBXXhCzDRcvVAzoinGIQbpeWZ173+ kQ8Ccn43ePwHUEmkepgqHIbGdrtnu9baGOTDzMse+TjNikw5NpvQoys/jokhCO9IYS1A gQhkuq3WCfsJbdghM9s4zveZspSWMX+oGD982mcljpqMzChBzIJx1kh93Lk1s8FH1pyV X+XI9ISbbTTrPoqlXMIPyrKvQhzuvVYyg9JBEMtAVJO69qtV69erkgVai6NAhHpjY23W y+6qZRxyM0dEHLkGQ1Da+bSWrzIdU2XYol2Tj4MV2SJOMGms6r/hdiMZldT3ffycEBCb xzVg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:arc-filter :dmarc-filter:delivered-to; bh=4CmlhP+s8cUg2bc89Jci0HBN6GYfNiyocsvR77NpNKM=; fh=XmKRJ/v50SpME4RCtMcq0HQrISYhuSjIv2I/ppJXYlI=; b=O+eRs9SLZujs0ejnx3o8P6HzD4GYDCN8j602dYkd3f6nxkZGlCDawujCEkhbu7J3ub gEILGzmuSZB5m6VTqtAt+fElhhByVRex33vqzZ68CyBFRadGiJP1DpoOPVQWPUMWSmWJ cho4yY9FIWLhJ/XjCh9A7HJKdVDIlDIvWaF6+tzetZEssBH3AraozneskGHdBiysiD9K 1NF6I4LGcShvEvkEZDanMHVuxkNgtmE++/hBsSLoLMwFeerHK4eKtbQTnkZssTh3mOx7 ar3xkj4Gtvb6dddkoHRBQQm5xyMJ3Fptw84vL6Uk1ukAFbf8yp1E6rmNaCpzuULCdQzl EWNg== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id u19-20020a0cb413000000b0065b0161a263si14890920qve.27.2023.12.19.22.50.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 22:50:18 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7A9C7384DECD for ; Wed, 20 Dec 2023 06:50:14 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from NelsondeMBP.localdomain (36-230-154-232.dynamic-ip.hinet.net [36.230.154.232]) by sourceware.org (Postfix) with ESMTP id C7548385E019 for ; Wed, 20 Dec 2023 06:50:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C7548385E019 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=NelsondeMBP.localdomain ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C7548385E019 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=36.230.154.232 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703055010; cv=none; b=vNZNwgqGcTu7gdBkxHh2nfomMT34gV4jH8AE8T9zhDOox2WsU7nAz9mXJmo2PhYuSMaYO06QqgHJBDDt5ocHL3Qk0aX8VMFqE4uCZOjY/K0MM0tNqDqsm5BeU4qPafnsWstfLUV3cfVkXaK/VBxi7ZqIsFyY912X+OWsUpaBuY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703055010; c=relaxed/simple; bh=kMd0U8kicnWSd9gno4tBFjGJ2GB652nEuO67Ss0HlVg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=UVKlEQ2zx8iAnUVv2wgtQL5CK4oLDGJLvKAp2DbFrNHcKVSHkY1wbaLg/zH2IM8UZr3Ja3/CfN/+O0j3eSV8hWpoKJAusJy5TXcQB88UTkPxYmRV66omIFc0VALNC1SbGBXAzCkDtWttdr4Iuqqym/haH4uXNIjVyji4R5L0UPs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by NelsondeMBP.localdomain (Postfix, from userid 501) id D9FD1154A468; Wed, 20 Dec 2023 14:50:04 +0800 (CST) From: Nelson Chu To: binutils@sourceware.org, jim.wilson.gcc@gmail.com, palmer@rivosinc.com, andrew@sifive.com, schwab@suse.de, kito.cheng@sifive.com Cc: Nelson Chu Subject: [PATCH] RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objects Date: Wed, 20 Dec 2023 14:50:03 +0800 Message-Id: <20231220065003.2795-1-nelson@rivosinc.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, NO_DNS_FOR_FROM, RCVD_IN_PBL, RCVD_IN_SORBS_DUL, RDNS_DYNAMIC, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785782619044092075 X-GMAIL-MSGID: 1785782619044092075 * Problematic fix commit, 2029e13917d53d2289d3ebb390c4f40bd2112d21 RISC-V: Clarify the behaviors of SET/ADD/SUB relocations * Bugzilla, https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5 The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it non-zero by accident in assembler before. This causes troubles by applying the above commit, since the calculation is changed to support .reloc *SUB* relocations with non-zero addend. We encourage people to rebuild their stuff to get the non-zero addend of SUB_ULEB128, but that might need some times, so report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it may acceptable that stop supproting them until people rebuld their stuff, maybe half-year or a year later. Or maybe we should teach people that don't write the .reloc R_RISCV_SUB* with non-zero constant, and then report warnings/errors in assembler. bfd/ * elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of R_RISCV_SUB_ULEB128. (riscv_elf_relocate_section): Report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. So that can get the right non-zero addend of R_RISCV_SUB_ULEB128. * elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128. gas/ * NEWS: Updated. ld/ * emultempl/riscvelf.em: Added linker risc-v target options, --[no-]check-uleb128, to enable/disable checking if the addend of uleb128 is non-zero or not. So that people will know they need to rebuild the objects with new binutils to get the right zero addend of SUB_ULEB128 relocation, or they may get troubles if using .reloc. * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * ld/testsuite/ld-riscv-elf/pr31179*: New test cases. --- bfd/elfnn-riscv.c | 44 +++++++++++++++------- bfd/elfxx-riscv.h | 2 + gas/NEWS | 5 +++ ld/emultempl/riscvelf.em | 17 ++++++++- ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 2 + ld/testsuite/ld-riscv-elf/pr31179-r.d | 10 +++++ ld/testsuite/ld-riscv-elf/pr31179.d | 11 ++++++ ld/testsuite/ld-riscv-elf/pr31179.s | 13 +++++++ 8 files changed, 89 insertions(+), 15 deletions(-) create mode 100644 ld/testsuite/ld-riscv-elf/pr31179-r.d create mode 100644 ld/testsuite/ld-riscv-elf/pr31179.d create mode 100644 ld/testsuite/ld-riscv-elf/pr31179.s diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c index 042266e791b..6a1f1d9884f 100644 --- a/bfd/elfnn-riscv.c +++ b/bfd/elfnn-riscv.c @@ -1735,19 +1735,9 @@ perform_relocation (const reloc_howto_type *howto, if (howto->pc_relative) value -= sec_addr (input_section) + rel->r_offset; - switch (ELFNN_R_TYPE (rel->r_info)) - { - case R_RISCV_SUB6: - case R_RISCV_SUB8: - case R_RISCV_SUB16: - case R_RISCV_SUB32: - case R_RISCV_SUB64: - case R_RISCV_SUB_ULEB128: - value -= rel->r_addend; - break; - default: - value += rel->r_addend; - } + /* PR31179, ignore the non-zero addend of R_RISCV_SUB_ULEB128. */ + if (ELFNN_R_TYPE (rel->r_info) != R_RISCV_SUB_ULEB128) + value += rel->r_addend; switch (ELFNN_R_TYPE (rel->r_info)) { @@ -2530,9 +2520,35 @@ riscv_elf_relocate_section (bfd *output_bfd, if (uleb128_set_rel != NULL && uleb128_set_rel->r_offset == rel->r_offset) { - relocation = uleb128_set_vma - relocation + uleb128_set_rel->r_addend; + relocation = uleb128_set_vma - relocation + + uleb128_set_rel->r_addend; uleb128_set_vma = 0; uleb128_set_rel = NULL; + + /* PR31179, the addend of SUB_ULEB128 should be zero if using + .uleb128, but we make it non-zero by accident in assembler, + so just ignore it in perform_relocation, and make assembler + continue doing the right thing. Don't reset the addend of + SUB_ULEB128 to zero here since it will break the --emit-reloc, + even though the non-zero addend is unexpected. + + We encourage people to rebuild their stuff to get the + non-zero addend of SUB_ULEB128, but that might need some + times, so report warnings to inform people need to rebuild + if --check-uleb128 is enabled. However, since the failed + .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it + may acceptable that stop supproting them until people rebuld + their stuff, maybe half-year or one year later. I believe + this might be the least harmful option that we should go. + + Or maybe we should teach people that don't write the + .reloc R_RISCV_SUB* with non-zero constant, and report + warnings/errors in assembler. */ + if (htab->params->check_uleb128 + && rel->r_addend != 0) + _bfd_error_handler (_("%pB: warning: R_RISCV_SUB_ULEB128 with" + " non-zero addend, please rebuild by new" + " binutils"), input_bfd); } else { diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h index abcb409bd78..6959ec1b61f 100644 --- a/bfd/elfxx-riscv.h +++ b/bfd/elfxx-riscv.h @@ -31,6 +31,8 @@ struct riscv_elf_params { /* Whether to relax code sequences to GP-relative addressing. */ bool relax_gp; + /* Whether to check if SUB_ULEB128 relocation with non-zero addend. */ + bool check_uleb128; }; extern void riscv_elf32_set_options (struct bfd_link_info *, diff --git a/gas/NEWS b/gas/NEWS index 4c8d5946690..8647d9699ad 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -3,6 +3,11 @@ * On RISC-V macro instructions expanding to AUIPC and a load, store, or branch no longer accept x0 as an intermediate and/or destination register. +* On RISC-V, add ld target option --[no-]check-uleb128. Should rebuild the + objects by new assembler if enabling the option and get warnings, since + the non-zero addend of SUB_ULEB128 shouldn't be generated from .uleb128 + directives. + * Add support for Reliability, Availability and Serviceability extension v2 (RASv2) for AArch64. diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em index bb6298d3e8d..7dbd264c0e8 100644 --- a/ld/emultempl/riscvelf.em +++ b/ld/emultempl/riscvelf.em @@ -25,7 +25,8 @@ fragment <