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[PATCH] ufs: mcq: Adding a function for MCQ enable Date: Wed, 20 Dec 2023 14:27:37 +0900 Message-Id: <20231220052737.19857-1-cw9316.lee@samsung.com> X-Mailer: git-send-email 2.29.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Te0yTVxzN7dd+LczCZ5F5h4isQaMkPMrzFmSaScyXYAjGPclcrfQbJZS2 6YM4NOIorxZ0YHgogkPGQ8CAA4GC41USeYyQAcLYoNsAmY7J0yIBFdZS2Pzv3JNzfifnd/Nj YRwt04kVI1VRCqlQwsVt6Y1dRzw8Pr6YRHlffchHf95uxNFQJUTa7HIG+nttBEedk1o6yltc w5BpsB1DN/pSGahttJeJBquTGWj9TS0TlYw10pD+aT8T1U2PMtBwSyGOhjWDAGX8osdRx2IV QBXdGzSUlOyLGpZfMdCccZOO7qQX0dH10fs4yn3WzURJr9voqKzhV4Dmv+kCx53J4cdhpN5Y CsjmAiOTLK5Tk3VVWpxsnuSTWSUdgKwvTSSTe9vp5GptOk4uzfxGJ7N/vExee1AFyBd1LmRa RwYtwj4y9qiYEooohSsljZKJYqTRIdywM4ITAv8Ab54Hj48Cua5SYRwVwg09FeFxMkZiXg3X NV4oUZupCKFSyfX64KhCplZRrmKZUhXCpeQiiTxA7qkUxinV0mhPKaUK4nl7+/ibhedixSua VZrc6HKhqecv+hWw8Z4O2LAg4QeNsyM0HbBlcQg9gGVaE7A+lgGsbC3HLSoO8RLA2wXSHcdC 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X-CMS-MailID: 20231220052749epcas1p3b90f6c03110ff5f63ffc547ef0f35907 X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231220052749epcas1p3b90f6c03110ff5f63ffc547ef0f35907 References: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785777457109758015 X-GMAIL-MSGID: 1785777457109758015 From: ChanWoo Lee The REG_UFS_MEM_CFG register is too general(broad) and it is difficult to know the meaning of only values of 0x1 and 0x2. So far, comments were required. Therefore, I have added new functions and defines to improve code readability/reusability. Signed-off-by: ChanWoo Lee --- drivers/ufs/core/ufs-mcq.c | 10 +++++++++- drivers/ufs/core/ufshcd.c | 5 +---- drivers/ufs/host/ufs-mediatek.c | 4 +--- include/ufs/ufshcd.h | 1 + include/ufs/ufshci.h | 4 ++++ 5 files changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 0787456c2b89..a34ef3aac540 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -394,11 +394,19 @@ EXPORT_SYMBOL_GPL(ufshcd_mcq_make_queues_operational); void ufshcd_mcq_enable_esi(struct ufs_hba *hba) { - ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x2, + ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | ESI_ENABLE, REG_UFS_MEM_CFG); } EXPORT_SYMBOL_GPL(ufshcd_mcq_enable_esi); +void ufshcd_mcq_enable(struct ufs_hba *hba) +{ + ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | MCQ_MODE_SELECT, + REG_UFS_MEM_CFG); + hba->mcq_enabled = true; +} +EXPORT_SYMBOL_GPL(ufshcd_mcq_enable); + void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg) { ufshcd_writel(hba, msg->address_lo, REG_UFS_ESILBA); diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index ae9936fc6ffb..8195e01e7a3f 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8723,10 +8723,7 @@ static void ufshcd_config_mcq(struct ufs_hba *hba) hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; - /* Select MCQ mode */ - ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, - REG_UFS_MEM_CFG); - hba->mcq_enabled = true; + ufshcd_mcq_enable(hba); dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index fc61790d289b..1048add66419 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1219,9 +1219,7 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) ufs_mtk_config_mcq(hba, false); ufshcd_mcq_make_queues_operational(hba); ufshcd_mcq_config_mac(hba, hba->nutrs); - /* Enable MCQ mode */ - ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, - REG_UFS_MEM_CFG); + ufshcd_mcq_enable(hba); } if (err) diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index d862c8ddce03..a96c45fa4b4b 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1257,6 +1257,7 @@ unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, struct ufs_hw_queue *hwq); void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); void ufshcd_mcq_enable_esi(struct ufs_hba *hba); +void ufshcd_mcq_enable(struct ufs_hba *hba); void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index d5accacae6bc..e669fad11fd4 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -282,6 +282,10 @@ enum { /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 +/* REG_UFS_MEM_CFG - Global Config Registers 300h */ +#define MCQ_MODE_SELECT 0x1 +#define ESI_ENABLE 0x2 + /* CQISy - CQ y Interrupt Status Register */ #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1