From patchwork Wed Dec 20 00:30:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181377 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328185dyi; Tue, 19 Dec 2023 16:33:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IFBGhX71vaeNMrmJ7L9gWKpzN9adeNmWyHQomnXJpKXFpI7Pdv5G062eHnSV8PAdL5lWfFG X-Received: by 2002:a05:6808:3029:b0:3ba:59cc:d2d0 with SMTP id ay41-20020a056808302900b003ba59ccd2d0mr4543648oib.20.1703032392032; Tue, 19 Dec 2023 16:33:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032391; cv=none; d=google.com; s=arc-20160816; b=F0KOQhU+vp8g4r8pEyyIu06QAAdV6sB6dbg5en9YMCxmEwmXmW0J1h6sXhNtOtzDtw SB1DppcUZmQEdp5eEc5ovjan29tu4wkUrl2znlHVh9xobLVZxX927epRkAG4d255Ui7v 3SfVgwbjHRUfeA5WzRXZNOv5kJirlD0WSXdEolLccH3e3MAcoSv7WzlXuPNl2wY1T+Wi /CpzNKUrxCIMAxdM/y1IeMtMrtOxHdDANc0qfkRihdGTHTpcN0OW1HAQWQuP5ZwEb4MR 80dmqQW3VjuIIeXJm6o6BA2/2TVwn7JANgn022iseYV0TKSpn/wJyqfev2P5O8OdNPC4 dNTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=XfDCSXNar/0OypW7xIXC/SzvfN+SSQCc1nv247H/a24=; fh=MkFdVN+LDhRMwYZGMbT0hIwVISxx/ufGkS/k1knkCCE=; b=suBXzD96wVUgNNrGTA952mangY2fsqc8kH5zZCwWTdM2tU1OwREWo91wjNruvtJSNk w261DfEokHVAANnFFfMug+Yz+qQcufwIJJw6rggz95UI7J+sAtbn0MLtn731ud82W6Ff hfWf7o/nrKdQH2jnO+6FKHIjViZBoaW8fgyPckys2lVZZcBwzZ5PUUjiZjTYrMtH57jq OOlyNOE3l9NgFrWFp21Ilk4xYfMsiainz+ooNlNQvfEzEtiLuFtKazanIXXmbUsY/k4p 2E+FQmLguHGMpDqAC74pEcI6gw2uUbEca0PCwG8t4jZdMjPNwgXPQ3HbbFIQx8hsZbQl ngyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZeqmLtfo; spf=pass (google.com: domain of linux-kernel+bounces-6170-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6170-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [147.75.48.161]) by mx.google.com with ESMTPS id d14-20020aa78e4e000000b006cefb653cecsi7486515pfr.146.2023.12.19.16.33.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:33:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6170-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZeqmLtfo; spf=pass (google.com: domain of linux-kernel+bounces-6170-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6170-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id B13ECB2492E for ; Wed, 20 Dec 2023 00:31:38 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EBBEC1FA8; Wed, 20 Dec 2023 00:31:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZeqmLtfo" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F9A23B5 for ; Wed, 20 Dec 2023 00:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-552d39ac3ccso442454a12.0 for ; Tue, 19 Dec 2023 16:30:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032254; x=1703637054; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XfDCSXNar/0OypW7xIXC/SzvfN+SSQCc1nv247H/a24=; b=ZeqmLtfo6JFYe9N5fUjBun+6jpfOa4GSggXv+qpbM4aV4W4TbN8lSSlLIArybUtcJb RCm/uhE49H+OEcUHVz4wdgtibP42Mm/an3C3y0rqNK0M5tK8yIXBPnOJJsidiRcat3GP 328GLhkifGLR1n6vWTtYp9zT0/yiBwC5R8/FpcI0RSljOpM9T3O7kVMrMAHnsJ0O4YIc FAwfybbDKvohUwL079W1nntJuK1VMf9jdapZFbXPo0WelHYTLLI69xXhfLNBJmTwuVZS uOr3jGWcdpLSDjnEJoi6uR7NK3GAP0qAYCzua6zRk0yGWVgj2weFLPML3GGygWCIfX4t pnMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032254; x=1703637054; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XfDCSXNar/0OypW7xIXC/SzvfN+SSQCc1nv247H/a24=; b=oFxaY6VX9iDR4Q9BSz8BHFyJ2Ea8uf6emxioVOjxv0A7oEFHAN7JbFpJsl3Q5ud4lO loN1lzyiahfhgABFZ60Vroftv2oOjXPWgI6UK0EQL/6ZPbhp4LUk4892vBAFMuaPdbBH wn/DAAEKJ2OOcnBAtcSM/Ij2Zi4xMg/WSgwbNSJfKuVhtaqJOYFLx1bTth52zsj8Aamd 5/xC0OPLAqNrXkLuxvNreo5O8Yh7eVzgcrtsX9fumof+KGjFANsrYV3ojoBWhxJnjVoO 72rzjsLLJrqHTeMCHtlcqaStKFoZv6L115lfmj9cN2lZAF5pzrTXU+avJhT5CPerPXoy fHxA== X-Gm-Message-State: AOJu0YwnvN1Aqc7xci3FVbIJt9043EAHmdGOW4Tw7uyP0aS1jLLPFaNl Vi3rcyH7JKplYXanj4vkcMjya10OozJMZg== X-Received: by 2002:aa7:d448:0:b0:551:b477:8e58 with SMTP id q8-20020aa7d448000000b00551b4778e58mr1801142edr.13.1703032254401; Tue, 19 Dec 2023 16:30:54 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:30:54 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:42 +0100 Subject: [PATCH v3 01/15] clk: qcom: branch: Add a helper for setting the enable bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-1-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Johan Hovold , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032249; l=1413; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Bhpm8sfSCBACZPHOO1eUmAv4id2tp/m4vWhfhP3T9EI=; b=y6MBItszK6bIeyi7CDvuFWntvQh3lvXjyOQbIgMOK9B6+WVV9OJuisYq9tjoajhe+InHPuwjy bINoIU1LM5qAUrvYk0US/q2rTlJfui9It7KtcVJMuZd2jmXdMXtExvd X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758893255269745 X-GMAIL-MSGID: 1785758893255269745 We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 8ffed603c050..0514bc43100b 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -64,6 +64,7 @@ struct clk_mem_branch { #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) #define CBCR_WAKEUP GENMASK(11, 8) #define CBCR_SLEEP GENMASK(7, 4) +#define CBCR_CLOCK_ENABLE BIT(0) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -98,6 +99,12 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc FIELD_PREP(CBCR_SLEEP, val)); } +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) +{ + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, + CBCR_CLOCK_ENABLE); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; From patchwork Wed Dec 20 00:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181374 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2327873dyi; Tue, 19 Dec 2023 16:32:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IH/rzLfiZWhLuIeT5OMP4XSRlZ7TsMgMv7G69E1QbyxWQwHQhwT+SQe3JEYEmz7osu01Ssk X-Received: by 2002:a05:6358:5248:b0:172:d3c6:2830 with SMTP id c8-20020a056358524800b00172d3c62830mr6693811rwa.35.1703032348026; Tue, 19 Dec 2023 16:32:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032348; cv=none; d=google.com; s=arc-20160816; b=0UAOlJbid5EZYIXAudvbmJMjMi9q62ElbmlEjFJ7gWYiixVRjP4nOExs8NN9XzLmcM HNMCm0gzX29wxcs3lAYd4VJvnjZKtUVDWvZbYyvjAPy+/lpjSiXIbL3H+7okXWLTxlaf Qd5MiJGQpuR2L6znpW5T/iS2+ii3TA8ICDpyvGWZ/FrKHs5GTklZNLx0G5sCGMLfTorj iPUk31XopPhw8Uycj6/C73tQz5XZbUsii08vkU1ooRnegznnexFA3A3mXVyDhxfTAjHQ PO9S5bQkoTxlmEgHMAFhCnBxr7kzX49eb15DCNhxMpm9FLvyjVqd1DFV/vtX1fWYjv4j NELw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=0ArWtAjMjG2oW52HAqWjg1fB/72cOidR8cjWCpvKn4o=; fh=/9IvASkZ5EB5zGoodRetKiJiPtH7a6iK9GbsrCyU1gk=; b=rdi9IHnteuwnr3ZONeMZI7Y72rxEeSWvC756E355wBSUQ2x6QmR9h3aT+GWz+mdGRH +GuXPNJP75GQ6AiWEwBDII3fko5ioInHHAw51CkpCdfif+r2NDbXkp9wEb2futOxfSTc Pzku9OuWIOsjLd8+sK4AB+FUPvPMjgQUs8L4IVSyTEl76soly+67rg9rxlujV/h1mre3 HobSd4giB9TKkNKkMvdia3aez9Ei+YkUvyS7cX2tBjJvZQJDDqgAfY5J/wygNGG3G8HX nfUy5Hsyk48O6nypIynxGaGyy+t7P4XFwTfoAoIzy5aaLBimwAIEJMKa5IARBcIY86cs t1YQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vfh27w88; spf=pass (google.com: domain of linux-kernel+bounces-6171-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6171-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id bs19-20020ac86f13000000b0042785be8bdasi757722qtb.156.2023.12.19.16.32.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:32:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6171-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vfh27w88; spf=pass (google.com: domain of linux-kernel+bounces-6171-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6171-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id B083F1C21212 for ; Wed, 20 Dec 2023 00:32:27 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8E90BC2C5; Wed, 20 Dec 2023 00:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vfh27w88" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3252443C for ; Wed, 20 Dec 2023 00:30:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-50e4a637958so1513646e87.2 for ; Tue, 19 Dec 2023 16:30:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032257; x=1703637057; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0ArWtAjMjG2oW52HAqWjg1fB/72cOidR8cjWCpvKn4o=; b=vfh27w88ld4IcI3UGNSUSAQK1sSoo/r52Nd4WVfCtTZDX3rf9fStIeolblaoAt/6yN iEvW6n9PK8Jf94yeOu1lM3BBvPRpgsUbswq94H5HuMUB3he7NuE/UY/Tl3BF5zJ1fDoZ 7jgU0mwIA21cb6zcxXzzuEH45f0la4KF365VozTHSZYFZ82FSXXpjecvAzHE5fCMvtIf 2WrquiIn4oiXFYNe3WpUHV9I+ZC6olDh5qTYkf/HrxnHAEOj9Fr4DIJY1HFCzufroqWr HquvwFyBe+Et3TN2KPyumvOhTba6pJM3XDEKTWF2nToNnTIq6pHTkDKFCkNMFt3IWsd8 OUSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032257; x=1703637057; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0ArWtAjMjG2oW52HAqWjg1fB/72cOidR8cjWCpvKn4o=; b=EnAZHxOlTXtb7waquw1/26SwVqRYIvC3RUnEwey2Mga/pC4t+dlg6XO3XwX9NSEinM vAUytddzENvQnALOVO/iYI8ECfji2Yek56zcrG1aVPapIGB2QWeJMlDaZXt3J090W2x5 oyudr33P6jthX75J7T4dxrmAaWmCb5uwGMaYwhBIGYgeR14kbt2W1PXZuCId8E15TEkD QQ1QrVkI6cOosjY2hLwA9E6+W4sMNyyLppIYXSMd7xuDY62AegAuPSlmoNiHzj7hg6NS tfSmAr7IDUC/Ukn758WObYO9/A/OvLzls6LJvi4U9YshRTmANmaqUCiJL0/5cXP+HC0F eWLQ== X-Gm-Message-State: AOJu0YwcAFCJAbNsY3zOmfc4if97Y6f/BWBqXhg0OeBcEPXrYDBg6IQi A3mCuaRKJUgwqgPJETSlOcuA5g== X-Received: by 2002:a05:6512:3a95:b0:50e:4a7d:5ea8 with SMTP id q21-20020a0565123a9500b0050e4a7d5ea8mr426164lfu.74.1703032256657; Tue, 19 Dec 2023 16:30:56 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:30:56 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:43 +0100 Subject: [PATCH v3 02/15] clk: qcom: Use qcom_branch_set_clk_en() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-2-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032249; l=35786; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EB1ZOjMzAQG7Bt9lDBQLMP1PxUxP97t3l2JekWavNT8=; b=dwqeH/0k+f1uLGYEndyVH0PB6EOCz5a26ZFXe+hZWVXMK05sX3gYFgjWrJ3IcSfDeKYe1JI+q TkJa/VQzehJBMvITLWojGn2GizsfDmhSnzC0v0+xZrrf/QPZm4w3uGn X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758847374507404 X-GMAIL-MSGID: 1785758847374507404 Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/camcc-sm8550.c | 9 ++------- drivers/clk/qcom/dispcc-qcm2290.c | 3 +-- drivers/clk/qcom/dispcc-sc7280.c | 6 +----- drivers/clk/qcom/dispcc-sc8280xp.c | 3 +-- drivers/clk/qcom/dispcc-sm6115.c | 3 +-- drivers/clk/qcom/dispcc-sm8250.c | 3 +-- drivers/clk/qcom/dispcc-sm8450.c | 6 +----- drivers/clk/qcom/dispcc-sm8550.c | 6 +----- drivers/clk/qcom/gcc-sa8775p.c | 24 +++++++++--------------- drivers/clk/qcom/gcc-sc7180.c | 21 ++++++++------------- drivers/clk/qcom/gcc-sc7280.c | 19 +++++++------------ drivers/clk/qcom/gcc-sc8180x.c | 27 ++++++++++----------------- drivers/clk/qcom/gcc-sc8280xp.c | 24 +++++++++--------------- drivers/clk/qcom/gcc-sdx55.c | 11 +++-------- drivers/clk/qcom/gcc-sdx65.c | 12 ++++-------- drivers/clk/qcom/gcc-sdx75.c | 9 ++------- drivers/clk/qcom/gcc-sm4450.c | 27 ++++++++------------------- drivers/clk/qcom/gcc-sm6375.c | 10 +++------- drivers/clk/qcom/gcc-sm7150.c | 22 ++++++++-------------- drivers/clk/qcom/gcc-sm8250.c | 18 ++++++------------ drivers/clk/qcom/gcc-sm8350.c | 19 +++++++------------ drivers/clk/qcom/gcc-sm8450.c | 20 +++++++------------- drivers/clk/qcom/gcc-sm8550.c | 20 +++++++------------- drivers/clk/qcom/gpucc-sc7280.c | 8 ++------ drivers/clk/qcom/gpucc-sc8280xp.c | 8 ++------ drivers/clk/qcom/gpucc-sm8550.c | 9 ++------- drivers/clk/qcom/lpasscorecc-sc7180.c | 6 +----- drivers/clk/qcom/videocc-sm8250.c | 5 ++--- drivers/clk/qcom/videocc-sm8350.c | 9 ++------- drivers/clk/qcom/videocc-sm8450.c | 12 +++--------- drivers/clk/qcom/videocc-sm8550.c | 12 +++--------- 31 files changed, 124 insertions(+), 267 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c index dd51ba4ea757..de424913cf47 100644 --- a/drivers/clk/qcom/camcc-sm8550.c +++ b/drivers/clk/qcom/camcc-sm8550.c @@ -3536,13 +3536,8 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); - /* - * Keep clocks always enabled: - * cam_cc_gdsc_clk - * cam_cc_sleep_clk - */ - regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index 9206f0eed446..a6d905feeddb 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -519,8 +519,7 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c index ad596d567f6a..2d40febbedc2 100644 --- a/drivers/clk/qcom/dispcc-sc7280.c +++ b/drivers/clk/qcom/dispcc-sc7280.c @@ -878,11 +878,7 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - /* - * Keep the clocks always-ON - * DISP_CC_XO_CLK - */ - regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */ return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); } diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c index 30f636b9f0ec..606beb34028d 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3178,8 +3178,7 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev) goto out_pm_runtime_put; } - /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ out_pm_runtime_put: pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 1fab43f08e73..a3cf7d09dfb2 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -583,8 +583,7 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index e17bb8b543b5..eedb48311ac9 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1365,8 +1365,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, 0x8000, 0x10, 0x10); - /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 2c4aecd75186..2c374286ee66 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1787,11 +1787,7 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); - /* - * Keep clocks always enabled: - * disp_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index aefa19f3c2c5..cad2ca39c6c6 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1772,11 +1772,7 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); - /* - * Keep clocks always enabled: - * disp_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 8171d23c96e6..9145ceecbb2f 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4742,21 +4742,15 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) if (ret) return ret; - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, - * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. - */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index a3406aadbd17..8fcf30fe2050 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -2443,19 +2443,14 @@ static int gcc_sc7180_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - /* - * Keep the clocks always-ON - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, - * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 2b661df5de26..b2e2fa2a01a7 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3453,18 +3453,13 @@ static int gcc_sc7280_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK - * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index ae2147381559..764cd41c5660 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4579,23 +4579,16 @@ static int gcc_sc8180x_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Enable the following always-on clocks: - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK, - * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and - * GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ + qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index bfb77931e868..1ba78990b9f4 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7543,21 +7543,15 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) goto err_put_rpm; } - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index d5e17122698c..314931b4b10f 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -1611,14 +1611,9 @@ static int gcc_sdx55_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON as they are critical to the functioning - * of the system: - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK - */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c index ffddbed5a6db..999268cc8eee 100644 --- a/drivers/clk/qcom/gcc-sdx65.c +++ b/drivers/clk/qcom/gcc-sdx65.c @@ -1574,14 +1574,10 @@ static int gcc_sdx65_probe(struct platform_device *pdev) regmap = qcom_cc_map(pdev, &gcc_sdx65_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON as they are critical to the functioning - * of the system: - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK - */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); + + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c index 573af17bd24c..0189da8c7a13 100644 --- a/drivers/clk/qcom/gcc-sdx75.c +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -2936,13 +2936,8 @@ static int gcc_sdx75_probe(struct platform_device *pdev) if (ret) return ret; - /* - * Keep clocks always enabled: - * gcc_ahb_pcie_link_clk - * gcc_xo_pcie_link_clk - */ - regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ + qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c index 31abe2775fc8..ce7c209a3ed6 100644 --- a/drivers/clk/qcom/gcc-sm4450.c +++ b/drivers/clk/qcom/gcc-sm4450.c @@ -2849,25 +2849,14 @@ static int gcc_sm4450_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); - /* - * Keep clocks always enabled: - * gcc_camera_ahb_clk - * gcc_camera_sleep_clk - * gcc_camera_xo_clk - * gcc_disp_ahb_clk - * gcc_disp_xo_clk - * gcc_gpu_cfg_ahb_clk - * gcc_video_ahb_clk - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */ regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 3dd15d765b22..fe1a004c259d 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -3882,13 +3882,9 @@ static int gcc_sm6375_probe(struct platform_device *pdev) if (ret) return ret; - /* - * Keep the following clocks always on: - * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK - */ - regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index d9983bb27475..673810be8310 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -3002,20 +3002,14 @@ static int gcc_sm7150_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - /* - * Keep the critical clocks always-ON - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, - * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, ARRAY_SIZE(gcc_sm7150_dfs_desc)); diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index c6c5261264f1..a8aa3f1f6373 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -3643,18 +3643,12 @@ static int gcc_sm8250_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - /* - * Keep the clocks always-ON - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, - * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, - * GCC_SYS_NOC_CPUSS_AHB_CLK - */ - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index 1385a98eb3bb..f7e1775663f5 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -3806,18 +3806,13 @@ static int gcc_sm8350_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - /* - * Keep the critical clock always-On - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 563542982551..c9544f1bbd71 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -3280,19 +3280,13 @@ static int gcc_sm8450_probe(struct platform_device *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); - /* - * Keep the critical clock always-On - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 586126c4dd90..bb45bc6d72db 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3344,19 +3344,13 @@ static int gcc_sm8550_probe(struct platform_device *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); - /* - * Keep the critical clock always-On - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52024, 0x0); diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 1490cd45a654..0eeca1e9ccc1 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -457,12 +457,8 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - /* - * Keep the clocks always-ON - * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK - */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */ regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 8e147ee294ee..55102f648a5d 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -444,12 +444,8 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - /* - * Keep the clocks always-ON - * GPU_CC_CB_CLK, GPU_CC_CXO_CLK - */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ + qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 420dcb27b47d..98ecac49c1b9 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -575,13 +575,8 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - /* - * Keep clocks always enabled: - * gpu_cc_cxo_aon_clk - * gpu_cc_demet_clk - */ - regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); } diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c index 9051fd567112..e4c20cc4c998 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -401,11 +401,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev) goto exit; } - /* - * Keep the CLK always-ON - * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK - */ - regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */ /* PLL settings */ regmap_write(regmap, 0x1008, 0x20); diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index ad46c4014a40..d11a5bdf7da7 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -383,9 +383,8 @@ static int video_cc_sm8250_probe(struct platform_device *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); - /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index 7246f3c99492..a14d6702e6c3 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -558,13 +558,8 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index 16a61146e619..52a4b08ad577 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -423,15 +423,9 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_sleep_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index f3c9dfaee968..28747d483a30 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -428,15 +428,9 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_sleep_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); From patchwork Wed Dec 20 00:30:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181387 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2330725dyi; Tue, 19 Dec 2023 16:39:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IHFu5EXihm65+IATd0SEam5hjk9cDd7I3tctNbfC8fD6ItiyE42LdUgFap/+I7KVusRjXnI X-Received: by 2002:a05:6e02:1bed:b0:35f:b7a3:5dc2 with SMTP id y13-20020a056e021bed00b0035fb7a35dc2mr3905576ilv.50.1703032786493; Tue, 19 Dec 2023 16:39:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032786; cv=none; d=google.com; s=arc-20160816; b=sdg42ONTAEERwodZVKwGwl+iP3D4zQF1r+ssVGVj+uObDFMs9hbHAIV381xPbFtG0M mV3EPlirNYLJJiHekgSh7y/sWKFd8WjSee5k8Vi++iOZWJuJr1egqHwAkEkI+Rh0r4cT azLMNJ+nGAS3dOg0zngORM6dVD7c8StK9tVhsLxXyRNdcm9coUVOuzTF8kkU8xQXAOwj NDhsNPez9ckA/dgjjO1V59LJObp66dL4EjbMSB9JhhJJKzaxlekHpVjeV/r8dclZv0cv 1J9xkf3xVR/3+R4A5tmEmFs6fvMzl+eFeBw14T7kBQADc3XJ4Qq1k71ndO/2QtFo61ms oKnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=I+ZrJPlKCE2XobzOUvnm/u3k2fKz6EiI6LipZZTMtxo=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=LTwATnEtjrtTgRcRfNMFppk4Pt61DkmbugBvHx1+pNpHWBqFx/drfcDLtEbOB7vlQp Kcv1DpMX+UoaMRdUb7Gu4Nif5zH/I6jv6uN2Zrw1hFIfPUUJyrdtr+nbVbi2BJmrX5Gr CfZQoc8kbzMUbj6gMc7h4FtO21VSk/C9YuHVStrroRkIcEUcNaqN4zeGkfG3VXMo7Pjr 4Fm8MXivUtx8YJOGN9Ss3fmeYtQl0StJtIn4QWTHebNKL+XRypVGP/e0GUSbohv52/DO WR6WKj1P1dB0jQocIMXC7PmPuJJuf5572VDf6f81Qs/0LGNutSIKDhCGuM5Ei2mk/mmn JqcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OBXNwBcJ; spf=pass (google.com: domain of linux-kernel+bounces-6172-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6172-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id x15-20020a170902ec8f00b001d332818f37si14189817plg.188.2023.12.19.16.39.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:39:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6172-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OBXNwBcJ; spf=pass (google.com: domain of linux-kernel+bounces-6172-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6172-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 5967D28A7CC for ; Wed, 20 Dec 2023 00:32:26 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8B23AC153; Wed, 20 Dec 2023 00:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OBXNwBcJ" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9408567D for ; Wed, 20 Dec 2023 00:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-553729ee917so3280667a12.1 for ; Tue, 19 Dec 2023 16:30:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032258; x=1703637058; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=I+ZrJPlKCE2XobzOUvnm/u3k2fKz6EiI6LipZZTMtxo=; b=OBXNwBcJwkj3eEtDqKe1Mf6Piu1WkFEhphiRlHYruz4xtMWZQJFZfC3WiOKqqDWpwD cVBzH/MsZvl1LQN3PfHu/iI8ksvZHJx2bMB6Vb4ljk4K+kYiZnAX6Muls40yhQr4FD6r 79jS1Ypq7/ooN/pf30R2pv1D/irrdcU6R4PqXpEudHJ+VyXMzA/84C0F/3sJZojgwf6z 1FleK9srucY2MhhgaA2+7Dnnuz4pvlsBEVIJQyadct35Vc9duc6zgldQJbUKpEF1aqcR M/c2aJBkve7OXdEHZ9Te3TYjkBgZWfkAO7q1kCT8LPU9Hxx7joNWUiVmxMdNC3+XkB4x wmZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032258; x=1703637058; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I+ZrJPlKCE2XobzOUvnm/u3k2fKz6EiI6LipZZTMtxo=; b=wMAOc9OuLz5G6pCDDm+Lkmtx68/bhUFrx+2WignAzzXMDpYPQrEpIrrPE/vJFy4/aS FjIE2MQGhGIytdeBkfsYBKEizOHgi7dRwUddFMA7OH+JqdXieiXXLz1jToCW0uiNbMiO dRin7n/TuAXW9IxxydWlhRnPWulJsh4SRpYSTxcVsgS4sFR4vR9OuEfISXhqf7UTsdOV V7tJfJvYOjlTnHzK38p6NfWFpD3Zacpu6ZvYB3LW3XP5/9fo4PEqP5Sm1y1hyIYXu5sc C01Cohj4dccrJk3BHTU/NraJOdudQUqtc+N8em7lycnH/IIRo8hGGSlD0pa2x8H1asEy /2yA== X-Gm-Message-State: AOJu0YxqsY0y2nLm3LReI8guTKaWF/boa6JMS0ZXevBQsGGj+yXu5TjZ 75CKhWzQq9M/qtqncjmWdyeS5A== X-Received: by 2002:a05:6402:902:b0:54c:4837:93ee with SMTP id g2-20020a056402090200b0054c483793eemr10093987edz.53.1703032258126; Tue, 19 Dec 2023 16:30:58 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:30:57 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:44 +0100 Subject: [PATCH v3 03/15] clk: qcom: gcc-sm6375: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-3-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=6876; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yxxhuhuXRALb59eSaLlJgngK5MCV51x+hc7h/IwV3Uw=; b=DUkI+s/Zz8S7uxAJ1PwTs3QDi+SPqurAyW1vY5A7RRUDidt3dVKZ5SWknCvhlM5Atr2+Dyyur cq3/pXCpTJYDvItuzBA9IiZIhmoyIjH2dK5AeCk/90dKWxzSL3FB+zL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759307068155755 X-GMAIL-MSGID: 1785759307068155755 Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 94 +++---------------------------------------- 1 file changed, 5 insertions(+), 89 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index fe1a004c259d..44c74e74885f 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -1743,22 +1743,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2309,22 +2293,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2455,22 +2423,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -3094,26 +3046,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3433,22 +3365,6 @@ static struct clk_branch gcc_venus_ctl_axi_clk = { }, }; -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_video_axi0_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT_VOTED, @@ -3615,7 +3531,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, @@ -3671,7 +3586,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, @@ -3683,7 +3597,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, @@ -3739,7 +3652,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, @@ -3766,7 +3678,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, @@ -3885,6 +3796,11 @@ static int gcc_sm6375_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x79004); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17004); /* GCC_VIDEO_AHB_CLK */ clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); From patchwork Wed Dec 20 00:30:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181375 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2327925dyi; Tue, 19 Dec 2023 16:32:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXfsK4dW2eW5bRejZWKYsz+8ERxkA3S7CAWE0b8jRD+jZxEAe9JTBRJZYvTxEqQFdxdIgM X-Received: by 2002:a05:6870:3929:b0:204:20b:2de with SMTP id b41-20020a056870392900b00204020b02demr886832oap.35.1703032355260; Tue, 19 Dec 2023 16:32:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032355; cv=none; d=google.com; s=arc-20160816; b=pEzOaipQcUS5fauDX16+gWihtCAP3QJZU3+qy1+RXnJ+bUfeLe5P0rAAiDspcr0JYq ymD3rHNswX+LSJDRaMT+ka5cmzowcWXHfUAUWixYDHp6vLbR46IQdoj7b9h/47icV4i9 hSFjacyGeCu55mHA+PswPTYWgDJvUjdJVh0yYXSATeVdexiK0rBxD+v5crS25S+BaDSM jln2hUSit09GiPy7OSP/1zDEKJF6x8o34jPdn2U4T07Hn+I4gFOecJgQwZWcQ6EwNhmU 1ggBPfgx1LJYkXJQ+YD5XEN9+sPtNES4JWusyGAwK8l7XrpMMcFewocL/158+LqAXlDk 6wxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=F/XYeH7WpVmrRfjifn0LxMiuPs0oZ+EZwghWZGkWLzI=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=CaBn+23D+ISExU2/pdMCJrw5DKdYUKR1pSPlDCmy/LwerxtjO/Yy3uX3rfvbvsY23H W+4sLqkh9Lz5kUTI7P/EfTQp55fxtiEH2byP3r7vGAEIrqd5tfkHtnWNXMdbtTlAyzsE U/5gjdn0vp3N8KA/Et9Wac97/OhpctgCeJouhuYPZQbmIAjnYHUfDBqdZd77s4uY9XvF whA6eBzC2gj5wmQwku9pC5fEvkoN/VhszHsEDN39mOVJ7eacfE364dGJNnCpX3M6qDTg ktOK7V5lNndqs/8+SiWC5cxjTHHEX3OFzcXpYEVoWLeacWULg3ltHccwXy00vX+9i+sK D8Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B1wiASmD; spf=pass (google.com: domain of linux-kernel+bounces-6173-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6173-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id br17-20020a05622a1e1100b00403f0dfedb7si29981351qtb.193.2023.12.19.16.32.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:32:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6173-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B1wiASmD; spf=pass (google.com: domain of linux-kernel+bounces-6173-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6173-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id D4FCC1C24F44 for ; Wed, 20 Dec 2023 00:32:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0E51117D8; Wed, 20 Dec 2023 00:31:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="B1wiASmD" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BCF86FCE for ; Wed, 20 Dec 2023 00:31:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-552d39ac3ccso442544a12.0 for ; Tue, 19 Dec 2023 16:31:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032259; x=1703637059; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=F/XYeH7WpVmrRfjifn0LxMiuPs0oZ+EZwghWZGkWLzI=; b=B1wiASmDbWdNpJW1qrAy0VLJyNG7zvBTwgCHbq6JnjBQPkXVCvFfEf2e/Kj+pZt/u9 OOqK4ot1qeFRVb0NrWnZ+MQqvpQ4ZPJplaovtmaxtf2plKDa5dRs2y6a+mnHcx/eqilt hJBCek1SCcNdigUkq8pFjJWZJztV5tVaYH7DGWIFGyw6xyXMMTLSzalRAK5cqaU16j8G xbR7K8eJMYbPQsLB4rNx5jbc64XOh/K/5xNtffScxMfiwagXY6JPN+xHUlYfNZeKHgXF FwwKxb6ql8bV54CZU8FLBftUIEE1a1PwvFtPy2CCMR+B9efxdFuEc/HDP96YauSk/IJY fi2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032259; x=1703637059; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F/XYeH7WpVmrRfjifn0LxMiuPs0oZ+EZwghWZGkWLzI=; b=J1Q+cgp5t0f4oCqgxsdNHmZ8aN/v2g6EA9bybl8lGdVvylWkGbUb3eOcthqvs1uE0w tJykUOAxPUxNViYkK9XDaUh6VhNwgkb9aWzDJda8QM7XnYb5Gq9EFbIjabbxwY90nena iQQc3sYKAI76l2iphZ66xkFnakVTWGbAO+UWRk602LMZl4YyItbijEO/7RQG8Nv+AEQY 1BEToCKFnuMpB1hHkxw/8nrsoZovRqYQHf1Y3SAgwqkwOTeGhcqBhk13076NdMjCG+7w jXq1tQZrbpLLjOasgvyyjPLLvT8cRdV4kEF/Gobrm0DlESHlhLvyy13ihUsix7UHXVVi JBDQ== X-Gm-Message-State: AOJu0YzydXVcTZKFJaArqPmoK8eoqxhCbWw+oXIYi7RPPJwEqjEQO0MS PMc8ERXxDbFZY2dDkDg0KQm5oGrxlm50vw== X-Received: by 2002:a05:6402:3d1:b0:54a:ff0f:78d6 with SMTP id t17-20020a05640203d100b0054aff0f78d6mr2069269edw.0.1703032259623; Tue, 19 Dec 2023 16:30:59 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.30.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:30:59 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:45 +0100 Subject: [PATCH v3 04/15] clk: qcom: gcc-sm6375: Add runtime PM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-4-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=2103; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4UqVyq+AxibHs92QeNlETxsytT0HCThfcpvGOwkFOrI=; b=iiSeyWs/O2OzHZmgBEJRedCWaba3810lLJ3uOd1HuHXPKwcNas15q3llZzKivf1j0k5R+CVyG 64XDCxRuzftCQE18X1QayaGxOhMJjD7K/qKRoBUdjbrvpkjMZIkWJNv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758854603795572 X-GMAIL-MSGID: 1785758854603795572 The GCC block on SM6375 is powered by the VDD_CX rail. We need to ensure that CX is enabled to prevent unwanted power collapse and that the reference is dropped when unused so that the system can enter a firmware-managed lower power state. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 44c74e74885f..dff0b2f20759 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -3785,13 +3786,25 @@ static int gcc_sm6375_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_sm6375_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); - if (ret) + if (ret) { + pm_runtime_put(&pdev->dev); return ret; + } qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ @@ -3807,7 +3820,10 @@ static int gcc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); - return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gcc_sm6375_driver = { From patchwork Wed Dec 20 00:30:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181376 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328043dyi; Tue, 19 Dec 2023 16:32:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IF6pbqInhUsFeYDVkJtN3xnrPzMtNJNSdfb0J40Gc0UFQCPZMyUJpcf6RDFxUjxTHQO2+s2 X-Received: by 2002:a17:906:178f:b0:a19:a19b:c6ff with SMTP id t15-20020a170906178f00b00a19a19bc6ffmr9972565eje.79.1703032373287; Tue, 19 Dec 2023 16:32:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032373; cv=none; d=google.com; s=arc-20160816; b=hG2EDbSDFF5tpFtYoyOUG6y2zI/Ka2dmDaPs81eki5plB3RrzxlNXNB3ySo6cVCg84 Ld+sJ2vDR2rIymG6Dl3h8ho+ftr6778ist8MazucVuXNQmUotXtia7P48m/d12nAeMk7 i09t3pzvvPJGfznNAMIP4JMdfnTXrcrdtKpX2xtb/NdtNy9xT6mFF7up7U2TTKuoXMbs 0MKFFGuDcQppaG1DICIvxfmJu33ONF6aEGlAAgeSvaHVjMT7iLBR+73XAKwnTkhS0zto cLImSGV/71pqdVY8tvQ0fZdNetn08tE0REIFICu8Sf4Ih7P1goOQaBVPk5pM7qVl5Or1 obVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=v976SmXxRiZAGe8x+4gqFafbRMwHJbbnvfO+A1vZOV4=; fh=/9IvASkZ5EB5zGoodRetKiJiPtH7a6iK9GbsrCyU1gk=; b=VktWaubxXk33KQAUxubxcC4IicWa3KcW75t4wX9Oe7oBOS5k4gmHsCc/6dfSlQLFC8 tAjFn/513aiHKRPeCXLhVJ8qxxIcS58T+AJnbtoqMX50vI19vBz+/fh4j++igynUPbsu 3zvZKMBBG2di9ZcZLWKrPcMOTDaFeUia8mCiaKepTPEfI0l8QcNems/QwG5fUg15xH3O zgP8ArqSfwWMcF/gGZRCFEqWnv0X6fPGHCoGPySxnU3RAemfskoV7xpODE8VvwRTlanj ououAJUlBBn2GWGXoB/xC92NfAG/oYzz9xW2ueFmHdRzXTxjqABgLLHjj5lMUR3MfKGo x2WA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BSGqCX4R; spf=pass (google.com: domain of linux-kernel+bounces-6174-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6174-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id l12-20020a1709065a8c00b00a233733bff7si2891206ejq.699.2023.12.19.16.32.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:32:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6174-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BSGqCX4R; spf=pass (google.com: domain of linux-kernel+bounces-6174-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6174-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id B29EF1F26516 for ; Wed, 20 Dec 2023 00:32:52 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5517B11715; Wed, 20 Dec 2023 00:31:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BSGqCX4R" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B60E567C for ; Wed, 20 Dec 2023 00:31:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-54cd2281ccbso6195278a12.2 for ; Tue, 19 Dec 2023 16:31:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032261; x=1703637061; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v976SmXxRiZAGe8x+4gqFafbRMwHJbbnvfO+A1vZOV4=; b=BSGqCX4R61NhDKiPiYWISHxAbdNWsr7j5o/2LgoCwoAV9w1AvMgEnVMgBmGbgS9Uxw P4USeUEAqVE/obOTfloqATI7o2GrM5esnoFb/V6cRSsIBTFPYQs2vcxIMjIgdQaHUMd3 LUwwQ0E5x69uuRlbmKI1VDSW2u7O6mURseeKUG08Hfby4AdJsHOGk5mG6F9bPt9Om4zt LCb5AvkwAf0pnBN1d4uGCaGeJKwDVqncmMg0cy9jpdQEarll1AKyIPtaR7MFFQy4aqB2 2iMeuExxFyy82kXTo3/wB8sLmRsPNOxA7bdQG2h+M/AYzAEyLRITVVtvjtzDCTxERp9u 9nVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032261; x=1703637061; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v976SmXxRiZAGe8x+4gqFafbRMwHJbbnvfO+A1vZOV4=; b=hx3aCyO4Ya8NQ6jzKA7Sk2qyk2w5JfQs0amSI+ZdN1W8T8YpaqWWXl5iX5DlkzYXL1 BMwnbU8P2YbnLHpLvXoHNx3VAuvL2gZLRpbIpmaR3XqyPX0D3uL2/19OLGnACNs7ClXC cMcpHt85G2x4pxyrDiyp+Z2GxRxbR66dPxA/6YVrA/U7Cz8BPhbuU/e9hvyrDKifsSek cSvE18rNAMOsJ3vjrbxB0vn0+D9d51bKROIYAawzqXwFEhlE9UGOLujJz9P23sGFdEj2 AkwKKE9F6GRm64EO5izquDV9Hv383c93s+uzviZ2EFn+/fP6giUZLKWn2ANNWzDtvS54 fPAw== X-Gm-Message-State: AOJu0Yzs+x19Loj6lUPWj0wp6OiXWsfwSYd2Iq8DhkT0PC6enbt4tylp YzrHsJvOOJyQ7OXRiu4KSL3I9Q== X-Received: by 2002:a50:d7c1:0:b0:553:6195:b866 with SMTP id m1-20020a50d7c1000000b005536195b866mr1880176edj.66.1703032260989; Tue, 19 Dec 2023 16:31:00 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:00 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:46 +0100 Subject: [PATCH v3 05/15] clk: qcom: gpucc-sm6375: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-5-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=3028; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=fXRoqdRlJHc5Qzabc5UfVEq2iMwhjOiaxUJ84TrgGsw=; b=Mepc+kyD8ErB7ZogQGNmtUTVAoPSNFvg4MV4ZMzEdy8x1+AVJHQvX5wrEv9IPlnTUbaCxaKQd 1Mq2WRj8a/TAmOUIj8Hmu/0GMNrLOgd8fFXvg7ZC/+mZCbIeiWIic0i X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758873951583554 X-GMAIL-MSGID: 1785758873951583554 Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6375.c | 33 +++------------------------------ 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index da24276a018e..6d85936dd441 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -183,20 +183,6 @@ static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = { }, }; -static struct clk_branch gpucc_ahb_clk = { - .halt_reg = 0x1078, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_cx_gfx3d_clk = { .halt_reg = 0x10a4, .halt_check = BRANCH_HALT_DELAY, @@ -294,20 +280,6 @@ static struct clk_branch gpucc_cxo_clk = { }, }; -static struct clk_branch gpucc_gx_cxo_clk = { - .halt_reg = 0x1060, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_gx_cxo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT_DELAY, @@ -381,7 +353,6 @@ static struct gdsc gpu_gx_gdsc = { }; static struct clk_regmap *gpucc_sm6375_clocks[] = { - [GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr, @@ -389,7 +360,6 @@ static struct clk_regmap *gpucc_sm6375_clocks[] = { [GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr, [GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr, @@ -455,6 +425,9 @@ static int gpucc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); + qcom_branch_set_clk_en(regmap, 0x1078); /* GPUCC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1060); /* GPUCC_GX_CXO_CLK */ + ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); pm_runtime_put(&pdev->dev); From patchwork Wed Dec 20 00:30:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181388 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2331039dyi; Tue, 19 Dec 2023 16:40:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHkgJ0fik8ulXbOULKF8sk/7x8WEb1KE0q/hiM7ArV16eP3cHHefHfOVH3n9XVdJqiNytU X-Received: by 2002:a17:902:b7c7:b0:1d3:bf26:fe66 with SMTP id v7-20020a170902b7c700b001d3bf26fe66mr2336675plz.1.1703032834711; Tue, 19 Dec 2023 16:40:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032834; cv=none; d=google.com; s=arc-20160816; b=XYzsK6YYuSvZChj+xbZbnHZILRRsK/2gZn5gVNNzN+4HjcrjXiTtyYQMbqerrbGxa3 GefFCW/TJ1+iLVtrxMAfjxgpFb5wphri8sdlZ5CFtas3sEqCC9thLjIKgp29CZLqc1Lp MHJYa5+pz5wv67ccbn91l0TtLYDf7lSO2Ap3kAMcBoC1o/cJi85nBoGp9Xn+ced+Hla7 tzFGqNJXm6dE1BjfvM3KVN6Z2/BJxneurpyl7s+j+32sndSQRZAW8yueAf3trSdV7QyU 2WJ9Af+z5VEQZJEaMpV/CeyhZxLbmmHVFvgl37h545NpY4fS6YVPUdTLU7PoXSZTqTXa nq4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=XlDUepmJECDPJhuprnqUu3VqOzP0g1ylAOO9+Ec40Fc=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=qGzuPGrpl5mgM+TAk+MzSlk2PsFBofFM+tonF2jFaeCjT9Xenji4auVA0KW3t0tjGd 4BHXhQ/19qnI7sQBvvEwuyZBzEnXKcYI6nBedbbjlizK1pycJcSAPuieKEm7llHPll0F 4Y53snB4Tt/J/gULiWsmtWYyLaYdtw471ovexOLz2G1y/1+QkX6KEYKf0yHB8ZAhOU+u 4BTfiiCaJk+vIq7BR4uRbLpXjTVx2vTeXUZfiDzO1DLa9CTThUp1gSr4KlDVz6axRP4C IRYdF+/6WWt+lYoS8W9xzj7bxAI29W3adbJoWbZrjxMPYTWNwxB8kfFHjZkI3ilMNhH7 S8xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yf1GFAWI; spf=pass (google.com: domain of linux-kernel+bounces-6175-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6175-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id t8-20020a1709028c8800b001d069748938si20104633plo.105.2023.12.19.16.40.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:40:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6175-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yf1GFAWI; spf=pass (google.com: domain of linux-kernel+bounces-6175-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6175-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id A8E5528AD84 for ; Wed, 20 Dec 2023 00:33:07 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F00ED13ACF; Wed, 20 Dec 2023 00:31:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yf1GFAWI" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FB39AD50 for ; Wed, 20 Dec 2023 00:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-5537114380bso2434583a12.3 for ; Tue, 19 Dec 2023 16:31:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032262; x=1703637062; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XlDUepmJECDPJhuprnqUu3VqOzP0g1ylAOO9+Ec40Fc=; b=yf1GFAWIYWWfv3GfbD/FlRWVIBtciW4Ivp4yRHqDmy4CYiampwhdNv9MLN191fvQaj AUpjTX/bVH8O16ibI1xGnQ9nZl+D9JQNtYToaSuGSCMtxlaIOjhzerBL/JPSbDVnUsjP tPYJVLMnengHVtI2OvTEiz/wK/DNey7SVFvJpYNi+QLYQ5gcw75C9OLUs78VYMZl2Vrc 5D/TAN6NCeug5KkpQbK7vnFtctzdFlUSn/gzFVRh0jMKeeedl+s/v0wIvckVh9m5PoOm K66+Lx8NcS4NaxOrb84iv9qksqDHX8FQyHHHpNaG65pddMeF0HlXYf8MBbkEbZ5w3el7 g0qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032262; x=1703637062; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XlDUepmJECDPJhuprnqUu3VqOzP0g1ylAOO9+Ec40Fc=; b=NmM2hqzf/1y1YYGUzZXNRh3Rkzr/WhBdBGQOfjB8X0pU9xEzVmLiUNbiRSvWFvSLZt D9t/hNKWZFDFaVrcIiwGNS67quAf4kcB46v9xSIZsJSz9Wl2c/Fqdn+KA4z9zHTMaqc+ H41Vm9x9FhsFPIM5khT16TxrVeklKop7QxarFgxI3ClqE8VXgxcJE2CG/gWUOgh8kOvB /UWAQIZeTB0fx8SXRx9fm9uDbzjWZsNPpIme7Bepr9lD8p2c9zJw45gcE2sHHIUaHAan s5dooafBVZKHKEHiMjwD4d2DIZFWbFvJ269qNYwZOBFJJvbWh3qOXt6aR1GhTMBNlD5R +8Dg== X-Gm-Message-State: AOJu0YxEvtgdn5qaurVJpdMwZSWu4EEMu42FDAL3Q9Qv4yNhsC3I/d8u I18SAnaMCDSZMJTGGcnyWq7leA== X-Received: by 2002:a50:cd85:0:b0:553:7678:a180 with SMTP id p5-20020a50cd85000000b005537678a180mr1805440edi.35.1703032262767; Tue, 19 Dec 2023 16:31:02 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:02 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:47 +0100 Subject: [PATCH v3 06/15] clk: qcom: gpucc-sm6115: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-6-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=2946; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=L0PymLuHyWV4Yhgl+FgHBcte5FGcWRmHBmwI88u/f0w=; b=mb+8JyTtb5GOVdQk8pqP4Zfg7CUhUtYKZkLtfhYeejKLLAAcOcm7s6pG9xGblIhwsJ9K/MH0X iNiTWbEhf80ABEvtfKI+vRmLcu91/gYcS2T2/FnYGD9eId9kL2nwh8G X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759357224604093 X-GMAIL-MSGID: 1785759357224604093 Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 33 +++------------------------------ 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index fb71c21c9a89..93a50431aef8 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -234,20 +234,6 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { }, }; -static struct clk_branch gpu_cc_ahb_clk = { - .halt_reg = 0x1078, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpu_cc_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_crc_ahb_clk = { .halt_reg = 0x107c, .halt_check = BRANCH_HALT_DELAY, @@ -336,20 +322,6 @@ static struct clk_branch gpu_cc_cxo_clk = { }, }; -static struct clk_branch gpu_cc_gx_cxo_clk = { - .halt_reg = 0x1060, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpu_cc_gx_cxo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT_SKIP, @@ -418,7 +390,6 @@ static struct gdsc gpu_gx_gdsc = { }; static struct clk_regmap *gpu_cc_sm6115_clocks[] = { - [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, @@ -426,7 +397,6 @@ static struct clk_regmap *gpu_cc_sm6115_clocks[] = { [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, @@ -488,6 +458,9 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); + qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1060); /* GPU_CC_GX_CXO_CLK */ + return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); } From patchwork Wed Dec 20 00:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181378 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328300dyi; Tue, 19 Dec 2023 16:33:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IGI+MijG9RsNmAThR9bC7eeMZaLLyRqf0DGoPDVNj81Jkutuegeesb8+zHu3dD4mTaDMGDh X-Received: by 2002:a17:907:3e1a:b0:a23:71ca:2bb4 with SMTP id hp26-20020a1709073e1a00b00a2371ca2bb4mr1627429ejc.144.1703032405736; Tue, 19 Dec 2023 16:33:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032405; cv=none; d=google.com; s=arc-20160816; b=ZDASirCFiifezK/kPwjGH6D3SckIGSFv+hqjcmcAfcMnbcUtqIf/2NtUOK5KxOnJd4 u4zOf2Li1UHKstTQRw7vB2Zq4uH1DWzuqCX73N4yrdR3GsgxpFJd0Ru8oTzG+Tt3wMuN ahsRPh0A0ymwqoUwB+prLb3EXGoICCG4UGMDE7VJ52XCVcVuwn6ZzVbtB85xJKsFi1KG GUhrOU/O0EPjYsMyGF7If3zkPSfsp2bi+TRpMpfWaEFtWb8zk0I9NYOPS1LItu/idytU Yi4AFKKrlSDseU3eYwtWJ3ulgAB0ioPYXftAM+1irVj+ErH3Yhtz+zhE/sTzkDjAQ6sX N5nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=/EYvH2o2FDAOc1jBHzE94w2pt5/T4uUYkpgbUck9NPc=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=HSMaqNM+eeVJCqzqesDQ1ZGz51XfLDkbz2TyIk/jUZBwtqXLebw1ynp9xz7WiKo+jB JUUpwTVx7X0iKn5PaCK82SZycAhhwYerXgTnkk7hrwT5w3n6PNSLso5U91pz7Nq0HqDj wFx+840UrZWa99Q8JycjNzzA0mVfbp/Yi2+6aWHI6InlTcZlanjVDX5oYnxq4Ith0RkL /XgJGyfoRqICrRUdl8k+l4Z/AxVrpeV1MeGKl4O/jop8dSZRmIyAqcmB2HFBszgIjEzb kVHPfI3hIlQmRyt2AIw0NL4tT7o8q4YEbm00TRpJn5fy1ceMpf3l0+8GQXBLwP5/D4Jr 9azg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oonyqZCl; spf=pass (google.com: domain of linux-kernel+bounces-6176-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6176-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id l3-20020a1709067d4300b00a2549daae96si781578ejp.895.2023.12.19.16.33.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:33:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6176-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oonyqZCl; spf=pass (google.com: domain of linux-kernel+bounces-6176-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6176-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 5BB101F26082 for ; Wed, 20 Dec 2023 00:33:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C7BA7156F2; Wed, 20 Dec 2023 00:31:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oonyqZCl" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E011EEAE for ; Wed, 20 Dec 2023 00:31:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2cc4029dc6eso62191791fa.1 for ; Tue, 19 Dec 2023 16:31:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032264; x=1703637064; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/EYvH2o2FDAOc1jBHzE94w2pt5/T4uUYkpgbUck9NPc=; b=oonyqZClFsw5fJPDpSiOLyOu5fqaq1YsqhkAdZ3+Alrbr3httlBzhafsb3rVKH6K1w 4sgyd2VQyWaLeGNyi0s68EGL2YR2eKg/lN0ZX+RHeEWkMfr4oi/gtKHrgDiuUQjkzivT lasryqx7VBBvbgZL85PhuA3SAPjfohBxISQrgOi5rBL/vqfspD9dnh2iVmjm8I2vTl3/ uQe6fupeEK04mIKgSEVCjiIjoU9lNkuXz634z6wfl1ketcPBHW0yg7TVUWj/78u5p55V OvNleNzCN0DHLQOZKdTz5ZXuG9pfrpYk+n2eyQwhZh15wNO4NTWtuFm2TA7d+NZVz/h5 iN2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032264; x=1703637064; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/EYvH2o2FDAOc1jBHzE94w2pt5/T4uUYkpgbUck9NPc=; b=TVnlfpn8l8s5K4MEbYvBZ/i1h3uxpv8Xf+GOT2PkAhNmrDiPQdqgQXy93QlTSwk0ey AemQs3Gq97YgRNcADTidk/MvNqkfO+fyoVQHmhLJh6HDiMwN5EzAkX2kl9Y1D6Rumy67 5t+NErYEEL8r3RS/QLHtkVtORsGqN7g2vGh0SjEZuz6XkpHRmRgd7Hl+XTXGZ/qN8fmq QwjjpViB+j6M27HWzdouQzNH9INXG2Qh1nK3ItIo0DQluFrfAfEzXU6QZVOFJbtdYNWx gIB28EeRbg4EXCe1cPeJd2+UitcjTf1HeEzj1YLCjlL6L6frAS5WkeXHqd6CyPhyVAxk KqMQ== X-Gm-Message-State: AOJu0YybeTfhx+AWrv3TmHHuSBwZEZy9YQtZjKppIl78A/ZC8VrCncwq 8jaUR1fMN6e8vvym3iOn5CAjmQ== X-Received: by 2002:a2e:be11:0:b0:2cc:7703:e3d9 with SMTP id z17-20020a2ebe11000000b002cc7703e3d9mr2121864ljq.65.1703032264598; Tue, 19 Dec 2023 16:31:04 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:04 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:48 +0100 Subject: [PATCH v3 07/15] clk: qcom: gpucc-sm6115: Add runtime PM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-7-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=2049; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wo6RqwrpI+TvZGgUHlprTgAEXXwaEB8xXAWdfaiQ80I=; b=+GHnWyX1q0y09xk4YvnrfK9G829CiNmLGzLSLcS2W4lC4JlsUUv+0/aV3oEQO8a49yvcAdhIx 1DuoxWx1HnlCN1McDBF7ux42+CX7BY6Z/8SBUyeThWJN7Ox8/mmO5RN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758907990688924 X-GMAIL-MSGID: 1785758907990688924 The GPU_CC block on SM6115 is powered by the VDD_CX rail. We need to ensure that CX is enabled to prevent unwanted power collapse and that the reference is dropped when unused so that the system can enter a firmware-managed lower power state. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index 93a50431aef8..b50979ce1cbe 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -443,10 +444,21 @@ MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); static int gpu_cc_sm6115_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -461,7 +473,10 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x1060); /* GPU_CC_GX_CXO_CLK */ - return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gpu_cc_sm6115_driver = { From patchwork Wed Dec 20 00:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181379 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328437dyi; Tue, 19 Dec 2023 16:33:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IGmzLTS6zoLrpnEer9vOjs5QXr7hz3xADOH2+n17FXRClr/XvB29wY5sFjJ6xtvAALp9mKc X-Received: by 2002:ac8:5a43:0:b0:425:4043:7656 with SMTP id o3-20020ac85a43000000b0042540437656mr26324740qta.126.1703032422677; Tue, 19 Dec 2023 16:33:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032422; cv=none; d=google.com; s=arc-20160816; b=Ui6w4Zmx5CFGd3KYrk42n5hU+cPMc/crJhEOOxdYntGOq1lCCl5kyhbuDNNsdm+8mg bNjAK39LiW7HAWr3KgMYpH07Z4HGfmJKbxKDl07ie7+Z6AK+ZnVXbGcySKQsj1f/hkTb wL2piglsJIde/1ScHnxqcCPA2hFZgAwMfMUvpn8NcCyl0rkCv7nfqGZKWIPF9DfzcasT 0bcjiPZK+KYEr3uZCHi7Rg2ih+3aKSYjCLZgOON+NFthpgJn463wYklgYzL4LldTb0// Q0fv4U9mgmeAz3FCvVWa3XTRHv/JPqKrXxCo1FgIEsvZw4h9jqdcgXO8E23404pt+jwK WG7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=e101FlBi09Aa0fgZ/hYAWKa1wn5GbLF88ALZNrPPq0M=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=DpyYaRAE23Ksm4u/1h9PRolEvqO7qK/+gLG2h3QNYo6AJC546HXveR/cc+/uYo1/sP ZHj50GnSRKJ6wBtfbkJq5OHJNgOtt+6lg+xT5uG6vMElYbV9NVNneOSM/Pm8DzJPFRXD yXsC8x/I2igu5/F6URSVs05vgGANhGSPFf7mwuPtfidqjwsJv4WC24I+SpW7Xy/ZgX5S qR+HL9AObqexmA/po08OF6tl8jzFqJCV6KTMohDWxsohLUK3hZDMrYF2vS2SLbmNXIGq T0Dg3kSJh7XDlqQ3yQS/pjuXw1iKK0XDYKaC8YzjImjHQ6JV2MRIad9m1yoTL1YedQ6f ibmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HcWo7966; spf=pass (google.com: domain of linux-kernel+bounces-6177-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6177-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id b21-20020ac87fd5000000b00425fea03c15si14027444qtk.507.2023.12.19.16.33.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:33:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6177-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HcWo7966; spf=pass (google.com: domain of linux-kernel+bounces-6177-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6177-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 695FD1C23EE2 for ; Wed, 20 Dec 2023 00:33:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA2E216430; Wed, 20 Dec 2023 00:31:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HcWo7966" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04B801173B for ; Wed, 20 Dec 2023 00:31:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5532b348d30so3846584a12.1 for ; Tue, 19 Dec 2023 16:31:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032266; x=1703637066; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=e101FlBi09Aa0fgZ/hYAWKa1wn5GbLF88ALZNrPPq0M=; b=HcWo7966EAMoKINaj9Nq+pXCFnzi4gRREvlDJ8vqq+7a4L3vEydT+cFyNLgOBZXSLT tev1OS+WXpHLc3qv0TxpOS7dkvsdweXeQyB8SP4wjpe5WWdDERgMBLXSHhvJSdkdy3PJ M4En6uNW7Mgu18fqCoQcyX+siJRIuBRGyeLQXOSSAvakjG52nIaQOTzmbnk3hARiPcEZ 1QCniQ9ffhzwIl8FDH5ImGdgV48sHu5DT7Ypditi2eHW7GDD+flHXdPQtb+bs7/+SBxX d3uWOCQwbhKx6lGAnjhkHVP6c9i9FjC7iuCPPa6whE/MpWjVXjoejPWFptJFoE9t3Hil HOMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032266; x=1703637066; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e101FlBi09Aa0fgZ/hYAWKa1wn5GbLF88ALZNrPPq0M=; b=gQs9WyaAv+P/KT7Y6jWt+ynRS1OtW9nb7B4Nkv41iWDiWywmEekfJLtxHdsDDHewkN rLQp6l4Yb+Uq2WWlIh1Op2bgcUWqqbrmTuUsjZIQ3dLGtOmQ3ZrZEzHxotqyDi0MDo/I fJclH8cOSsAMRG2sdzqNZ4bnqDXmGpeClcVaFE9t2YiPC5myC/+BmCLlZDuRNSIRwY/4 ySnqp4nOMdVcM6YDfRlOx38fOr7TxlH0sVLHZhCHza8s7uRIt/du9Wba8hrBKIBy5PBz EojgHSgNeYlO58dhCD9qVpmTsyt+G7iCdPY5nC0a+2C/tVbVfDCr966Y9lFNvUxAqlB1 VKgQ== X-Gm-Message-State: AOJu0YwlXp01woTgGymIfwmelrjblCzIORG7JKq/7JUicAmq5LNQXC5y 9X9TN/jLzavtmtX2ekFmjASZeA== X-Received: by 2002:a50:d0d6:0:b0:553:dc96:bc17 with SMTP id g22-20020a50d0d6000000b00553dc96bc17mr38334edf.59.1703032266364; Tue, 19 Dec 2023 16:31:06 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:06 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:49 +0100 Subject: [PATCH v3 08/15] clk: qcom: gcc-sm6115: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-8-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=7151; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=G0UYzD6Kpjr3rvG7p+9nU/ocbhuHa6TQaZHq/prXa6g=; b=seiibSqC1cG1AvlvQv/zc0hrJ5+QLWb5cSoxI9+61v0WvNLidAGL9K7wj61o3X0u1i/sSaDWZ OrRXh81u8CiCLeCzKk4ZWw7WCP3vLveTKIqSmHaAQtTOocRrzW+ClCI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758925824426896 X-GMAIL-MSGID: 1785758925824426896 Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 123 +++--------------------------------------- 1 file changed, 8 insertions(+), 115 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 13e521cd4259..87a2bfe222a3 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -1586,36 +1586,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2124,38 +2094,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x2b004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2215,20 +2153,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -2283,22 +2207,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2771,22 +2679,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3272,8 +3164,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -3322,20 +3212,16 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -3376,7 +3262,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, @@ -3513,6 +3398,14 @@ static int gcc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); } From patchwork Wed Dec 20 00:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181380 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328535dyi; Tue, 19 Dec 2023 16:34:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IEqUuLwCxGMfkUd5xEdS/Ig/2Bc3sBZ4xrjbltf6sfrBnMMBGTdb3z0pYcAbfMwexemB21O X-Received: by 2002:a05:6214:da5:b0:67f:3f42:cf61 with SMTP id h5-20020a0562140da500b0067f3f42cf61mr4637859qvh.59.1703032441033; Tue, 19 Dec 2023 16:34:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032441; cv=none; d=google.com; s=arc-20160816; b=fwXkeCEMNbqn7fLg7YJyXGDW1SrXKKf9EA7gJWWQr6zZutFhj8UhZGACAetWqDh+lL mz4nVEgIaFyEte5GdMlBcvRdGZcE+TTkpQuwnfQH0sZT8J5hiM8/MNDdAP4J5T4JRCdA KMYOqqNgGFLfwzT+PdShA1lco79ejSxiCO6wwMB1Mgi4o3xRAG+rMG7LfZdokEODgWnk cQbJ0cwQRMN+YrPIo5pnz7ROVeYkv+zy7dmz/fKJRdEBRd2AmrpxqHUYz2tE+yXfSo8a fScf1yS5mO3f4jDdNbCW3GzmbXKx2MRM+9G9vOdTmL3tNPIEP3Ijk7LNSMXau+peDLnd HReA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=TfCS7EJc5WZz01BXUAh+J5+ayBuQvlNbLl5dADuNIr0=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=1C0r7f+wtwmR/cDnVtL5hiKw6sQuKibUB+LI4yVQPo8NHhr+X/gqJy/TfqzaJEYi72 55hR0SHjD1CK+S2VLJJzpj9eFxpez8tmTqjxFy0Vm3yUDuBdKBwvFTCaZ1oGqHEVehtH evPJL1Ds6OopAaTnOPkSjrQk+V4FcHRrDekgDVCK8vQB0cVE20TFD9qF9MM3PcXxi1PP HBbLyaOPSdtBUFjyIwNMgcTTL73laDPE8J+3FRV5sX4UkbeHVczhobaToH7SJfpRw/1Q XWlxWyZhOQqjhqy6KivN0NJxk2aopcHhm2uXac2vutaDVczNDUjUljvJ4jQVVRBQ+0Gx AqTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pOh7AODM; spf=pass (google.com: domain of linux-kernel+bounces-6178-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6178-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id j8-20020a0cf308000000b0067f43e14a15si5854331qvl.381.2023.12.19.16.34.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:34:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6178-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pOh7AODM; spf=pass (google.com: domain of linux-kernel+bounces-6178-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6178-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id C18751C242C5 for ; Wed, 20 Dec 2023 00:34:00 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A365C1863B; Wed, 20 Dec 2023 00:31:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pOh7AODM" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3846812E48 for ; Wed, 20 Dec 2023 00:31:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-50e3901c2e2so3500308e87.0 for ; Tue, 19 Dec 2023 16:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032268; x=1703637068; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TfCS7EJc5WZz01BXUAh+J5+ayBuQvlNbLl5dADuNIr0=; b=pOh7AODMGoY42p0RN24IMurN0jDQCW+zcaLxrf8IMsQ0C4GuhEWbab2wFeW7rJjWnH IX0y4wwrifQ8bk6flhwf3g1W90lvOKV52XVbhdGZdbwZMpqCMit4uot6m8167iuR031d aEozp/thYAF8Jfs+IQkLoalB1dehgs9/WE8q8FixP++yjktPN4uoYgx4+0yaOc5KIOSf cQzUHECIRmm08jNSayPbOKlvNUnSNPaaF5zKzT34OamHst0UanQ8b5ce2jkXIfw43npl LD2ok+qWVDZppG4sdwNmR2mabn/BBJB+Ve9RmH6yleyJ5ydHlkiqtO0PQjoFc/pJCDy7 oFMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032268; x=1703637068; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfCS7EJc5WZz01BXUAh+J5+ayBuQvlNbLl5dADuNIr0=; b=o8o9iR0AFbltE2SDAFF3nWXnm6I40eUS9WQgRrMCMlgFNHRCCPopUTzHTS6elakii4 XYzzOvePNP78jC7Pj+2CLPtndmLEh45aNkGFSdC69ImmwjWqjtb4koAPXhjCyz79gIpj ABKohYhzfnQupApPQke7FeACpcGmJz61wc25b1ZANkuu7rWTwXp/fl3oREKyZG9dEVFj FBlyShDxolka7yhuIHmlHv7djMz7SQQS5rhfE6kwark60PC095KLMJbdVvNKU1MulFEB 4qEao0cBHDt5Po0VUoc69uD3Ias2zSD+fglHN6rutNGhoYP/K4nWGVkmglr0Me7yv5+Z QLFQ== X-Gm-Message-State: AOJu0YyzPnCXJoh5nnaLEtgRyhard0NDrtB0C4tXBd0uNRFPuFaZHCtH dVh2Mrvdye3Gbr6HZhKnJAW4aA== X-Received: by 2002:a05:6512:b1e:b0:50e:357b:9917 with SMTP id w30-20020a0565120b1e00b0050e357b9917mr2662783lfu.106.1703032268260; Tue, 19 Dec 2023 16:31:08 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:07 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:50 +0100 Subject: [PATCH v3 09/15] clk: qcom: gcc-sm6115: Add runtime PM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-9-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=2112; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qGB7J3P0DJtbWo81wrMojy7eEnHmPOy4px200OELZEk=; b=Bb5Fj+0i6to7ZWc6udyT+Vs2btJJfq0/XcYI/9UOInkU0QDfwgSVlOq39MQ0o6ZrG3Py/cSKc yo7S4xA7oCoAO3o5K3VlpqNhFOOKbhxHuNcpIdgRecMqRKHHMNgz82K X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758944918468764 X-GMAIL-MSGID: 1785758944918468764 The GCC block on SM6115 is powered by the VDD_CX rail. We need to ensure that CX is enabled to prevent unwanted power collapse and that the reference is dropped when unused so that the system can enter a firmware-managed lower power state. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 87a2bfe222a3..3e0a3fd09718 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -3384,14 +3385,26 @@ static int gcc_sm6115_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); - if (ret) + if (ret) { + pm_runtime_put(&pdev->dev); return ret; + } clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); @@ -3406,7 +3419,10 @@ static int gcc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ - return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gcc_sm6115_driver = { From patchwork Wed Dec 20 00:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181381 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328658dyi; Tue, 19 Dec 2023 16:34:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IFiWHfDcf32HPyBZc3Q+QrVQERii1eGaOWrxT1m87B6XOT+8b9iR9YLr2qrCAvome2SMNx9 X-Received: by 2002:a50:9b13:0:b0:553:6454:e868 with SMTP id o19-20020a509b13000000b005536454e868mr2309795edi.30.1703032460630; Tue, 19 Dec 2023 16:34:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032460; cv=none; d=google.com; s=arc-20160816; b=OQI82c9srILhXMzYblM80yf1HiDZhZMNa/pVr6M5/BLqzVLH6yQe9nnh0eltW3eHhC jyjRFYCqENUcbpveJwdYM7sDB60PObtTQskzXT9OMJYAERF4xIwZZHqMEYSmWoYEJojF JI6AnTQTApRgbjOxNDR1nXKqlxIExOmw3Eh3TK/Oo+M3+/To3Sb+su3HJZqXHC2slmZw gLgQsf0ZFiaxaGUp4S+gs6QUw1VfMiSOkCMrA8zJZkFVWLgbKqlFaAmmS8Wp3LK/1w2Z tRUCsw5qnn1jR6YQwX99GSrD99aXghUe6iL6QiSShZltMiSgkt9fg6BAYACoRb3FdhoO wfoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=6bclp0Hvt3h5T6yWsz22aXRzxu9eyz+jU/N7/vaj7d4=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=RkwLC6PjPAcE7xWd5sKCazPNOHh2Thnlpzo57lEqci/qt+quyjWKO8panGGSBtHcgN 4MgNg6rZbuNjQFliJHuqh6NOCUtJNlu+p5ufWZfvr4RWGUQ9oea2GNovWWduiSTUHyWD P+AXn5+jE8leamsZ/VQTFkbN3iK15TRi0n6W+NU9t3EEgVA99VIwxhATHyD4Z6FCJtRN O0MeUBIX5bHbGDAbI9Ri8CMG/yoP8OVuCj6M7+fg+SiKxIXxYKhMsf+Xb43MNPLZj/2M oX2YxKmKdXspUys9KVjDq0SulhjJo7hjQLag7trP9LrH2NKInKoZsVLcqI/kMHngFirE qWtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HOrV1ih9; spf=pass (google.com: domain of linux-kernel+bounces-6179-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6179-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id bt10-20020a0564020a4a00b005539994af8csi993420edb.422.2023.12.19.16.34.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:34:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6179-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HOrV1ih9; spf=pass (google.com: domain of linux-kernel+bounces-6179-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6179-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 0EDE61F26474 for ; Wed, 20 Dec 2023 00:34:20 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 596A31C6B7; Wed, 20 Dec 2023 00:31:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HOrV1ih9" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBFFF16414 for ; Wed, 20 Dec 2023 00:31:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-553338313a0so3909161a12.2 for ; Tue, 19 Dec 2023 16:31:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032270; x=1703637070; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6bclp0Hvt3h5T6yWsz22aXRzxu9eyz+jU/N7/vaj7d4=; b=HOrV1ih920hs+lc1g/KLk5vzGaGILEgZRiioos5lhsUK2Ola9xdTTe9cbq3uIamki0 1GeG5mu2o9tFuYHVtWujVeJElLPPobFVtaxFYn5bRyVO8SesfRksx59rrds7mufEuFfo TmWWUbfwyfI+qiDajdxm4n5DekDyVFoqlqfgHxw1j9Cdx20yo5lLohTHDlj5kgs0lfkO Tyv3SrUcJgcsEKd6UKqT3h4BE0akM+nGJ01ZX2sqxKVj8AYO8YhBN4ymZT+aewjqiMJX rFcc+0OszaFX8MOjyeGUsVv5JfVmV5qjt+PeT2TqqePKH2AISqFEzx7gIViK4AgCxEmq +J1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032270; x=1703637070; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6bclp0Hvt3h5T6yWsz22aXRzxu9eyz+jU/N7/vaj7d4=; b=uQIKlqJqZIV3Cdvq6YpVC1MuY/jzNYpj02wNbIM5YOSQ321EKeoRSK2w7IYy5yCYZv dEYqu1Ja5YIFKHlb7kzcrGqYr0V5sdxV3Ffz4xm7y55VR0A36SIBFNT4Lrng/7w+IeGk 7pY2+AwzjZzHiI1yWbbyCA/82ji7FnQDteVG4yHBZrbQqgb61z2YQZiu0YpAC8Xlc/gq 1Mu/UO1ZHvpa5n3nMN52h6sDAY0viT4FqqIjPE/rY6u6oAeKD/CeKNxZSQ8kNBNKWVrY 80JisTuOutXh6LVa2WgTpm50YkIfgVn8MG3x7mPeAse7w/hn/kR7TQ08dCaWtDL3OJO5 Bzvg== X-Gm-Message-State: AOJu0YzPQhw9FIoludZ6uBPmyVckjEv0gcieXEPQ1/+l57sX5NYIH6Lu W/qszFdLRbzehpZ30ZX9gBuhFQ== X-Received: by 2002:a50:8adc:0:b0:552:886a:3c58 with SMTP id k28-20020a508adc000000b00552886a3c58mr4887428edk.73.1703032270117; Tue, 19 Dec 2023 16:31:10 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:09 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:51 +0100 Subject: [PATCH v3 10/15] clk: qcom: gcc-qcm2290: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-10-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=6677; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nn0LC7H4vb9zFC8A4lyuYszLgrYiCKJo2IvSN0ROhzw=; b=Ek+4z9CBWYjxS5aglhvTpTdOJZUzEqGbA4dJEy3JlxFEMh+eIZwe2MIoFa37z620amo4lrZnC hYHoxmUqRATDcy8e5Z1x9wc3acGPLVFEUoHwT+uNb4cIavcIXLtq+8l X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785758965137977839 X-GMAIL-MSGID: 1785758965137977839 Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 105 +++-------------------------------------- 1 file changed, 7 insertions(+), 98 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 48995e50c6bd..cc1dd5fc6d32 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2439,22 +2363,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { .halt_reg = 0x1a080, .halt_check = BRANCH_HALT, @@ -2774,8 +2682,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -2816,19 +2722,16 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -2869,7 +2772,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, @@ -2994,6 +2896,13 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); } From patchwork Wed Dec 20 00:30:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181389 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2332360dyi; Tue, 19 Dec 2023 16:44:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4LAXKZZ554K+yGcnR5mAQ2ClCjIv+mp9xFIBKVyJNmGxWtw/iZPFArJ9L/nXl3bCA6GTy X-Received: by 2002:a05:6e02:174d:b0:35f:7df4:ceac with SMTP id y13-20020a056e02174d00b0035f7df4ceacmr4603628ill.13.1703033074865; Tue, 19 Dec 2023 16:44:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703033074; cv=none; d=google.com; s=arc-20160816; b=zPZg7/6fp9qFvSNYa27jH9atITr9ieXhgWhs13lGrq5kMOQilOftUXAV8kl6NY6w/G KN0gCR8Lk/dnw0Z9y8B/6GVm+D/+8DM2M67UCgr8darrwNDw8CAxIJ5ccwHqZb5S4u08 iLuhjUMBZz6UBf3oKp/diGoxAXwa1ZvYM0SgRiefeWk8VdFlZENKqU7JCbqgyaslb1L7 PLBVUnVFKmiazLWeMkgqGN/e1VOQGECUUKBeMkVX7n+HxQ/ChK3nCrPNrszKJvgEfS4Z EvZDtzArceT6QRoENj7xLTnoQEDfAwbeTkjKePfIu+EsAtzs7NxIz2/zEH4dZBM4rKu9 N7xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=iL7/cJ6kElWHnhbek3aTb1dfvRVji6nGvSY/NIw03Sk=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=Fb8qeLLMg9zuATh7n3aXunPAPybxS8ehoyXgGiuV4SYOzCyCrQfNiQGn0AvaZb/C3f KIJoaK0HXu7LU1CgGK3S3Q9nT7T/adzzG4kp7uNXT/1Mad6SyZilx8bom8xDj/Tk/Bg+ dqADGaO4L7sggLfMVUstgjTWCpgqWFibmBlPhuicTS3NsYXczfmU/VomUbGAqMJT27tL 2z3VvkqR0+roo98Y+6E7aT38nbTwCJnf7sPA1rfyKqv2pfAzOsHOKSNnp+VfrfBSFF1I heQQKygW6HtpzwvBMC7hGXLxhh3Sn9+eHG1rXeH2hnK3rbsaOjrj/tUEDmAKOq62fTKz /f3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CGjLZn8R; spf=pass (google.com: domain of linux-kernel+bounces-6180-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6180-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id iw2-20020a170903044200b001d3ebfb1ff4si530415plb.2.2023.12.19.16.44.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:44:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6180-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CGjLZn8R; spf=pass (google.com: domain of linux-kernel+bounces-6180-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6180-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id C3E4428C117 for ; Wed, 20 Dec 2023 00:34:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA0D91CF88; Wed, 20 Dec 2023 00:31:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CGjLZn8R" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B4621173B for ; Wed, 20 Dec 2023 00:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2cc4029dc6eso62192681fa.1 for ; Tue, 19 Dec 2023 16:31:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032272; x=1703637072; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=iL7/cJ6kElWHnhbek3aTb1dfvRVji6nGvSY/NIw03Sk=; b=CGjLZn8RQSJNX0wsXcyRFOEoQWWLUmHI16Ise7axkkdwuILSywsDyRWFBIi4hGAi1f WZq503A2jdRA5PslAJWhVArYVGgoFDSJgwb0wVXP6f0OR4edZYYaIfx4ZdsTjsnJFGrw Kycjd95M3zrpcc+gasvkUrU4Nlum3/GHkQ073VXbbgsv2vrACzd5O1jid0GwXPAJT0dC nkv5e2F72aLSCkPU/2ywvupJc/uk3a25u2nU6Ql1LgZyuQEisOJtQ5MuuHCSpHVRF/lR 3TmnkoGwTJZo+84nSImenaHgCWbWBpILkjcEMpfjQuvKn0gS7nT5ey8QNOGUFphuu3SA UZWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032272; x=1703637072; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iL7/cJ6kElWHnhbek3aTb1dfvRVji6nGvSY/NIw03Sk=; b=bi7YgBpvqEcBYsylZDWEN7AFzi+0lMsnXY8b1qVuPXfcuyekac7ugxwRM4o/y79lKo K+VokQxnsg1499aKnNS7RABrpBG195u/g/K7OR2OUN/UmoOJ8k+j1UtNfJ4ybLM+7TVG O1EaKxpsNtk/EqQ8W2YrCg0V9MNUkuUS8OxSQtlg7tyXB+I2gGZ8OzhDS5qo/DfpmIb/ y2MFnJ47g6POsJDK7masc6f1JoDIRDkz7RIusFppDTJvuSF80XFC/JXIyxvFdZlf/Nv+ sZPf6eqJPD7HwRfuO899SMS7lgo8poLwkaFlMi9LHnMpIDhfUrecEeegqK6wSKLM6ZHD xGsg== X-Gm-Message-State: AOJu0YxGJ+oRnSf/dkArEkR/cCVNTwDPNaDp3Kv6PgWA33rsRwbphjMD rmrgMBs+Ce4d5PjCBXDt6ejXGg== X-Received: by 2002:a2e:a685:0:b0:2cc:69a6:a49d with SMTP id q5-20020a2ea685000000b002cc69a6a49dmr2060217lje.78.1703032271806; Tue, 19 Dec 2023 16:31:11 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:11 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:52 +0100 Subject: [PATCH v3 11/15] clk: qcom: gcc-qcm2290: Add runtime PM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-11-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=2146; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Am9uKVZmtmU4RslmGcqWt7Und9xViAlu8ssTW3WECb8=; b=P9NWhqhoMKb6ser2xFt0lQBZ+Aao5an5mJaPk9VN2bm2Vgn4In7Yny97kQ5t3WtDW3KF0/L9C 6cCVEJalfIOCb0A+pg1Lcax4vvhqXAGO0sSBAOE5NiQxXAg9VCtEkqc X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759609843355368 X-GMAIL-MSGID: 1785759609843355368 The GCC block on QCM2290 is powered by the VDD_CX rail. We need to ensure that CX is enabled to prevent unwanted power collapse and that the reference is dropped when unused so that the system can enter a firmware-managed lower power state. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index cc1dd5fc6d32..0992da84a741 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -2882,14 +2883,26 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); - if (ret) + if (ret) { + pm_runtime_put(&pdev->dev); return ret; + } clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); @@ -2903,7 +2916,10 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ - return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gcc_qcm2290_driver = { From patchwork Wed Dec 20 00:30:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181382 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328911dyi; Tue, 19 Dec 2023 16:35:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IHgiOrqlW6wSUSZyzqg68EvljkzK3ql6V/+8J1yKYXvgMQuJUhe3j6h0sz9rG29cY3v8I1k X-Received: by 2002:a05:620a:1924:b0:781:42d:69e with SMTP id bj36-20020a05620a192400b00781042d069emr2116969qkb.107.1703032502396; Tue, 19 Dec 2023 16:35:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032502; cv=none; d=google.com; s=arc-20160816; b=VEL7+Wc54HmvttFoAF1hx3wnwkIca8vXOtM47M78nPE0/DaDcjhSu6lEFmWvq2ADWH j3A8kR2WJCGGdzegndEDsF7XdZYagOOCnh6SZxVb1YQvn/erpP04VLJEBarsBUsjvsMJ wRIsE3XhSJAhKLo8Sb29KANKKKcbIOHwTksU6tpIzA77HZ8rdnG00C+htaP4ACXyY4g+ BZr43Kylcof2WsgfoDvk54PG9kHpme5/oRULng5u84v7RDyh1mf9qTx1JmVL4Yeq1vFA yDCA8eN+hAd16oyK00U+v/C0U0u2LG0l0WIo08HcOkyGwrKM5hLS1aQL8JzFHqHXND8y F5hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=+ls2aUMbVxdc/7lozE+p30ZeM7lcweE8oneLXZx5wYg=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=c1Mof6grAubgqKc907ty9Cf4PCDeO5bA5+QwFHjAwdWjRkHpKj092i61I7OxCwyIBD DOrXQu0V7j30J2TMAmOoAvxIk1mZLJ/KOUvicEabLjwI+GYO2Oe5eB/MkyinbL+yVqEw F2ez77ExqjfyxE1bPGX7jU9CUwwhI37bMV83dZcdufV/THabv9T9WlkN8V/N4hBmMBik ffSu4GLOtouQ0eP6iG7C1eTjuFNJWn9j5CZKZQEcJWSUcflaOIsl4HAii41jSPGRZ4Zw ZC6nOrb+jpiJ4T2FAvttXcdo4WZf/dxGYZOVOoesSExPcQQmgifzAU+aFxa3nNQEUG1b nGcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t+YI46tT; spf=pass (google.com: domain of linux-kernel+bounces-6181-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6181-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id i3-20020a05620a404300b0077f075a6016si29162616qko.290.2023.12.19.16.35.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:35:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6181-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t+YI46tT; spf=pass (google.com: domain of linux-kernel+bounces-6181-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6181-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 1E6441C213BC for ; Wed, 20 Dec 2023 00:35:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BFB451F606; Wed, 20 Dec 2023 00:31:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="t+YI46tT" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 887251A70A for ; Wed, 20 Dec 2023 00:31:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-lj1-f173.google.com with SMTP id 38308e7fff4ca-2cc843af59fso14790431fa.0 for ; Tue, 19 Dec 2023 16:31:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032273; x=1703637073; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+ls2aUMbVxdc/7lozE+p30ZeM7lcweE8oneLXZx5wYg=; b=t+YI46tTHIYcgwERFwMKxuTeA/QmRqxFcLYCbn2OeMPG/Pt7RkQvbgRdTw2ueOulIj wrnUVfgQVt+IEcks04QWUWcnuFkKNCzXS41ihHZY2VlBaLRacr86YB5mHS4kxZqGYKrp Lhszni+G27qR+jGQeA4BQEyhe/JPF8FaLglduymoX517qyxUrq91VDD5NCJKUQNka5/m KR9OKyqWyjx+ACdx8uaCNUTzqlYtH4esYqQLnXz+q6xOSMv/8nKKz5H+QwfoNt5AfGQl ZC/McPW9admSmCBbwpMsXCq+G757WpMED6QvPyLja+QGWei7yRBbU/rc00YqC3OpE/kG PTGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032273; x=1703637073; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+ls2aUMbVxdc/7lozE+p30ZeM7lcweE8oneLXZx5wYg=; b=Wax71MMMbHB0sUIGB/B8kb+6M505Mv6e+8lWr4Yq7Bl6eAzsuCdwc+1JXcAB+MA40w hJSfuOt9Jxkn0IxcTxvkF5iN81R47mX/08RiyWsB0Nnh2CR95V4pkVnTacDw+sHrr+z/ 4ihtgJWMXqbBGCPWxm8rTeLwXWbfCvW6VfcML5V24EGOSZNVyW1TkwHd+3srVjHnwMs0 4TA5WrK+C+iyoiusYwEqlyKPNfu8s40WrF7Og9bW2CLHtOWo6NqwljIzO6dTkWXUdP97 iH+EvZTHfDSZwB8x2ZaMSDUuKu2bLzKT/0nPGaeB+kpAgk0Move3CBEuAw0f2WhC3lqd zpnQ== X-Gm-Message-State: AOJu0YzV1iwYGiEaT0uYMatIDoCTlnXKDk959LsGWWmXhmTtzPArAiOT sKm6uB1rpfZSIBguzfofH5d0Qg== X-Received: by 2002:a2e:300e:0:b0:2cc:7b78:a4b9 with SMTP id w14-20020a2e300e000000b002cc7b78a4b9mr1298603ljw.1.1703032273686; Tue, 19 Dec 2023 16:31:13 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:13 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:53 +0100 Subject: [PATCH v3 12/15] arm64: dts: qcom: sm6375: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-12-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=718; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Gc/yH23ZENvzGFFViZ7/qVCV3FeiRMp+LehbPO3k6Xw=; b=LpPP3sYjj29DdeD2Vc6CdLOLcwYNezXrAnQZUt5BWyEjmp2mTGBc7njoOaySLt1N2SXJq5YV0 lfl88WAVSTwCh79WLhi3C4+SqgGLOo4sYa6Bkgg2kBksp2aCurg9l2D X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759009351771101 X-GMAIL-MSGID: 1785759009351771101 The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 7ac8bf26dda3..f578d110f36b 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -954,6 +954,7 @@ gcc: clock-controller@1400000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&sleep_clk>; + power-domains = <&rpmpd SM6375_VDDCX>; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Wed Dec 20 00:30:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181383 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2328993dyi; Tue, 19 Dec 2023 16:35:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IHQGRp6HSPBfcOq6JvnttpPUwto3mPxcSohQrelcpFIUTX346f3wqXUF8aFeR5UfECd33SY X-Received: by 2002:ae9:e115:0:b0:780:dddb:3220 with SMTP id g21-20020ae9e115000000b00780dddb3220mr6376770qkm.98.1703032514521; Tue, 19 Dec 2023 16:35:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032514; cv=none; d=google.com; s=arc-20160816; b=lZVjnJJyJ222wNf1RxvyDd2duRRVkLeQSy8NHQKmIdhdgb0P+s51LUU4EXUoTskzTh PEfZjcPtUtp8fmpThuIWQ3bqMXo6UyEb6c0iLWqd+cuZDmrH6qu32U7TmkkIrSI00fjo pZhn5EET6BQblJy1PxZp8Q16coClq2Dy+UBOqVgDf6dkwBmrUJeIbgvjrGlE3cmCaIU2 6Mc8YNXDhcXr7KN5/BzHT3bqq0I1sLcM2di80xQHLpTlwITG5uuecmGo7XRaOVNraZ1c DjaTRfVroUjP5AvzCn5cmif1Sn45VS1JAGh9N8gI/hCEKzAOlaLfRVdgLc36qZXln0Xm TiSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=l45e00PPUqZROMVNvs1HtSMIFJudE2l3Yzj9MkIdw95otqpLeLhnXW6U+8dtfvwkiN fAo+5XbGw6Jjer2F06o3lOLYwiYe7EeEUyg2ow8FVQuBJdTELVwj3HmPjTYo0VxuZmAb koQcNgWbpYt8W1zpJryTa7dJUcSWPZ5qpjugsR8AdHO59Yl5ECO20r7MCxRostWTh1jF oQndTKO7HoKALqTQQHIY3yVvHm+924gWiQyMx7u1wqLpsjv/LT4cG1COvavqc38Mo7i2 ZQ5c20tU5odUA2ErsuIYZ8pbQgtT4m2z9MQUX9o0EDPagEgh2e4dEUkLM/lbs2fokBeA FpAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RqFzXxY/"; spf=pass (google.com: domain of linux-kernel+bounces-6182-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6182-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id i3-20020a05620a404300b0077f075a6016si29162616qko.290.2023.12.19.16.35.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:35:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6182-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RqFzXxY/"; spf=pass (google.com: domain of linux-kernel+bounces-6182-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6182-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 529401C2403C for ; Wed, 20 Dec 2023 00:35:14 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C042B1E532; Wed, 20 Dec 2023 00:31:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RqFzXxY/" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5789C18057 for ; Wed, 20 Dec 2023 00:31:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-55359dc0290so431357a12.1 for ; Tue, 19 Dec 2023 16:31:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032275; x=1703637075; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; b=RqFzXxY/wPPJxiHgcUVivBBigZA3EB47UMHhvqEsCvzclTty6KzPzkgKwbU6zkqyWu 8H2NQe8aFe/HLy+lXFNb8xKW5TLCFA+Mm7K3pogOR0nBzJo43MiPirSrihT+AW/RU6ew 1mGEkAx2DOkJQXCbPcRePrvMuG167iQP9FXQDIDB8p7iB8ZAa2gWvVnF220AV09U4ltR tUBm7wn79f9QEYUAbXMlIY5NG3hIgsWJarqeNlmJnjh6jj+RjyycSEkyBEXz3YKorlKA sifvr684yZWsCB2Gu9uKjzDEp51ycwERcb25wFkgSoldDUBaBaXeGQRNbSXeHBBqZBI1 kf+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032275; x=1703637075; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; b=NYBtNo/puv/0xBYA/aav0g3BtneFcRGnKvLeFdRxfSQ2+AYRK8KB2QW7kb6a6EsMiy c5b7cJW9OWOpK/r0qV8WBfAXF3DaewE4ZwYQU1RSZ6ocuhuB9Dl7xl46cQtw/5Mny4ww P8ng3SUrCuqgWSwr3o9w9yKAdD9uo+47zkDxnhbC3KQk6f8LxofS5fjs5ACrkH7sVDXn DlEdynjKab/dp+GkUlPQYtGdIfpByTYSu0SCMCn82dyq1BMpF/NfKAuSAfW5iwczUo8z a877IXjYvlV3jXQIioxyVTqc2iFVqBNfCtHgVKKKwOBwQRYGgnVFZFsXnK7GelAFhHqf KxXw== X-Gm-Message-State: AOJu0Ywnen96UODkj45aorLyFIGBA6lWsoR8MfMz/kNbX3crWD4hD1e6 9cyTyU78bNUusfvdXt37WS5DRA== X-Received: by 2002:a50:d642:0:b0:551:7f2d:3e43 with SMTP id c2-20020a50d642000000b005517f2d3e43mr2258589edj.33.1703032275565; Tue, 19 Dec 2023 16:31:15 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:15 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:54 +0100 Subject: [PATCH v3 13/15] arm64: dts: qcom: qcm2290: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-13-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=764; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HEE3DdJ4zQzS/Foajh/2RBi9l8ssp2UwDgoH6XqPOSE=; b=6NYp0Uia0eNpkvRteI9GLnVVoBVz7CvNC7YCpuwUsc6QPev7ctbyBxJgygdRVubp6bsfC8Bcn 9HK1GmtGkNBDolETOVT4YFfY9hHCAEq+LEfzn3OgM8OPhGCqj0qz4fo X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759021679093425 X-GMAIL-MSGID: 1785759021679093425 The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 0911fb08ed63..51b05019ee25 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -647,6 +647,7 @@ gcc: clock-controller@1400000 { reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; + power-domains = <&rpmpd QCM2290_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Wed Dec 20 00:30:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181384 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2329121dyi; Tue, 19 Dec 2023 16:35:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IEPkEaMZedBoqPcAfrgakr99FuwLKAeFjP9d9+OtjQ1/PMcLGZQ38E4kUpilcm6Kc+JJkvZ X-Received: by 2002:a50:d5dd:0:b0:553:6730:9825 with SMTP id g29-20020a50d5dd000000b0055367309825mr2249629edj.55.1703032529955; Tue, 19 Dec 2023 16:35:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032529; cv=none; d=google.com; s=arc-20160816; b=yO4Q3OJi0A+sRUH1BKDRqb0alnSnVF+6CRx/Ut/wwTrBzHbMwMpPzbm5UA1MV+wsM0 JiN9nMjKhZmVAYmFiZFa80PX5qFPsbi2nMb4Qo1rMMZ0tX3bXmQKnEamQPrTmDromGq/ toGIOBUQ+BxnhmWqeVhPnscJuq5cGpNSBZgfGc27sZhFQfewDzAWMDK3qbOq+qQz0DyH pncoizLa10TcvbtgLad+9iJSSzRoXTeD6v9mlnt0rYGQW8FzkU9l+zwbqdtDDgShQnon TPu7h/nTVJtI2p2sml7zL85bXPvHVV+FI3DjWBUEzr+RJelGQG0yvt7Vbb4xJjozkzIy vbTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=MVGJ8KUsNOlQCxYrOkJEsHtZzCikRGcLUC4KONOaYAkQR2ZUo1fPgJlBZ2kyIRA6cL J69NKIZJnS73PpAwecXSmJ6WxSRF+HeEbKbiP862YKRnybZF1PTgmRyi8wzzEgxMNiSm 6ukr/BlSg8ltmqti/O4jB5t5QhN+dwVTTvQvmFou2vF41m4VJaqjTQM7QBS2EyARswGn il6J5j8HVaQV5iVEyuJ6/Vw5QyXQ3o1OOyexfZa+vdgXes7TXY+mvqFZzGIJqZp0bAqd yEUDt34SEcOX6ohod/BpcXdkkHM39WiGme1H3QPVkbgDp02cTlmbOqmV+d6ud8E//fKH pxJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OdQp7ptY; spf=pass (google.com: domain of linux-kernel+bounces-6183-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6183-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id a10-20020a50c30a000000b00553df1ed009si16096edb.266.2023.12.19.16.35.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:35:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6183-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OdQp7ptY; spf=pass (google.com: domain of linux-kernel+bounces-6183-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6183-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 938D91F26249 for ; Wed, 20 Dec 2023 00:35:29 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D20C61D6BD; Wed, 20 Dec 2023 00:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OdQp7ptY" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BE441D550 for ; Wed, 20 Dec 2023 00:31:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-553dc379809so64785a12.0 for ; Tue, 19 Dec 2023 16:31:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032277; x=1703637077; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; b=OdQp7ptYBoFXdEYO8iACLB9wjDGEJ9/mj6iGtNUBCHpa8MnxDLVHKTrixvaneHb3eR S3FmUe67eEWLndkka7YOV49sV+JA66OLTsiC9TEAj+y59k97IhqDbUzJLJfXxUmTqzKA VpPtva3dbbmeINkszvboH8403w2AAGuDUvA2d++yfaJ+caLtC7lgEw7CFuTlun+yqKj1 McuxkdJGUryA0y/PmrABLChc4LEUGJH68ZrmXWY7AZKhBDFgut11Jk1WhNNfOpy3wmpW V0BuqJfb6jUNne6bx2eLLowD+6CVX/vB4DE2928aiiZ5Lx5X351yvFFVm8Ek8XYwkmCi Jd7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032277; x=1703637077; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; b=Nz01dh+gdpsTZUJ9enrCkIuQjHFcKtVktYm8JKfNHIXxDkgLQcxq6sVc0Eo+fvb/r8 uP20vQfYbMFVeLQ/w6kIUX3eguyEog12pqcM3V9qEEhx+/GnHlIyg/E5lUAsWOAcChi5 Zit3dSI/HkVdpw+K2Za6gOAJwr0rO1lKu2y+GA8q2c48G0n1NDujFXS1OmvjlhjflKsO 0yeO+yYOeI5dtCz12t6QF1wJeLW2VM8iUfcY+rbjsqiLVGu1duaTdLAWA68l/u+uEeSP AZSkYEdM9BXTtZkWBf9tR47C/G0EF5whpnahVSIFCjeZXihEe63Vr77/dxMYh5BriUu/ 2ZUw== X-Gm-Message-State: AOJu0YxolKKRzAqLfzfIGsRv8M0yx4D1iwyXJJHwY0lxkx5y3U3XNoR+ tr81W1VjB2zfRm5oYPcreVmmXg== X-Received: by 2002:a50:f614:0:b0:553:dc26:caad with SMTP id c20-20020a50f614000000b00553dc26caadmr53566edn.67.1703032277109; Tue, 19 Dec 2023 16:31:17 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:16 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:55 +0100 Subject: [PATCH v3 14/15] arm64: dts: qcom: sm6115: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-14-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=758; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=L7WLthXykOxwSCjhfTNvX8JtR2g4GIz2oFPri6fp1uU=; b=THQoigRdGBzYP00XEQB2h4Z7qY2lWscNTp12Po50hbFNwGrviRM2Vxc8MOfXTChWY4Hj2yU3A OSmZF8tnl0VB+j95gq8aAJ9ziCCIGib6PapAY1c2GO3X0CL0qYGGPU/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759038343336225 X-GMAIL-MSGID: 1785759038343336225 The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 160e098f1075..30b140e1cec0 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -807,6 +807,7 @@ gcc: clock-controller@1400000 { reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; + power-domains = <&rpmpd SM6115_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Wed Dec 20 00:30:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 181385 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:24d3:b0:fb:cd0c:d3e with SMTP id r19csp2329192dyi; Tue, 19 Dec 2023 16:35:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHeOirePewUv4sipxfCHUdAr41SC4NqbfKYyl+ruJKvvVhqCq9s7/0KGpBfs7ynNJW+qji5 X-Received: by 2002:a05:6214:234f:b0:67f:48e0:6729 with SMTP id hu15-20020a056214234f00b0067f48e06729mr2542389qvb.5.1703032538991; Tue, 19 Dec 2023 16:35:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703032538; cv=none; d=google.com; s=arc-20160816; b=DWuTB+7Z5aN4C/SHKUR4jTWVvEVIGg2IWcZG/83e1os+LNb92GLYs6XAS7ZPiBHk+7 Nb8UKWUXo+Hs+pzsc5J4fdmbFhaLIeCU0vNWS89j5rSU0Fz09nxC6ZGtudUEVCdW0yeC swJxmeAWNF5tYIq8UFS3O9Z2MNOFH+hDqbkbk9Yik6Y++BZKd+hMpMnDgovBvPtpqExD nmiufVjYNYTjFfeTtXpMbFFg175GBzMOVi6AvFaCg7n/o6S3Eq2fPBbC6ZXDTOQR7CnO TahY1op+iGmngoeoVnsQkX5H/c/GUmkIcj5iecOu/9U6cQtmaFaqmdrFTF3Y0fTC+yg5 WTuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=wkeMDuhSg0OYvHBo+TBapzWCn/S4wNQp7wsa/qSzLELEBuE1nKTKOt6Rcy98UfmErl CuTYLyP8KepnmrVffum6lwPldytN9m6/OVNtZiMEl7AZKAFRNn7Rl7y9SUsP0LDXLOQf OQhwsHi8nj/01RV2n6MH0WjnwtfheeK9fy37h1C7kH7mOmbnvV799aP0hzINOSU4oBsD R7emIWJeSDF4LTPuc2AAwNtidkRxH03DcHKqigUMVAuRfHv+dQuWmDgGVIORCu18xoId 5/Y0IhG5rY7b+PImSv612wzFA3CrQJfu6Pv73hwac+O3H5xofI9XcUrGUC2AqIHOo6C7 i/HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iTCXYW+0; spf=pass (google.com: domain of linux-kernel+bounces-6184-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6184-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id v8-20020a0c9c08000000b0067f67e0da7dsi1223770qve.228.2023.12.19.16.35.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:35:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6184-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iTCXYW+0; spf=pass (google.com: domain of linux-kernel+bounces-6184-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6184-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id C26141C20B19 for ; Wed, 20 Dec 2023 00:35:38 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6ACE4208C4; Wed, 20 Dec 2023 00:31:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="iTCXYW+0" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBCF31DFF5 for ; Wed, 20 Dec 2023 00:31:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-54c79968ffbso5746551a12.3 for ; Tue, 19 Dec 2023 16:31:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703032278; x=1703637078; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; b=iTCXYW+0i4eAV4hQMqN8RjcSA8GqX456kr4QuNfj5Nw+u64ZpB7AcmrxkttHTjOF47 2foLCdke94OoieAbCN2kfMrpj0QE2xpwe9iGTS1jZrQzVRaDXKQTMqxgy6KqRuhJfz8+ mQBDGG65XvpXcDwe4LEdcx4J2CXab8LOTLS11Zj0ugqAnTHSKMilFzSeF2hFl9eEkemV IFpgO/RJ/T5/JEhkaypQ6hwAXqqhRgVvHcJjWWwZp9/NxtEay1M6L5BIgwwExaZhQ+uy WIthHiIHJHtnvyvmbG6RoputmEXyQ5XidEBdYVkSl9S8IyYvjW58JG9h6fGHB+cl2gy1 Tw/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703032278; x=1703637078; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; b=JxauC9q7uq8tq5w2qsvop4BdP8qqVtl5iDOiUzPW5POSeuK9hC8tQjt0Pl9nEB+pyX CB5O8q+Evnps6G3FNj+pFNTTb4x0vdBXvCtCq6pJyjSuireJmTugJU5HVX3h8+/RTmzo N9T7fyOtmKUsX/TfYoSCq3U2vi8/w6+Jr6OeN/ljCKCl1DExlshF4DbT8VlngoYXfAHM oMc8FvKitFXNaIzq+6IAiGKpbqugJZiQ37/Xw5AJa1hw9FIbT4D05x0B6QQinX3+aVwn 2oHC/3L2aiWbpKkjZN3/E/QxyDQxQXEnor3GLBMWut8rN79mM5IvzzXJICYU1JjB2xeJ BO5g== X-Gm-Message-State: AOJu0YySLr+RAoWXHGjvwq3gVQ+eVRAJAh4krlqoTxX2ENuS5xAcXxX0 GAG6SrwLMLCSN3FONq8G82gUjQ== X-Received: by 2002:a50:cdcf:0:b0:553:d641:a662 with SMTP id h15-20020a50cdcf000000b00553d641a662mr105787edj.16.1703032278403; Tue, 19 Dec 2023 16:31:18 -0800 (PST) Received: from [10.167.154.1] (178235179206.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.206]) by smtp.gmail.com with ESMTPSA id k16-20020a056402049000b00552d03a17acsm4824397edv.61.2023.12.19.16.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 16:31:18 -0800 (PST) From: Konrad Dybcio Date: Wed, 20 Dec 2023 01:30:56 +0100 Subject: [PATCH v3 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v3-15-3e31bce9c626@linaro.org> References: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v3-0-3e31bce9c626@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703032250; l=911; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WDI26IliceRlW0YgN7X8GrPWGyVd7988pOYar0kAAss=; b=JT9map2Vij7kDkB2GHwlcrRA/PgAQ2Y58vBqJjsCY549ds81i1UK9SvzTpVTsS1KT9mklzCaf C2VYQCp2xkQA0O+Oq6whvZJzd0wz8PLykLRWLo0Ox6UIb6ceFDlhwRP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785759047366641072 X-GMAIL-MSGID: 1785759047366641072 The GPU_CC block is powered by VDD_CX. Link the power domain and provide a reasonable minimum vote (lowest available on the platform) to ensure the registers within are accessible. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 30b140e1cec0..ec9a74acc69c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1723,6 +1723,8 @@ gpucc: clock-controller@5990000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd SM6115_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;