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[2620:137:e000::1:20]) by mx.google.com with ESMTP id la26-20020a170907781a00b007aa493b067asi1759902ejc.396.2022.11.11.08.18.44; Fri, 11 Nov 2022 08:19:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=TV4jxhCr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233829AbiKKQLT (ORCPT + 99 others); Fri, 11 Nov 2022 11:11:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232983AbiKKQLL (ORCPT ); Fri, 11 Nov 2022 11:11:11 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E47FF5B2; Fri, 11 Nov 2022 08:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668183069; x=1699719069; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p+KilnQz2eoX972sfrdoTz59qjsRam5nejXgBaHGa1s=; b=TV4jxhCrvW9lN6wEdUR7IUSFMR3RZiLaQNymkb1H1xAA+UKIYrncVow6 duOiIjMYHlYjZjn0juyPWUYNLd2mZ6/083vPD6ifAGJprz0HoCE8QCPXu 8HxmzFPVtFCSs43DrCyVtOSWIgFts3Hfj4nNSm6cET0XXQ2M7dnOjzW0+ VVupGv8YR9w9r5aw5k9QQZM8XLw6xgaPlV1m1doIzuiglC6qoc1JX18jJ Kxh3U1B5Z9dYpRbiQhazZLEGbJLq6SnBYsyLv9kAdfmcEDyIvgDR20ntB xQrOPhxgLOdv0SVvOi27vYwh+EgcqkmpWgkZ5vLp5DK/vDPBSJph82qeF g==; X-IronPort-AV: E=Sophos;i="5.96,156,1665471600"; d="scan'208";a="183132896" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Nov 2022 09:11:08 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 11 Nov 2022 09:11:08 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 11 Nov 2022 09:11:02 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v4 tty-next 1/3] 8250: microchip: pci1xxxx: Add driver for quad-uart support. Date: Fri, 11 Nov 2022 21:41:28 +0530 Message-ID: <20221111161130.2043882-2-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111161130.2043882-1-kumaravel.thiagarajan@microchip.com> References: <20221111161130.2043882-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749217232395908711?= X-GMAIL-MSGID: =?utf-8?q?1749217232395908711?= pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. Quad-uart is one of the functions in the multi-function endpoint. This driver loads for the quad-uart and enumerates single or multiple instances of uart based on the PCIe subsystem device ID. Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v4: - Renamed pci_setup_port to serial8250_pci_serial_port - Added Copyright information to 8250_pcilib.c Changes in v3: - Used NSEC_PER_SEC, HZ_PER_MHZ, FIELD_PREP, FIELD_GET MACROs wherever necessary - Handled failure case of serial8250_register_8250_port properly - Moved pci_setup_port to 8250_pcilib.c Changes in v2: - Use only the 62.5 MHz for baud clock. - Define custom implementation for get_divisor and set_divisor. - Use BOTHER instead of UPF_SPD_CUST for non standard baud rates (untested). - Correct indentation in clock divisor computation. - Remove unnecessary call to pci_save_state in probe function. - Fix null pointer dereference in probe function. - Move pci1xxxx_rs485_config to a separate patch. - Depends on SERIAL_8250_PCI & default to SERIAL_8250. - Change PORT_MCHP16550A to 100 from 124. --- MAINTAINERS | 7 + drivers/tty/serial/8250/8250_pci.c | 24 +- drivers/tty/serial/8250/8250_pci1xxxx.c | 370 ++++++++++++++++++++++++ drivers/tty/serial/8250/8250_pcilib.c | 34 +++ drivers/tty/serial/8250/8250_pcilib.h | 5 + drivers/tty/serial/8250/8250_port.c | 8 + drivers/tty/serial/8250/Kconfig | 15 + drivers/tty/serial/8250/Makefile | 2 + include/uapi/linux/serial_core.h | 3 + 9 files changed, 446 insertions(+), 22 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_pci1xxxx.c create mode 100644 drivers/tty/serial/8250/8250_pcilib.c create mode 100644 drivers/tty/serial/8250/8250_pcilib.h diff --git a/MAINTAINERS b/MAINTAINERS index d30f26e07cd3..aa98deaba249 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13434,6 +13434,13 @@ F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml F: drivers/nvmem/microchip-otpc.c F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h +MICROCHIP PCIe UART DRIVER +M: Kumaravel Thiagarajan +M: Tharun Kumar P +L: linux-serial@vger.kernel.org +S: Maintained +F: drivers/tty/serial/8250/8250_pci1xxxx.c + MICROCHIP PWM DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 6f66dc2ebacc..69ff367b08de 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -24,6 +24,7 @@ #include #include "8250.h" +#include "8250_pcilib.h" /* * init function returns: @@ -89,28 +90,7 @@ static int setup_port(struct serial_private *priv, struct uart_8250_port *port, u8 bar, unsigned int offset, int regshift) { - struct pci_dev *dev = priv->dev; - - if (bar >= PCI_STD_NUM_BARS) - return -EINVAL; - - if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { - if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) - return -ENOMEM; - - port->port.iotype = UPIO_MEM; - port->port.iobase = 0; - port->port.mapbase = pci_resource_start(dev, bar) + offset; - port->port.membase = pcim_iomap_table(dev)[bar] + offset; - port->port.regshift = regshift; - } else { - port->port.iotype = UPIO_PORT; - port->port.iobase = pci_resource_start(dev, bar) + offset; - port->port.mapbase = 0; - port->port.membase = NULL; - port->port.regshift = 0; - } - return 0; + return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); } /* diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c new file mode 100644 index 000000000000..b4b50909eb4d --- /dev/null +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Probe module for 8250/16550-type MCHP PCI serial ports. + * + * Based on drivers/tty/serial/8250/8250_pci.c, + * + * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "8250.h" +#include "8250_pcilib.h" + +#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 +#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 +#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 +#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 +#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 + +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f + +#define PCI_SUBDEVICE_ID_EFAR_PCI12000 0xa002 +#define PCI_SUBDEVICE_ID_EFAR_PCI11010 0xa012 +#define PCI_SUBDEVICE_ID_EFAR_PCI11101 0xa022 +#define PCI_SUBDEVICE_ID_EFAR_PCI11400 0xa032 +#define PCI_SUBDEVICE_ID_EFAR_PCI11414 0xa042 + +#define UART_ACTV_REG 0x11 +#define UART_BLOCK_SET_ACTIVE BIT(0) + +#define UART_PCI_CTRL_REG 0x80 +#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) +#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) + +#define ADCL_CFG_REG 0x40 +#define ADCL_CFG_POL_SEL BIT(2) +#define ADCL_CFG_PIN_SEL BIT(1) +#define ADCL_CFG_EN BIT(0) + +#define UART_BIT_SAMPLE_CNT 16 +#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) +#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) +#define UART_CLOCK_DEFAULT (62.5 * HZ_PER_MHZ) + +#define UART_WAKE_REG 0x8C +#define UART_WAKE_MASK_REG 0x90 +#define UART_WAKE_N_PIN BIT(2) +#define UART_WAKE_NCTS BIT(1) +#define UART_WAKE_INT BIT(0) +#define UART_WAKE_SRCS (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) + +#define UART_BAUD_CLK_DIVISOR_REG 0x54 + +#define UART_RESET_REG 0x94 +#define UART_RESET_D3_RESET_DISABLE BIT(16) + +struct pci1xxxx_8250 { + struct pci_dev *dev; + unsigned int nr; + void __iomem *membase; + int line[]; +}; + +static int pci1xxxx_get_num_ports(struct pci_dev *dev) +{ + switch (dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + return 2; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + return 3; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: + case PCI_SUBDEVICE_ID_EFAR_PCI11414: + return 4; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + default: + return 1; + } +} + +static unsigned int pci1xxxx_get_divisor(struct uart_port *port, + unsigned int baud, unsigned int *frac) +{ + unsigned int quot; + + /* + * Calculate baud rate sampling period in nanoseconds. + * Fractional part x denotes x/255 parts of a nanosecond. + */ + quot = (NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT)); + *frac = (((NSEC_PER_SEC - (quot * baud * UART_BIT_SAMPLE_CNT)) / + UART_BIT_SAMPLE_CNT) * 255) / baud; + + return quot; +} + +static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, + unsigned int quot, unsigned int frac) +{ + writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, + port->membase + UART_BAUD_CLK_DIVISOR_REG); +} + +static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, + struct uart_8250_port *port, int idx) +{ + int first_offset; + int offset; + int ret; + + switch (priv->dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + first_offset = 256; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + first_offset = 512; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + first_offset = 768; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + if (idx > 0) + idx++; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + if (idx > 0) + idx += 2; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + first_offset = 256; + if (idx > 0) + idx++; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + if (idx > 1) + idx++; + break; + default: + first_offset = 0; + break; + } + + offset = first_offset + idx * 256; + port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; + port->port.type = PORT_MCHP16550A; + port->port.set_termios = serial8250_do_set_termios; + port->port.get_divisor = pci1xxxx_get_divisor; + port->port.set_divisor = pci1xxxx_set_divisor; + ret = serial8250_pci_setup_port(priv->dev, port, 0, offset, 0); + if (ret < 0) + return ret; + + writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); + writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); + + return 0; +} + +static void pci1xxxx_irq_assign(struct pci1xxxx_8250 *priv, + struct uart_8250_port *uart, int idx) +{ + switch (priv->dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + uart->port.irq = pci_irq_vector(priv->dev, 1); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + uart->port.irq = pci_irq_vector(priv->dev, 2); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + uart->port.irq = pci_irq_vector(priv->dev, 3); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + if (idx > 0) + idx++; + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + if (idx > 0) + idx += 2; + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + uart->port.irq = pci_irq_vector(priv->dev, idx + 1); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + if (idx > 0) + idx += 1; + uart->port.irq = pci_irq_vector(priv->dev, idx + 1); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + uart->port.irq = pci_irq_vector(priv->dev, idx + 2); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + if (idx > 1) + idx++; + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + if (idx > 0) + idx++; + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + uart->port.irq = pci_irq_vector(priv->dev, idx + 1); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: + case PCI_SUBDEVICE_ID_EFAR_PCI11414: + uart->port.irq = pci_irq_vector(priv->dev, idx); + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: + case PCI_SUBDEVICE_ID_EFAR_PCI12000: + case PCI_SUBDEVICE_ID_EFAR_PCI11010: + case PCI_SUBDEVICE_ID_EFAR_PCI11101: + case PCI_SUBDEVICE_ID_EFAR_PCI11400: + default: + uart->port.irq = pci_irq_vector(priv->dev, 0); + break; + } +} + +static int pci1xxxx_serial_probe(struct pci_dev *dev, + const struct pci_device_id *ent) +{ + unsigned int nr_ports, i, j; + struct pci1xxxx_8250 *priv; + struct uart_8250_port uart; + int num_vectors = 0; + int rc; + + rc = pcim_enable_device(dev); + if (rc) + return rc; + + nr_ports = pci1xxxx_get_num_ports(dev); + + priv = devm_kzalloc(&dev->dev, struct_size(priv, line, nr_ports), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->membase = pcim_iomap(dev, 0, 0); + priv->dev = dev; + priv->nr = nr_ports; + pci_set_master(dev); + + num_vectors = pci_alloc_irq_vectors(dev, 1, 4, PCI_IRQ_ALL_TYPES); + if (num_vectors < 0) + return num_vectors; + + memset(&uart, 0, sizeof(uart)); + uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; + uart.port.uartclk = UART_CLOCK_DEFAULT; + uart.port.dev = &dev->dev; + + if (num_vectors == 4) + writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, + priv->membase + UART_PCI_CTRL_REG); + else + uart.port.irq = pci_irq_vector(dev, 0); + + for (i = 0; i < nr_ports; i++) { + if (num_vectors == 4) + pci1xxxx_irq_assign(priv, &uart, i); + + priv->line[i] = -ENOSPC; + rc = pci1xxxx_setup(priv, &uart, i); + if (rc) { + dev_err(&dev->dev, "Failed to setup port %u\n", i); + break; + } + priv->line[i] = serial8250_register_8250_port(&uart); + + if (priv->line[i] < 0) { + for (j = i + 1; j < nr_ports; j++) + priv->line[j] = -ENOSPC; + + dev_err(&dev->dev, + "Couldn't register serial port %lx, irq %d, type %d, error %d\n", + uart.port.iobase, uart.port.irq, + uart.port.iotype, priv->line[i]); + break; + } + } + + pci_set_drvdata(dev, priv); + + return 0; +} + +static void pci1xxxx_serial_remove(struct pci_dev *dev) +{ + struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) + serial8250_unregister_port(priv->line[i]); + } +} + +static const struct pci_device_id pci1xxxx_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, + {} +}; +MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); + +static struct pci_driver pci1xxxx_pci_driver = { + .name = "pci1xxxx serial", + .probe = pci1xxxx_serial_probe, + .remove = pci1xxxx_serial_remove, + .id_table = pci1xxxx_pci_tbl, +}; + +module_pci_driver(pci1xxxx_pci_driver); + +MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); +MODULE_AUTHOR("Kumaravel Thiagarajan "); +MODULE_AUTHOR("Tharun Kumar P "); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/8250_pcilib.c b/drivers/tty/serial/8250/8250_pcilib.c new file mode 100644 index 000000000000..2f0449026bc2 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * 8250 PCI library. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ +#include +#include "8250.h" + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, + u8 bar, unsigned int offset, int regshift) +{ + if (bar >= PCI_STD_NUM_BARS) + return -EINVAL; + + if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { + if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) + return -ENOMEM; + + port->port.iotype = UPIO_MEM; + port->port.iobase = 0; + port->port.mapbase = pci_resource_start(dev, bar) + offset; + port->port.membase = pcim_iomap_table(dev)[bar] + offset; + port->port.regshift = regshift; + } else { + port->port.iotype = UPIO_PORT; + port->port.iobase = pci_resource_start(dev, bar) + offset; + port->port.mapbase = 0; + port->port.membase = NULL; + port->port.regshift = 0; + } + return 0; +} +EXPORT_SYMBOL_GPL(serial8250_pci_setup_port); diff --git a/drivers/tty/serial/8250/8250_pcilib.h b/drivers/tty/serial/8250/8250_pcilib.h new file mode 100644 index 000000000000..d60d2b4a787b --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Microchip pci1xxxx 8250 library header file. */ + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, u8 bar, + unsigned int offset, int regshift); diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 1d2a43214b48..ec2fe5fd7b02 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -313,6 +313,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 4, 8, 14}, .flags = UART_CAP_FIFO, }, + [PORT_MCHP16550A] = { + .name = "MCHP16550A", + .fifo_size = 256, + .tx_loadsz = 256, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, + .rxtrig_bytes = {2, 66, 130, 194}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index d0b49e15fbf5..f67542470eae 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -132,6 +132,7 @@ config SERIAL_8250_DMA config SERIAL_8250_PCI tristate "8250/16550 PCI device support" depends on SERIAL_8250 && PCI + select SERIAL_8250_PCILIB default SERIAL_8250 help This builds standard PCI serial support. You may be able to @@ -291,6 +292,17 @@ config SERIAL_8250_HUB6 To compile this driver as a module, choose M here: the module will be called 8250_hub6. +config SERIAL_8250_PCI1XXXX + tristate "Microchip 8250 based serial port" + depends on SERIAL_8250_PCI + select SERIAL_8250_PCILIB + default SERIAL_8250 + help + Select this option if you have a setup with Microchip PCIe + Switch with serial port enabled and wish to enable 8250 + serial driver for the serial interface. This driver support + will ensure to support baud rates upto 1.5Mpbs. + # # Misc. options/drivers. # @@ -500,6 +512,9 @@ config SERIAL_8250_MID Intel Medfield SOC and various other Intel platforms that is not covered by the more generic SERIAL_8250_PCI option. +config SERIAL_8250_PCILIB + bool + config SERIAL_8250_PERICOM tristate "Support for Pericom and Acces I/O serial ports" default SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index bee908f99ea0..98202fdf39f8 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o 8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o +8250_base-$(CONFIG_SERIAL_8250_PCILIB) += 8250_pcilib.o obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o @@ -26,6 +27,7 @@ obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o +obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 3ba34d8378bd..281fa286555c 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -207,6 +207,9 @@ /* Atheros AR933X SoC */ #define PORT_AR933X 99 +/* MCHP 16550A UART with 256 byte FIFOs */ +#define PORT_MCHP16550A 100 + /* ARC (Synopsys) on-chip UART */ #define PORT_ARC 101 From patchwork Fri Nov 11 16:11:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 18900 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp838137wru; Fri, 11 Nov 2022 08:20:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf4VTSPDq3/dem2qogGLEzHMuWXR26hUPWeQhgNXRrICTab6U6tXgGi6wEpNsj61nkhKEsB3 X-Received: by 2002:a62:1c94:0:b0:56b:cc74:4bd5 with SMTP id c142-20020a621c94000000b0056bcc744bd5mr3337087pfc.79.1668183599810; Fri, 11 Nov 2022 08:19:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668183599; cv=none; d=google.com; s=arc-20160816; b=ww4BEyG+ORPtpLsJfRZsKykL/080j6Oerh0urddfhIwQQPsmrNXDmD8XBiEcUQUUze QgOaXPobqonFl/qVV3pljGTCNtnpdMMjtsdkFK6ZS1yPioP3QQasvqG2VGhISZZ9cnDQ X4GzVZ0xYWUJtoSpyOyfM2Tk4WySg0eBhsRblwMTwftq3S0qOvUoyJmhiEp/Evnj5B4p KWPtmLrBC3FI/xOHZK5bGClIUKQTPXMfnZ+G3gweBPKXL9xE4tKshzjHQlmA0wFMFHc5 mQigeTavBIK4Imd2eLPgNKs+psCLWKXsL6kbU0xBL2fR1rcWQWSjFkID+gFm26vAPzwS Guyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rIu3k6dPGbST7dlsHbrwukw536uR1N9ivYjvj2vYeNQ=; b=HS/R5oM3C/wHnh/4yL6T45vmMu7yTaeiyJmuZRmxDiIpfVtT5ULNdWmDw74ciCFn7d 3M7Y4FiCPvCZH7EzmDl52B3ggDn7le7nxzLWyCUrqExSHwPrYsTGFLkXVp2oD1DpaCRz kFV2SiFzEyEvN9MMDxmYBEyQ2zcBiLvMut6NkzkqPVH0ILBc3YDq3PPUYlrIYF4IK9lM ST56cLntRxStZZ74kq0hNEw3b5IhoBhy9jGGKYJKsbOd8bkTPKPhTFUdprS4lNpCSR7z Aa1w53weuwYmFaDrSe6C59DBUNIUrdqq3hIbs5AhGvHS52QJrrPY27OhYj8wZiCSGdt6 DHzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ZnqZEBUm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 70-20020a630149000000b004395afacb7csi2685757pgb.214.2022.11.11.08.19.44; Fri, 11 Nov 2022 08:19:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ZnqZEBUm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234230AbiKKQLr (ORCPT + 99 others); Fri, 11 Nov 2022 11:11:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234153AbiKKQLf (ORCPT ); Fri, 11 Nov 2022 11:11:35 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC6DB787B8; Fri, 11 Nov 2022 08:11:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668183087; x=1699719087; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p9jRTYmyoBsS2jW1aR2osYNrdlG945o/hIZs/x6KAgo=; b=ZnqZEBUmkDeihpDE+/6EvOkmfq59N7ihKou/5CTbi4wcwrapFkJY0pHJ sieMHNplYm8/czYGAlgfLhfQsAinfYe56iDdQHDWVvl+W19Gxx4pEIj7z WGe72GYsntBWzVykTm0uMPA8uUp2kq69DQHTtqHyj9oz59eVyEVHSQSQ3 vV8beytEn0VUhktQnsz54l6/6dNwsHym1alpgjvbPkF/pyLgqi5w5uc13 6DMaYRAoOZOc3DsFbFPQ5jFEh3o5ENtT3zFjWQY9lTPf4rxEddwP99JZ2 66PVrPDsQTBU0LAXizY0lP56aLXKpuzsEr4BQRY1eSBqvUbpmFRPu2joQ g==; X-IronPort-AV: E=Sophos;i="5.96,156,1665471600"; d="scan'208";a="186585024" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Nov 2022 09:11:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 11 Nov 2022 09:11:15 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 11 Nov 2022 09:11:09 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v4 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485 support to quad-uart driver Date: Fri, 11 Nov 2022 21:41:29 +0530 Message-ID: <20221111161130.2043882-3-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111161130.2043882-1-kumaravel.thiagarajan@microchip.com> References: <20221111161130.2043882-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749217286458429940?= X-GMAIL-MSGID: =?utf-8?q?1749217286458429940?= pci1xxxx uart supports rs485 mode of operation in the hardware with auto-direction control with configurable delay for releasing RTS after the transmission. This patch adds support for the rs485 mode. Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v4: - No Change Changes in v3: - Remove flags sanitization in driver which is taken care in core Changes in v2: - move pci1xxxx_rs485_config to a separate patch with pci1xxxx_rs485_supported. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index b4b50909eb4d..97636818db5c 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -137,6 +137,53 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, port->membase + UART_BAUD_CLK_DIVISOR_REG); } +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + u8 delay_in_baud_periods = 0; + u32 baud_period_in_ns = 0; + u32 data = 0; + + /* pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + data |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + (rs485->delay_rts_after_send * NSEC_PER_MSEC) / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u8, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + (baud_period_in_ns * delay_in_baud_periods) / + NSEC_PER_MSEC; + rs485->delay_rts_before_send = 0; + } + } + writel(data, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int idx) { @@ -186,6 +233,8 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; ret = serial8250_pci_setup_port(priv->dev, port, 0, offset, 0); if (ret < 0) return ret; From patchwork Fri Nov 11 16:11:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 18902 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp838945wru; Fri, 11 Nov 2022 08:21:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf5wBCYFg+bdzR3Ws2q68TIjNS6s5aiUJlnJo7ot32gZovLqWSlEuRM5wijT8/J4vBYnBNQq X-Received: by 2002:a05:6402:ea0:b0:461:a9ce:5408 with SMTP id h32-20020a0564020ea000b00461a9ce5408mr2148673eda.201.1668183685693; Fri, 11 Nov 2022 08:21:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668183685; cv=none; d=google.com; s=arc-20160816; b=RH7xyuMaYtbQ7ynNeMtmgABMcmjfZiKcBDLEc9lZgZUr/Q/wmkl4eV2gD97zTJ7GkH TdRTm/GlyXY/U4svZYRAHdUavwzWaL5EPZsDOHgv0m350LRQQkyA3YXT3zaPlAp1LV7c B9oNO8J+nmCktIUTQo+y8ZGE9POX216e3x0jmmsbX9100IhB3Cji18GdLMvfTQ92l9Qk FA1JB/AU43wsXb7dZn6VV5aWnKIgPk7AFte7Z740x3mkA9u5uaV6Dh54UE6vxwIhHih4 7SJzqaCYer77FvVOKlaZGDgfnNbKXrnpCxOtRyQioPQwixN0BFw8X4RHQwG+E0wfO9bA vKJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lTd9UUlPwYHfB/xJga7Jq0FjtDDdwqyNKfcxho4KzIQ=; b=VapojtX3ndwavvIk9gGbxvjDBN7TRl/i51uyv8yCofzh9E4rmZiIqiwRAV4tNFUNVh iWVVi7+ONpniNDb3q/UjdirS3vCjnSxkK6LdjqknsI+n9cLd0TDtsRsXJUMYS7VdpQvS etJf6UztI4erav1UXhClK3/rTOWsEEQK7uV6jU1xMZfDxhBvkFj9UiB5CLdMb/wiOHPj Rk9kNHLI0EvgyHG2ncogjHTHGLQ0ix8Gp2mz9SXilNVvDlT6AG1BtIdEsx7GkqM0zXmQ ZxIUXGjIiNA9oYLEsL+4uj/IxBLtInp51oIjBf+6MQ1I8u5c3PbreMs95Sv0rIo10bXz wX5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=FLbZvk5G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r22-20020aa7c156000000b004615ccd71a0si2272640edp.162.2022.11.11.08.20.59; Fri, 11 Nov 2022 08:21:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=FLbZvk5G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234114AbiKKQLj (ORCPT + 99 others); Fri, 11 Nov 2022 11:11:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233950AbiKKQLe (ORCPT ); Fri, 11 Nov 2022 11:11:34 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B70096315D; Fri, 11 Nov 2022 08:11:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668183086; x=1699719086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=72v/JHHAuGu0nowyr7cxKPumT2RZhgjZqsSNfigexzY=; b=FLbZvk5GrMl71y7JM1KschZ5lE9+H29c1qdM0rsq97XTsJYbB2JcdcWI FVBorOjU1MI6yaFu8jmvGjdwEfs8YZ8HzT9wmASr4KjsZGsyHTp0KUZrn bo8genAgZtHWJCoqdwCeH7NRjfsm1GH2BbhfgeJERy9VzcttU3z6tG8z8 STzyp2ZovR02eSWMHGxS7BEwPLWoiuw60/JtcPMJjI91CGYs2oQn0ZZQL qg5dgA0XBDEK9ehjbgg6UPpP5ZRAXemFa7VAV/2gxUpHx8F2BzH1PW5th Y3DBgcZHfiJ2GnNvddtvlZGntGVn9mfjPQyB1B/FPOkcwujt88U8mW9g+ w==; X-IronPort-AV: E=Sophos;i="5.96,156,1665471600"; d="scan'208";a="188636617" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Nov 2022 09:11:25 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 11 Nov 2022 09:11:23 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 11 Nov 2022 09:11:17 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v4 tty-next 3/3] 8250: microchip: pci1xxxx: Add power management functions to quad-uart driver Date: Fri, 11 Nov 2022 21:41:30 +0530 Message-ID: <20221111161130.2043882-4-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111161130.2043882-1-kumaravel.thiagarajan@microchip.com> References: <20221111161130.2043882-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749217376834036989?= X-GMAIL-MSGID: =?utf-8?q?1749217376834036989?= pci1xxxx's quad-uart function has the capability to wake up the host from suspend state. Enable wakeup before entering into suspend and disable wakeup on resume. Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v4: - No Change Changes in v3: - Handled race condition in suspend and resume callbacks Changes in v2: - Use DEFINE_SIMPLE_DEV_PM_OPS instead of SIMPLE_DEV_PM_OPS. - Use pm_sleep_ptr instead of CONFIG_PM_SLEEP. - Change the return data type of pci1xxxx_port_suspend to bool from int. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 97636818db5c..60619f65e114 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -184,6 +184,117 @@ static const struct serial_rs485 pci1xxxx_rs485_supported = { /* Delay RTS before send is not supported */ }; +static bool pci1xxxx_port_suspend(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + bool ret = false; + u8 wakeup_mask; + + mutex_lock(&tport->mutex); + if (port->suspended == 0 && port->dev) { + wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); + + spin_lock_irqsave(&port->lock, flags); + port->mctrl &= ~TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + + if ((wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS) + ret = true; + } + + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + mutex_unlock(&tport->mutex); + + return ret; +} + +static void pci1xxxx_port_resume(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + + mutex_lock(&tport->mutex); + writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + + if (port->suspended == 0) { + spin_lock_irqsave(&port->lock, flags); + port->mctrl |= TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + } + mutex_unlock(&tport->mutex); +} + +static int pci1xxxx_suspend(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + bool wakeup = false; + unsigned int data; + void __iomem *p; + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + serial8250_suspend_port(priv->line[i]); + wakeup |= pci1xxxx_port_suspend(priv->line[i]); + } + } + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + + if (wakeup) + writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); + + iounmap(p); + device_set_wakeup_enable(dev, true); + pci_wake_from_d3(pcidev, true); + + return 0; +} + +static int pci1xxxx_resume(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + unsigned int data; + void __iomem *p; + int i; + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + iounmap(p); + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + pci1xxxx_port_resume(priv->line[i]); + serial8250_resume_port(priv->line[i]); + } + } + + return 0; +} + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int idx) { @@ -394,6 +505,9 @@ static void pci1xxxx_serial_remove(struct pci_dev *dev) } } +static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, + pci1xxxx_resume); + static const struct pci_device_id pci1xxxx_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, @@ -408,6 +522,9 @@ static struct pci_driver pci1xxxx_pci_driver = { .name = "pci1xxxx serial", .probe = pci1xxxx_serial_probe, .remove = pci1xxxx_serial_remove, + .driver = { + .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), + }, .id_table = pci1xxxx_pci_tbl, };