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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y14-20020a17090ad70e00b0020d9f618c4asi6933963pju.17.2022.11.11.06.06.05; Fri, 11 Nov 2022 06:06:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Cl5Cge90; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=vJI5ABKs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234375AbiKKOFD (ORCPT + 99 others); Fri, 11 Nov 2022 09:05:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234108AbiKKOEl (ORCPT ); Fri, 11 Nov 2022 09:04:41 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3783889F93; Fri, 11 Nov 2022 05:58:52 -0800 (PST) Message-ID: <20221111135205.309731052@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175093; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=x3hIqu1krW0wya/Cp5B9blgpcq3/YMthZGe6CW4aay0=; b=Cl5Cge90NeD11tWuUxPPNdqZbeOuu4BQbbJMd3s9+G4WD0B9jm0X3WAOhAy2+ZIQ5xgVeY nPgODgSeTnlOzkTqejTq7e1tsTPXmPTG07cumpYKhU+huUjnB0PgzxC+HKe9O4D4kWOFDH GhQ0dJ890Y7W+YCJL9W8srS/HxDfxc2jEFyKjBp9PM8QeGxpdXM7Uwr93MATI+dlCynZ9K NPEn5kuFfG9Ka8zpB2HV86db979qP7UD18U+LQpUbq+rMjeoyToZjYkybfI2Rfo27lxpA6 E8LdRZHmeYCL1FIrZKAKpmHrfX7CygBkvkO9B1lGvGrHLvhYpy4+9twcRYbBIQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175093; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=x3hIqu1krW0wya/Cp5B9blgpcq3/YMthZGe6CW4aay0=; b=vJI5ABKsNoBbr9nzBicoj0rOjr0qz69urGN0yNn0bnfvWmNvrsRfmT6zwZYg8ATxc4NGuw 2IqzREvpGLwcaRBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 01/33] genirq/msi: Rearrange MSI domain flags References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:12 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208879963398399?= X-GMAIL-MSGID: =?utf-8?q?1749208879963398399?= These flags got added as necessary and have no obvious structure. For feature support checks and masking it's convenient to have two blocks of flags: 1) Flags to control the internal behaviour like allocating/freeing MSI descriptors. Those flags do not need any support from the underlying MSI parent domain. They are mostly under the control of the outermost domain which implements the actual MSI support. 2) Flags to expose features, e.g. PCI multi-MSI or requirements which can depend on a underlying domain. No functional change. Signed-off-by: Thomas Gleixner Reviewed-by: Jason Gunthorpe --- include/linux/msi.h | 49 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 15 deletions(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -24,6 +24,8 @@ #include #include #include +#include + #include /* Dummy shadow structures if an architecture does not define them */ @@ -428,7 +430,16 @@ struct msi_domain_info { void *data; }; -/* Flags for msi_domain_info */ +/* + * Flags for msi_domain_info + * + * Bit 0-15: Generic MSI functionality which is not subject to restriction + * by parent domains + * + * Bit 16-31: Functionality which depends on the underlying parent domain and + * can be masked out by msi_parent_ops::init_dev_msi_info() when + * a device MSI domain is initialized. + */ enum { /* * Init non implemented ops callbacks with default MSI domain @@ -440,33 +451,41 @@ enum { * callbacks. */ MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1), - /* Support multiple PCI MSI interrupts */ - MSI_FLAG_MULTI_PCI_MSI = (1 << 2), - /* Support PCI MSIX interrupts */ - MSI_FLAG_PCI_MSIX = (1 << 3), /* Needs early activate, required for PCI */ - MSI_FLAG_ACTIVATE_EARLY = (1 << 4), + MSI_FLAG_ACTIVATE_EARLY = (1 << 2), /* * Must reactivate when irq is started even when * MSI_FLAG_ACTIVATE_EARLY has been set. */ - MSI_FLAG_MUST_REACTIVATE = (1 << 5), - /* Is level-triggered capable, using two messages */ - MSI_FLAG_LEVEL_CAPABLE = (1 << 6), + MSI_FLAG_MUST_REACTIVATE = (1 << 3), /* Populate sysfs on alloc() and destroy it on free() */ - MSI_FLAG_DEV_SYSFS = (1 << 7), - /* MSI-X entries must be contiguous */ - MSI_FLAG_MSIX_CONTIGUOUS = (1 << 8), + MSI_FLAG_DEV_SYSFS = (1 << 4), /* Allocate simple MSI descriptors */ - MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = (1 << 9), + MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = (1 << 5), /* Free MSI descriptors */ - MSI_FLAG_FREE_MSI_DESCS = (1 << 10), + MSI_FLAG_FREE_MSI_DESCS = (1 << 6), /* * Quirk to handle MSI implementations which do not provide * masking. Currently known to affect x86, but has to be partially * handled in the core MSI code. */ - MSI_FLAG_NOMASK_QUIRK = (1 << 11), + MSI_FLAG_NOMASK_QUIRK = (1 << 7), + + /* Mask for the generic functionality */ + MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), + + /* Mask for the domain specific functionality */ + MSI_DOMAIN_FLAGS_MASK = GENMASK(31, 16), + + /* Support multiple PCI MSI interrupts */ + MSI_FLAG_MULTI_PCI_MSI = (1 << 16), + /* Support PCI MSIX interrupts */ + MSI_FLAG_PCI_MSIX = (1 << 17), + /* Is level-triggered capable, using two messages */ + MSI_FLAG_LEVEL_CAPABLE = (1 << 18), + /* MSI-X entries must be contiguous */ + MSI_FLAG_MSIX_CONTIGUOUS = (1 << 19), + }; int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, From patchwork Fri Nov 11 13:58:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18821 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp758895wru; Fri, 11 Nov 2022 06:06:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf5pt3Y+2iJn0JxYA4IwUc211zWt293qc1jpJUjXVtT6Dy4sEXS6e6frFaNl8DBQFt77SnPr X-Received: by 2002:a63:1a59:0:b0:473:c377:b82 with SMTP id a25-20020a631a59000000b00473c3770b82mr1909287pgm.113.1668175601528; Fri, 11 Nov 2022 06:06:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175601; cv=none; d=google.com; s=arc-20160816; b=QB7IDxv7cK25ApPmC8GLZGh5filw1OPppxAyzcLoyDJsFWgqRdpWpGDq/w5H4Bd1Im pzz3c5Q+berekFPdcKnf87VS84mehqlOUAmJnIZ9ssWdzVU2+8r49hp68FvjZe0MvxZ8 Vz0zC6HZCSDZAmZgZW+/KRbgopvTgDhWlHLHcTUbiundtiXIAn2Bu6TIuz8h2izp8UP9 sKxImUcM3qfpzZwakr9lXjUprDET0zTbF80yK3no4nNfq/JwoxfuKZ/XtukKBJN9Q2vy /gmXm0PcpfPSnsteUhygqFCLdxPXrWX38OQNIdIx+4BhCubqJVLz4EbjhvGVKfDpIlfP Q+Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=e8FMSieAN/nuamC9qf7yvRciPl3gkYlctlSfz55sfqw=; b=UI0YiHSPtXmf6H8YZAKN9X7NyZRcLYHilImC2f1fJpkHfy7lquWna5+6LQvuBW1gRF /7SWAQro57EorXOTXnfU091j5v4BTizVmrB1DV6sF0Y8h1YiWj5iEeLKZd8OjOckRKpI Iu1Ee/cN3Fuh3d6rzGsLrzw04enT3hRQvFmsMYxuqW6jmJ8ifZoF46qyAucLKxaUsB1E teci+YnjVC8c96cAHjK4MF4ZM+b061P6zO8n049fYi1LDsB8OhWjIrxm91he8b7yD4pS S4Jk7tPT3T5AI4+v3rci0H/UmrnlGCDyqB21um1MfzmBotCi8w577ZOjI/q4NpRdrRqc EnBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=whPHvmGs; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jc13-20020a17090325cd00b00186b280a430si2214561plb.242.2022.11.11.06.06.27; Fri, 11 Nov 2022 06:06:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=whPHvmGs; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234415AbiKKOFK (ORCPT + 99 others); Fri, 11 Nov 2022 09:05:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234082AbiKKOEo (ORCPT ); Fri, 11 Nov 2022 09:04:44 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2363987B2B; Fri, 11 Nov 2022 05:58:53 -0800 (PST) Message-ID: <20221111135205.368911521@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=e8FMSieAN/nuamC9qf7yvRciPl3gkYlctlSfz55sfqw=; b=whPHvmGsSTEAxU0UpyWL+s2V98t8wQyMTkxmtcd3cFXgOGnWMjhx4YnxJWu8M+OFve1iEm 2kWzHThXQzkJZEDdJ+9EQpyEOLJryPs0CK/4lYS55RTgMuSWVTXxLvjJge6071up38G8z3 wPW65B7I/v5uiVDEb2yXTphln4iR2r2RDa/5hLeytVR/f0z4j+K8DcyxNbMFEHJLNAYeTI O0CSuItSz2dT03GPUIn7DqDRlrQBxvhMcn197ojQcoj8x6FRTqeaqahntGPSGiIax1pn4Z 9ORsvROp++bdSHkjnorAcyg606IZ5KyGkduPbjClPaizcHMI2fWXXKgArNyV0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=e8FMSieAN/nuamC9qf7yvRciPl3gkYlctlSfz55sfqw=; b=Easie5wEeQFjls8M+15mkYyIDobQYmQxU9KI3o95c+umHJwBwacQjMprgv1YGq2vfl5Pn8 uzq5ge9MfxJaxgAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 02/33] genirq/msi: Provide struct msi_parent_ops References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:14 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208899665101927?= X-GMAIL-MSGID: =?utf-8?q?1749208899665101927?= MSI parent domains must have some control over the MSI domains which are built on top. On domain creation they need to fill in e.g. architecture specific chip callbacks or msi domain ops to make the outermost domain parent agnostic which is obviously required for architecture independence etc. The structure contains: 1) A bitfield which exposes the supported functional features. This allows to check for features and is also used in the initialization callback to mask out unsupported features when the actual domain implementation requests a broader range, e.g. on x86 PCI multi-MSI is only supported by remapping domains but not by the underlying vector domain. The PCI/MSI code can then always request multi-MSI support, but the resulting feature set after creation might not have it set. 2) An optional string prefix which is put in front of domain and chip names during creation of the MSI domain. That allows to keep the naming schemes e.g. on x86 where PCI-MSI domains have a IR- prefix when interrupt remapping is enabled. 3) An initialization callback to sanity check the domain info of the to be created MSI domain, to restrict features and to apply changes in MSI ops and interrupt chip callbacks to accomodate to the particular MSI parent implementation and/or the underlying hierarchy. Add a conveniance function to delegate the initialization from the MSI parent domain to an underlying domain in the hierarchy. Signed-off-by: Thomas Gleixner --- include/linux/irqdomain.h | 5 +++++ include/linux/msi.h | 20 ++++++++++++++++++++ kernel/irq/msi.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -46,6 +46,7 @@ struct irq_desc; struct cpumask; struct seq_file; struct irq_affinity_desc; +struct msi_parent_ops; #define IRQ_DOMAIN_IRQ_SPEC_PARAMS 16 @@ -134,6 +135,7 @@ struct irq_domain_chip_generic; * @pm_dev: Pointer to a device that can be utilized for power management * purposes related to the irq domain. * @parent: Pointer to parent irq_domain to support hierarchy irq_domains + * @msi_parent_ops: Pointer to MSI parent domain methods for per device domain init * * Revmap data, used internally by the irq domain code: * @revmap_size: Size of the linear map table @revmap[] @@ -157,6 +159,9 @@ struct irq_domain { #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY struct irq_domain *parent; #endif +#ifdef CONFIG_GENERIC_MSI_IRQ + const struct msi_parent_ops *msi_parent_ops; +#endif /* reverse map data. The linear map gets appended to the irq_domain */ irq_hw_number_t hwirq_max; --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -488,6 +488,26 @@ enum { }; +/** + * struct msi_parent_ops - MSI parent domain callbacks and configuration info + * + * @supported_flags: Required: The supported MSI flags of the parent domain + * @prefix: Optional: Prefix for the domain and chip name + * @init_dev_msi_info: Required: Callback for MSI parent domains to setup parent + * domain specific domain flags, domain ops and interrupt chip + * callbacks when a per device domain is created. + */ +struct msi_parent_ops { + u32 supported_flags; + const char *prefix; + bool (*init_dev_msi_info)(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info); +}; + +bool msi_parent_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, struct msi_domain_info *info); + int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force); --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -825,6 +825,42 @@ struct irq_domain *msi_create_irq_domain return domain; } +/** + * msi_parent_init_dev_msi_info - Delegate initialization of device MSI info to parent domain + * @dev: The device for which the domain should be created + * @domain: The domain which delegates + * @real_parent: The real parent domain of the to be initialized MSI domain + * @info: The MSI domain info to initialize + * + * Return: true on success, false otherwise + * + * This is the most complex problem of per device MSI domains and the + * underlying interrupt domain hierarchy: + * + * The device domain to be initialized requests the broadest feature set + * possible and the underlying domain hierarchy puts restrictions on it. + * + * That's working perfectly fine for a strict parent->device model, but it + * falls apart with a root_parent->real_parent->device chain because the + * intermediate 'real parent' can expand the capabilities which the + * 'root_parent' domain is providing. So that creates a classic hen and egg + * problem: Which entity is doing the restrictions/expansions? + * + * One solution is to let the root parent domain handle the initialization + * that's why there is the @domain and the @real_parent pointer. + */ +bool msi_parent_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, struct msi_domain_info *info) +{ + struct irq_domain *parent = domain->parent; + + if (WARN_ON_ONCE(!parent || !parent->msi_parent_ops || + !parent->msi_parent_ops->init_dev_msi_info)) + return false; + + return parent->msi_parent_ops->init_dev_msi_info(dev, parent, real_parent, info); +} + int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *arg) { From patchwork Fri Nov 11 13:58:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18820 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp758888wru; Fri, 11 Nov 2022 06:06:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf7kPoF6vv0uM5Hcxj33RMYU/UbWdAk5SdbbHsnrrhTpapEE3gLj6DSSck2ao+Vmf1alNdIj X-Received: by 2002:a17:90a:4503:b0:200:2069:7702 with SMTP id u3-20020a17090a450300b0020020697702mr2067601pjg.239.1668175600999; Fri, 11 Nov 2022 06:06:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175600; cv=none; d=google.com; s=arc-20160816; b=lL3lxKHkA8n/M5C+cJyYSm9tZ8xhliLlpnJnOF4tDpO9jNl+0ro+8rfIO1sU0rwebL 3a5k9AV9AW30Zclti7SzhbZIJ2RNcAt5o7Hec6ZxvaG8kXI/4r2hUvHQRLtq5equlS2e GClZspWyI1sgpCAw2x+s/Zf8RHHb9qD1VdUrKgSZ8Y7j/aeZXnjWf3f5VZiV6pEcNE/r gKxRzVCZaEdkWII9h0ftY3YnrHO3JxcWFwW3STVaip2/UotA3YwXt53rVNbMMe9LbkCu QTYbD+yLRqT6x5y6hnQxvZsuadoQhmYNGR+9a3MJtsjVazJiRw2xd4pyNDUQ7HGU64Xg 0UKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=/GP5ZfhesXV4jkE3W+IUGaBn9TdtWzm6Yg+gBfFIDQM=; b=Hyuyco54ofJciiHkaFXrhDkzr05rq3SCASfVooyI1qkCMFV2agB8N5eZN9uoZ+EiTn 3tetm591IY5BzS5vhUUWM/M1CAKJhmrYqzZLZtxXTH2AJ3+KnliBc3nytEEah2ZS9mii 6EAWcT0fFUiU2RDobfH7gI9ZmmrV56gbH+2CTQpxYEDS7qlM11apg4DFr2jCDsNw4mGc 7ZjzICH6GU1yFIA106Gc2mpYEWLRsCeAtW9YTBF4hi7HthRX5xC3ewCBZf+82eTP8JbN ctey1K5FnVu75Rw9xFdg0ckygj7ZysuP/7VzgrWUq7lkuaZeN1kmO0VdvbGwRtkp3MIZ aT5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=T9GnH5Wx; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 03/33] genirq/msi: Provide data structs for per device domains References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:15 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208899116489683?= X-GMAIL-MSGID: =?utf-8?q?1749208899116489683?= Provide struct msi_domain_template which contains a bundle of struct irq_chip, struct msi_domain_ops and struct msi_domain_info and a name field. This template is used by MSI device domain implementations to provide the domain specific functionality, feature bits etc. When a MSI domain is created the template is duplicated in the core code so that it can be modified per instance. That means templates can be marked const at the MSI device domain code. The template is a bundle to avoid several allocations and duplications of the involved structures. The name field is used to construct the final domain and chip name via: $PREFIX-$NAME-$DEVNAME where prefix is the optional prefix of the MSI parent domain, $NAME is the provided name in template::chip and the device name so that the domain is properly identified. On x86 this results for PCI/MSI in: PCI-MSI-0000:3d:00.1 or IR-PCI-MSIX-0000:3d:00.1 depending on the domain type and the availability of remapping. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -74,7 +75,6 @@ struct msi_msg { extern int pci_msi_ignore_mask; /* Helper functions */ -struct irq_data; struct msi_desc; struct pci_dev; struct platform_msi_priv_data; @@ -430,6 +430,20 @@ struct msi_domain_info { void *data; }; +/** + * struct msi_domain_template - Template for MSI device domains + * @name: Storage for the resulting name. Filled in by the core. + * @chip: Interrupt chip for this domain + * @ops: MSI domain ops + * @info: MSI domain info data + */ +struct msi_domain_template { + char name[48]; + struct irq_chip chip; + struct msi_domain_ops ops; + struct msi_domain_info info; +}; + /* * Flags for msi_domain_info * From patchwork Fri Nov 11 13:58:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18822 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759083wru; Fri, 11 Nov 2022 06:06:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf7zdN2aHUYZtP7hxOY/jNVXroPGM+2lQZNbV0tYODoJw9UV9XmQ0vekM2plZoTGz9G8e5PC X-Received: by 2002:a17:902:da90:b0:187:12cc:d6f1 with SMTP id j16-20020a170902da9000b0018712ccd6f1mr2395013plx.63.1668175617858; Fri, 11 Nov 2022 06:06:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175617; cv=none; d=google.com; s=arc-20160816; b=PgD5BlpDxmH/aT+N7fk5+nIvr8pC+JAEoGGVTfQ+uvtlOYD/X4HovHhJY+qs6Ve3eW O3iPNHvWxWUIYaKr5izL4tZKFoA+Upy/DcObQXAjzZKmw8XIIfu8gw2pdiZGyZFkbw9d mEftId4ET973z8XhYMmmGtsyfULjeeWtY7zMKv2jKfa6M9v66Y9wi0LkZM9cVpfVTFhB jx10urTOEXboK6kEq2QTIlZAemQE6tKPP97dOyiKrn4ymxL+8PxvrTRT2a83eIkTF/s6 8nvH3VSVVbuC6ZimdySVNqjGtxEkX3+N5w/KmtlBm0g4uf1SpkcxJYNMPX6Lrw6axglD +DWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=wvq/UAWBnWLIn373I3iZtaQ+G1F0GV+IlK6QQPaFqcU=; b=yqyLn5krf54r2W28sy7VCwRz3hsc5FTVc4mmBKKtwImqf9k8FVAepxMit3uadNfiEm lD8wIlQdLd0FWbBJoUaRoV5BI3IIBxDQSEM7JcayI0ZTTPgIkBEFtN3ZPc9OZtu+rLcf hhywwfaepZhWiaVKFn78neKQ1kWpNay0BmZ/g6SMmkSXj9/GaKDUj82DqQPiUFNhhZ21 Fikp8S049CH3DSBXIjLU1z2ZJsdB7Yz5wULXG6s1kv49dKsLA9gR3/x3vKRbAyaDDso0 P1kpbMUlnvHx1MGWKh82mqL8K/QSYGZjByPghGWoei0OxrJd5nK9JQPQ0W2EmDwNw3of gTtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Oi5Fm2es; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="L0f1/AJb"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 04/33] genirq/msi: Add size info to struct msi_domain_info References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:17 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208916455089846?= X-GMAIL-MSGID: =?utf-8?q?1749208916455089846?= To allow proper range checking especially for dynamic allocations add a size field to struct msi_domain_info. If the field is 0 then the size is unknown or unlimited (up to MSI_MAX_INDEX) to provide backwards compability. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 2 ++ 1 file changed, 2 insertions(+) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -410,6 +410,7 @@ struct msi_domain_ops { * struct msi_domain_info - MSI interrupt domain data * @flags: Flags to decribe features and capabilities * @bus_token: The domain bus token + * @hwsize: The hardware table size (0 if unknown/unlimited) * @ops: The callback data structure * @chip: Optional: associated interrupt chip * @chip_data: Optional: associated interrupt chip data @@ -421,6 +422,7 @@ struct msi_domain_ops { struct msi_domain_info { u32 flags; enum irq_domain_bus_token bus_token; + unsigned int hwsize; struct msi_domain_ops *ops; struct irq_chip *chip; void *chip_data; From patchwork Fri Nov 11 13:58:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18832 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760214wru; Fri, 11 Nov 2022 06:08:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf7iqbAw8xee5TCsFpATnbgzszdzu89KwgxJX33eFwFODa9xH18xcSp8XrIA4oZ+qUIZY5hh X-Received: by 2002:a63:4e20:0:b0:470:2c90:3bc6 with SMTP id c32-20020a634e20000000b004702c903bc6mr1912630pgb.158.1668175712808; Fri, 11 Nov 2022 06:08:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175712; cv=none; d=google.com; s=arc-20160816; b=nJJdo6D3vMUI8L4xhGbtV96MSjAUj2qaYayQzFD0OACShxHEHD/k3HcnF5FUYsWjOV 25NfNMhtCdJsNE/3k5qZHd51UeGQEIeRMUWF31l18a3VSIX67Ba5NMo4wVKBmT/+kCy9 4nzjqQhkSXi2jzUsPby8N9V9qrcQPMeZWsRWPa2xOIipFwm0ZWjtX/Bb8P75P9a4Wngf wy1VmJkfg9Rc3IOCh2OP+P9UrUQDbMfwX2oaupnqC1HAcUihwUG41XtiozFuCNNcQuRC lz8XVNss43xKR4hJNUnb+MmvME13kpG6C7Qz52PzN69KL7q2Hb0ygNT7lzLsIs9M2fcV RJUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Oak79lo/7cHcPMXn18Hj8VarinH9SEGY40y7VRfsAjo=; b=HKqrEZj1HTEg/3BulYDYRxJZdXoC37Fsx/QSzGUeVShVwIrVv/dyniDshHTyK+D7Qu milKw2TEs5wGyhkoWOST3MXrIqpQTCd3YZq1CaJA5lf5rMb5V2VBZF9wuHY0mgKVYKe9 upZBrST+uUS/7HfY9mNgTkedigVJhz972DuukVVRPHY4bZ+xNy98m/bhi75Vy911/Jro EAP43MXSWCYuDEPmZsWPNIkWfQYvw9ZK4qlquknSehECLHPi+14+K5ASzNKvU3w2VGK7 y5WwFabonNbgdkhHxqmCgIaJMxiN9pQ2SIN57tE9+l4u/oKNkPiNW3N4VXZxpomq3Prf mH7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=pBqdNgbA; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k3-20020aa79d03000000b0056cac533dfdsi2127914pfp.261.2022.11.11.06.08.15; Fri, 11 Nov 2022 06:08:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=pBqdNgbA; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234113AbiKKOHx (ORCPT + 99 others); Fri, 11 Nov 2022 09:07:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234464AbiKKOGX (ORCPT ); Fri, 11 Nov 2022 09:06:23 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B49D8A8E6; Fri, 11 Nov 2022 05:59:41 -0800 (PST) Message-ID: <20221111135205.543363889@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Oak79lo/7cHcPMXn18Hj8VarinH9SEGY40y7VRfsAjo=; b=pBqdNgbAzXxUKGKDj7jLQp+M8aHV+AWaaXqgcvSxV4Fof+m+6qNtNARkiEOYaQs3PtUzWR 1hmh5rRhqmQgYwvRWYkWH6Q6J8SkydOIXNsk07GmGyKdl/B7AxwDSDE0X9U1NGwwxwDwv6 YgZ7+WLSHMdAa2sFWlAaUAzVt99uBErWvOG9yx6iA8ykogkwtVmWeyucCeep5E6DUE049k CHNIVaUJg4njEDJi+1nHAm3kAQXQeKQuAD/brmbWZYa7HDxUJ5JykEHrQbL9e5OKvOZWsR DH13DwLpownYGkEqSwnQqgwp9QQlsYL2f442XAmdjEghnbHVI9BaMvXQvevHkg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Oak79lo/7cHcPMXn18Hj8VarinH9SEGY40y7VRfsAjo=; b=mLJW7vo/nLUrPNcPAXXjSyIpq9qHGaPEIyrq6QBonl09L4LHa9MTGtdYktNIsqmLIUIrAL D7El80NCOTi87CAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 05/33] genirq/msi: Split msi_create_irq_domain() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:19 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209016353720805?= X-GMAIL-MSGID: =?utf-8?q?1749209016353720805?= Split the functionality of msi_create_irq_domain() so it can be reused for creating per device irq domains. No functional change. Signed-off-by: Thomas Gleixner --- kernel/irq/msi.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -795,17 +795,10 @@ static void msi_domain_update_chip_ops(s chip->irq_set_affinity = msi_domain_set_affinity; } -/** - * msi_create_irq_domain - Create an MSI interrupt domain - * @fwnode: Optional fwnode of the interrupt controller - * @info: MSI domain info - * @parent: Parent irq domain - * - * Return: pointer to the created &struct irq_domain or %NULL on failure - */ -struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent) +static struct irq_domain *__msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + unsigned int flags, + struct irq_domain *parent) { struct irq_domain *domain; @@ -813,7 +806,7 @@ struct irq_domain *msi_create_irq_domain if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) msi_domain_update_chip_ops(info); - domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0, + domain = irq_domain_create_hierarchy(parent, flags | IRQ_DOMAIN_FLAG_MSI, 0, fwnode, &msi_domain_ops, info); if (domain) { @@ -826,6 +819,21 @@ struct irq_domain *msi_create_irq_domain } /** + * msi_create_irq_domain - Create an MSI interrupt domain + * @fwnode: Optional fwnode of the interrupt controller + * @info: MSI domain info + * @parent: Parent irq domain + * + * Return: pointer to the created &struct irq_domain or %NULL on failure + */ +struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + struct irq_domain *parent) +{ + return __msi_create_irq_domain(fwnode, info, 0, parent); +} + +/** * msi_parent_init_dev_msi_info - Delegate initialization of device MSI info to parent domain * @dev: The device for which the domain should be created * @domain: The domain which delegates From patchwork Fri Nov 11 13:58:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18823 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759149wru; Fri, 11 Nov 2022 06:07:04 -0800 (PST) X-Google-Smtp-Source: AA0mqf6Wy5wKty8bEnMDwLK/fYh7TiaZicyej4qpLk8ZjDiq6CZKHOfZrFvL2UVZffeIvfMn3sdt X-Received: by 2002:a17:90b:2785:b0:211:d22b:9f14 with SMTP id pw5-20020a17090b278500b00211d22b9f14mr2111931pjb.68.1668175624404; Fri, 11 Nov 2022 06:07:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175624; cv=none; d=google.com; s=arc-20160816; b=mPVhB+7LOL0LTBRYuXYkh74WgvEeC2uZq3hXpKR+j4yNoHkTGwSXngy6Sj/NbkFnTg rIk5+S0N4tkhSbjDd4XXu6ByTc/xDb04k6j+rHJb4/Y4azJr63HgSC19PKG9UMoCs2ad wUiXx3YUBA+JkxHhJdMiu2moj5xYDjB7Ckpp7wIzgMr6DOSC+E7PMqEdUZS7vmdKT3xO kTw6sunp73Xm84vF+oTaeLBHF1orDAhoLYZx8fr+l0tlhN1qPZugPoPcZ7QkUc5hzGEV GVfjTD5itoXrnuRFySinrtXGzTm89Z8+LBf9UKo2nB6LKeYHzMdLRuk0BZZnb5mRzdqu K42w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=xdXQN8DRlFx/ul31qn4JSIb+1+AWkLgJWGGnxBYyOqY=; b=vtOhEK7OHhjpcuEOokakqznR8SjS/Vb/aVV3hzSsfY6tGXdTrcW8VuXnZoYX21LLP5 jqVFLs0irwL8AozpS8WYKadQPg86AmNN3fN6KNmkq6W2N55gMvQEi9EOY4tSJiepsw9F V+Q35NscwCy1Rs22LX0DptcHdZ1c85TctMGhM0hLwBqLbUP93mDMY8AdshhVahJMMfng 14LOlFVAWaFjD7GT4SlrPgJLsV6Whd5P4cQDUIaEj3o1P+4PBBUV1nAYmrO4YebK1ZFY U/cA4tXQ/luEDdMJWf7BIx15pJUsod//OosCXNh9k+pjgFczL9mttTZonwLR0FWKxw0a Pu8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WtVC2QIq; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=UYTcQJeb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 140-20020a621692000000b0056bb101f472si2236049pfw.223.2022.11.11.06.06.46; Fri, 11 Nov 2022 06:07:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WtVC2QIq; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=UYTcQJeb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234083AbiKKOFz (ORCPT + 99 others); Fri, 11 Nov 2022 09:05:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234250AbiKKOFc (ORCPT ); Fri, 11 Nov 2022 09:05:32 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 783938B47C; Fri, 11 Nov 2022 05:59:17 -0800 (PST) Message-ID: <20221111135205.601563808@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175101; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xdXQN8DRlFx/ul31qn4JSIb+1+AWkLgJWGGnxBYyOqY=; b=WtVC2QIqbLK6P3xlT6wSY/JDFKu3lLwNilN3JNp6QWP3khbi+wL1jnS3qudRT0exHV45Th AiZuYZQFD2qoXVI6pwnM45xMVYxj8JDFuqsQ0IEdsrmjyBBzNzP+Ws5gnSXnwJKGJEXSAu 1t2hYbGBDr9Srww34ao6RhbukK+QDbiG4urD4dmz88hvUuukH7c8H6uaMEmsyis1izFGtO p0+uQPdOV22UvUt12EuUwkzqJmmi4FC0uNLhkb2i2bHg9IbGA7eDJ6u5wtqZf3DmPTvm9B 3RBDoSYtugSy3lM7gLKl2tK1AeDBhOQu1hhuBVzVLJjQzuEnUo/WcapNeprYLQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175101; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xdXQN8DRlFx/ul31qn4JSIb+1+AWkLgJWGGnxBYyOqY=; b=UYTcQJebJYMtepSbazMw2A4Q5zsWOluoAV6RD556tCbHR6nMrpe/rZqwIzBPiMJmYyliDG f4QET080a9aGrwAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:20 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208923796017044?= X-GMAIL-MSGID: =?utf-8?q?1749208923796017044?= Per device domains require the device pointer of the device which instantiated the domain for some purposes. Add the pointer to struct irq_domain. It will be used in the next step which provides the infrastructure to create per device MSI domains. Signed-off-by: Thomas Gleixner --- include/linux/irqdomain.h | 4 ++++ 1 file changed, 4 insertions(+) --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -132,6 +132,9 @@ struct irq_domain_chip_generic; * @gc: Pointer to a list of generic chips. There is a helper function for * setting up one or more generic chips for interrupt controllers * drivers using the generic chip library which uses this pointer. + * @dev: Pointer to the device which instantiated the irqdomain + * With per device irq domains this is not necessarily the same + * as @pm_dev. * @pm_dev: Pointer to a device that can be utilized for power management * purposes related to the irq domain. * @parent: Pointer to parent irq_domain to support hierarchy irq_domains @@ -155,6 +158,7 @@ struct irq_domain { struct fwnode_handle *fwnode; enum irq_domain_bus_token bus_token; struct irq_domain_chip_generic *gc; + struct device *dev; struct device *pm_dev; #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY struct irq_domain *parent; From patchwork Fri Nov 11 13:58:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18824 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759200wru; Fri, 11 Nov 2022 06:07:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf6x78I9MOW/2fIoGDS1uVBplpHTJ9t+WhwvmDZ7i3uk1L0iI83CNrCzxNsZkB5xC8pdSjOJ X-Received: by 2002:a17:90a:9a8f:b0:212:9625:c8e9 with SMTP id e15-20020a17090a9a8f00b002129625c8e9mr2097299pjp.128.1668175628884; Fri, 11 Nov 2022 06:07:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175628; cv=none; d=google.com; s=arc-20160816; b=nWmL3eQXy62krb39pd1BCkK2oOLHUKRfAEXHjmzXZnrQ0L1ogDukv80/lWMSJzVh/O DHn52pPnG7yTlKWjRCa+AIbEW4AFdHWcm5hlVqvFUZL3l24S3uJql20lR2TLtyjCHujR /TWxH3aEAqNTXvBg/6NHtD5cl5NMwkCj5HXZZJPf9KbsH1QSQJMim91F0rxePYIkjRlY sly1qxq0RxCAXrmQuLX+SsaEjKHvpJACDn886Yn21D080VIq2psmGbQlwTMoHgNvhlyi +cSvMsev32dvdJnKiC3F7dUmUolJ+nsw2bEF9TmfA5cDwYwEcjMv4/R+2+pPZm0xXOAa W9sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=9djoTnmW2VtqTMdaiZC8X9Gnafs0aQyZvLVu/huu2eY=; b=bSYCrWUOLC7UiWVpBPUHTf91R+fd1K0SybWielk1iwpgeskFKPEMMdF8m1DImINuTr Q47DuOti2IRXw3m2bOWPuVGPx6FHy/bhP/2N7HA+Gqt+2PGls8blLoNWutdu7+nRFzh1 43aw/oaKTklV3lSrQ0C9dDDXTg3f8EE72ZGCscZZgKglSSq+o/kCjludne7MOU34/QtU LXvqSJKDLnyjxgv4AkvOnR8J2lmrfQoH23vQqJpOXe3EkJd1gVyzr+qivjLeEA8/lAeK SUikZ4h+5KTFHnpeNBSfJxXKgC8SLX0uKTku+bmKDjZUQAmgVf/cSWjTGA4j+EyxjcCX bcYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=u3GZ9jOy; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j9-20020aa78dc9000000b005668645daebsi2179215pfr.111.2022.11.11.06.06.53; Fri, 11 Nov 2022 06:07:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=u3GZ9jOy; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234352AbiKKOGB (ORCPT + 99 others); Fri, 11 Nov 2022 09:06:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234285AbiKKOFl (ORCPT ); Fri, 11 Nov 2022 09:05:41 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9846E8B2C7; Fri, 11 Nov 2022 05:59:17 -0800 (PST) Message-ID: <20221111135205.658112153@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=9djoTnmW2VtqTMdaiZC8X9Gnafs0aQyZvLVu/huu2eY=; b=u3GZ9jOyY697Umvm6Bz8b77Vr10iY59IVHLL7RWVSAz+ip6JECS/SJRThTpobNZxb6uiap O2Crja51Es4Pge/PZRg8dATgOjNJpPUIc+ZRHX+MSWlUH6AS/2YxaXFrLvefFpjkZgyS3j TXBf04VWVaKQ9mohx1RkfKrK3GW9iDM1ZnU/cbjdHEgtoHl8xbe+zNplYyJA9TfDrf3ODI iV3y9MEw79iqf3nFdaQ9dXGHVhbHCmpt/mWVXMs3iFAcpmb/zY/Vv6evXK78mP7nO/b0pv YizNZfVMly6DmACKEB3IURNPZzcRa89ptiItf1tNYeId1h88yY/otRQzUuNUVg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=9djoTnmW2VtqTMdaiZC8X9Gnafs0aQyZvLVu/huu2eY=; b=jp7f4Xus9IpGRuTKh8gJZ2gBs16nAevYOaKBKHy0wvF5NlHAb1kZ29AslIPptmRPs4LKfB 4eKSp/7lSfUzlBDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:22 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208928658586405?= X-GMAIL-MSGID: =?utf-8?q?1749208928658586405?= Now that all prerequsites are in place, provide the actual interfaces for creating and removing per device interrupt domains. MSI device interrupt domains are created from the provided msi_domain_template which is duplicated so that it can be modified for the particular device. The name of the domain and the name of the interrupt chip are composed by "$(PREFIX)$(CHIPNAME)-$(DEVNAME)" $PREFIX: The optional prefix provided by the underlying MSI parent domain via msi_parent_ops::prefix. $CHIPNAME: The name of the irq_chip in the template $DEVNAME: The name of the device The domain is further initialized through a MSI parent domain callback which fills in the required functionality for the parent domain or domains further down the hierarchy. This initialization can fail, e.g. when the requested feature or MSI domain type cannot be supported. The domain pointer is stored in the pointer array inside of msi_device_data which is attached to the domain. The domain can be removed via the API or left for disposal via devres when the device is torn down. The API removal is useful e.g. for PCI to have seperate domains for MSI and MSI-X, which are mutually exclusive and always occupy the default domain id slot. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 6 ++ kernel/irq/msi.c | 142 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -531,6 +531,12 @@ struct irq_domain *msi_create_irq_domain struct msi_domain_info *info, struct irq_domain *parent); +bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, + const struct msi_domain_template *template, + unsigned int hwsize, void *domain_data, + void *chip_data); +void msi_remove_device_irq_domain(struct device *dev, unsigned int domid); + int msi_domain_alloc_irqs_range_locked(struct device *dev, unsigned int domid, unsigned int first, unsigned int last); int msi_domain_alloc_irqs_range(struct device *dev, unsigned int domid, --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -52,6 +52,14 @@ static inline void msi_setup_default_irq md->__irqdomains[MSI_DEFAULT_DOMAIN] = dev->msi.domain; } +static inline void msi_remove_device_irqdomains(struct device *dev, struct msi_device_data *md) +{ + int domid; + + for (domid = 0; domid < MSI_MAX_DEVICE_IRQDOMAINS; domid++) + msi_remove_device_irq_domain(dev, domid); +} + static int msi_get_domain_base_index(struct device *dev, unsigned int domid) { lockdep_assert_held(&dev->msi.data->mutex); @@ -281,6 +289,7 @@ static void msi_device_data_release(stru { struct msi_device_data *md = res; + msi_remove_device_irqdomains(dev, md); WARN_ON_ONCE(!xa_empty(&md->__store)); xa_destroy(&md->__store); dev->msi.data = NULL; @@ -869,6 +878,139 @@ bool msi_parent_init_dev_msi_info(struct return parent->msi_parent_ops->init_dev_msi_info(dev, parent, real_parent, info); } +/** + * msi_create_device_irq_domain - Create a device MSI interrupt domain + * @dev: Pointer to the device + * @domid: Domain id + * @template: MSI domain info bundle used as template + * @hwsize: Maximum number of MSI table entries (0 if unknown or unlimited) + * @domain_data: Optional pointer to domain specific data which is set in + * msi_domain_info::data + * @chip_data: Optional pointer to chip specific data which is set in + * msi_domain_info::chip_data + * + * Return: True on success, false otherwise + * + * There is no firmware node required for this interface because the per + * device domains are software constructs which are actually closer to the + * hardware reality than any firmware can describe them. + * + * The domain name and the irq chip name for a MSI device domain are + * composed by: "$(PREFIX)$(CHIPNAME)-$(DEVNAME)" + * + * $PREFIX: Optional prefix provided by the underlying MSI parent domain + * via msi_parent_ops::prefix. If that pointer is NULL the prefix + * is empty. + * $CHIPNAME: The name of the irq_chip in @template + * $DEVNAME: The name of the device + * + * This results in understandable chip names and hardware interrupt numbers + * in e.g. /proc/interrupts + * + * PCI-MSI-0000:00:1c.0 0-edge Parent domain has no prefix + * IR-PCI-MSI-0000:00:1c.4 0-edge Same with interrupt remapping prefix 'IR-' + * + * IR-PCI-MSIX-0000:3d:00.0 0-edge Hardware interrupt numbers reflect + * IR-PCI-MSIX-0000:3d:00.0 1-edge the real MSI-X index on that device + * IR-PCI-MSIX-0000:3d:00.0 2-edge + * + * On IMS domains the hardware interrupt number is either a table entry + * index or a purely software managed index but it is guaranteed to be + * unique. + * + * The domain pointer is stored in @dev::msi::data::__irqdomains[]. All + * subsequent operations on the domain depend on the domain id. + * + * The domain is automatically freed when the device is removed via devres + * in the context of @dev::msi::data freeing, but it can also be + * independently removed via @msi_remove_device_irq_domain(). + */ +bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, + const struct msi_domain_template *template, + unsigned int hwsize, void *domain_data, + void *chip_data) +{ + struct irq_domain *domain, *parent = dev->msi.domain; + const struct msi_parent_ops *pops; + struct msi_domain_template *bundle; + struct fwnode_handle *fwnode; + + if (!irq_domain_is_msi_parent(parent)) + return false; + + if (domid >= MSI_MAX_DEVICE_IRQDOMAINS) + return false; + + bundle = kmemdup(template, sizeof(*bundle), GFP_KERNEL); + if (!bundle) + return false; + + bundle->info.hwsize = hwsize ? hwsize : MSI_MAX_INDEX; + bundle->info.chip = &bundle->chip; + bundle->info.ops = &bundle->ops; + bundle->info.data = domain_data; + bundle->info.chip_data = chip_data; + + pops = parent->msi_parent_ops; + snprintf(bundle->name, sizeof(bundle->name), "%s%s-%s", + pops->prefix ? : "", bundle->chip.name, dev_name(dev)); + bundle->chip.name = bundle->name; + + fwnode = irq_domain_alloc_named_fwnode(bundle->name); + if (!fwnode) + goto free_bundle; + + msi_lock_descs(dev); + + if (WARN_ON_ONCE(msi_get_device_domain(dev, domid))) + goto fail; + + if (!pops->init_dev_msi_info(dev, parent, parent, &bundle->info)) + goto fail; + + domain = __msi_create_irq_domain(fwnode, &bundle->info, IRQ_DOMAIN_FLAG_MSI_DEVICE, parent); + if (!domain) + goto fail; + + domain->dev = dev; + dev->msi.data->__irqdomains[domid] = domain; + msi_unlock_descs(dev); + return true; + +fail: + msi_unlock_descs(dev); + kfree(fwnode); +free_bundle: + kfree(bundle); + return false; +} + +/** + * msi_remove_device_irq_domain - Free a device MSI interrupt domain + * @dev: Pointer to the device + * @domid: Domain id + */ +void msi_remove_device_irq_domain(struct device *dev, unsigned int domid) +{ + struct msi_domain_info *info; + struct irq_domain *domain; + + msi_lock_descs(dev); + + domain = msi_get_device_domain(dev, domid); + + if (!domain || !irq_domain_is_msi_device(domain)) + goto unlock; + + dev->msi.data->__irqdomains[domid] = NULL; + info = domain->host_data; + irq_domain_remove(domain); + kfree(container_of(info, struct msi_domain_template, info)); + +unlock: + msi_unlock_descs(dev); +} + int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *arg) { From patchwork Fri Nov 11 13:58:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18836 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760616wru; Fri, 11 Nov 2022 06:09:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf5KO9TAaFE0z1ZRslAwZ1b3Lfx4GfXugGDaA43yfU5a0v8cCfKXOUxwr/7V1skKX5DtpUV1 X-Received: by 2002:a17:906:7e4e:b0:7a8:3ecb:bd62 with SMTP id z14-20020a1709067e4e00b007a83ecbbd62mr1938239ejr.721.1668175751384; Fri, 11 Nov 2022 06:09:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175751; cv=none; d=google.com; s=arc-20160816; b=NhejligVGflxIXE4J/xx54ykXUJ/EV/PXX1CMLffHbrN1ozI4dAOZMewfllj+RT0oX xG0t8pq9G0GPn4ltTLDYGlPOqZT0dDt9dw5Qx8MMY3R4ln+ByriSCjV18Sq48DoT0pCg S1rMuGWmaSiAs3Vn/FTnfLvlbzt4SKL4DfQwp1bDuENnTo4uHuw6MjnoLiyy8bL7UtoS /P+uqUmnRr8nDzEr4BdU/O+9Jt1B00uIkzOjgF/AUcfeKua6Pcy3LeaCyUUZTknNHRxh QNKiAw0gX/W4RuR9AYYX4r4IPX9KdDvJaYTzvbQHX+GRo3/FGLrx3AYciOA6MAWkzsp+ upGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=6sl/l9myt20lNdigYL4yWzzuJo6j8gI/Xo6NnbnNhEc=; b=X9ReDV5pcMyG3A+p44L96tsRrhlZUtTYqajkweoyGUrsGiaQU5OS/5E3RBP+S9Yhbh Hx0BjapHlvFahLViq21ORQpd+jF+qnSCjSscw3Rl9o5OwtOmH1GAbNzOc1eusHWiphGC vba9mgxbhiQNNS42cxJsjrL7NQdJyjzNuZ4nI5EPNOaswIQp9GTXmBgXwh5oQ8rXvIRe cB/ZEGC+jMy/94JfE+d4KcjzuZP7EEr7429kM7YP5ZyuD668ljiHO3Rdts0/3z0g/QvX LZs5faCk9tIE1OefU8bVfuHL9EE2KIOQ5MWJIsf0IXsOdmwBBTY910F5ntWBpY24SnnC jlgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=CUXpw24Z; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 08/33] genirq/msi: Provide msi_match_device_domain() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:23 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209056744371866?= X-GMAIL-MSGID: =?utf-8?q?1749209056744371866?= Provide an interface to match a per device domain bus token. This allows to query which type of domain is installed for a particular domain id. Will be used for PCI to avoid frequent create/remove cycles for the MSI resp. MSI-X domains. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 3 +++ kernel/irq/msi.c | 25 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -537,6 +537,9 @@ bool msi_create_device_irq_domain(struct void *chip_data); void msi_remove_device_irq_domain(struct device *dev, unsigned int domid); +bool msi_match_device_irq_domain(struct device *dev, unsigned int domid, + enum irq_domain_bus_token bus_token); + int msi_domain_alloc_irqs_range_locked(struct device *dev, unsigned int domid, unsigned int first, unsigned int last); int msi_domain_alloc_irqs_range(struct device *dev, unsigned int domid, --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1011,6 +1011,31 @@ void msi_remove_device_irq_domain(struct msi_unlock_descs(dev); } +/** + * msi_match_device_irq_domain - Match a device irq domain against a bus token + * @dev: Pointer to the device + * @domid: Domain id + * @bus_token: Bus token to match against the domain bus token + * + * Return: True if device domain exists and bus tokens match. + */ +bool msi_match_device_irq_domain(struct device *dev, unsigned int domid, + enum irq_domain_bus_token bus_token) +{ + struct msi_domain_info *info; + struct irq_domain *domain; + bool ret = false; + + msi_lock_descs(dev); + domain = msi_get_device_domain(dev, domid); + if (domain && irq_domain_is_msi_device(domain)) { + info = domain->host_data; + ret = info->bus_token == bus_token; + } + msi_unlock_descs(dev); + return ret; +} + int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *arg) { From patchwork Fri Nov 11 13:58:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18825 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759225wru; Fri, 11 Nov 2022 06:07:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf7aRsVyXB0RMAQP82S5V2tY0XfLG5NGdhy5WGIwrrUUK9hqgsaFZgD2/cmKp5IVT+NGK9/9 X-Received: by 2002:a17:902:a983:b0:186:def0:4886 with SMTP id bh3-20020a170902a98300b00186def04886mr2343670plb.152.1668175631153; Fri, 11 Nov 2022 06:07:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175631; cv=none; d=google.com; s=arc-20160816; b=hs/Pgj446bRC4lyJdoDy6N+Ga68c0I4EQOsPdGBYetmgSo7AXQj/f0brxJugRbvIKt Z4V1tWmpt6Vicy5cuI1R1Ji4c2V7pj2oquUYjZ9ii0vXKJXqLiopIbdt9/qA3FXrzwbS BaTsEuG3yvc87YIohppdensdaqf0ixn0zE4NAhhRuJjxez4U8bjReoyicD6iHuc/kxEf FZsQ/0rCbo4oyHnpp/Gh/dHUy3F81/Fy2sIB5DJqhEcN5viayq6W5u2YOtl74GD+HHZo 5EZofpDLPVuQj3qDUJczWBktspg5JP7zIUapbrxkCg8pHFloOO0Z7pWeQOdMHrQ9E7dQ 5xLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=EEWX0fbjpip4mXWc4fSurpBy9Wsz+XqDUPDSbTVukvY=; b=nhCaQtUZzK9hxUdLfc3FA1DynBeyjGwOoKPCxei2vDSuG5Z+nxryS1+kX8YLNqK7UF z9l+xX7nlYorxs/RbL/d8AG6vGBxThFtS53OFQ4G7CL1sTa3mKgqplkpTQdXoW7DSbZ/ fbZwkpQTP8r1OU2dWtWk+AXylZQt8gJIpoZyBh6wqYTC6XRO2nwX7v7sKiI9+OQNoOz/ OsPLs2Dt/citxKNwjKI6pF2/9IOCcLHCfj4hr54bEp2sv+OWrrn/GKg0MB2WDzmeiVsm PrVheJBvNo8KGfzhbL+IeIlamnMP5qrWExGXB4pMH89lLK9wqzubUeOxDbAKSrNnbCZb sEPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=VugTZQCc; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q11-20020a170902f78b00b001869347b0besi2779371pln.174.2022.11.11.06.06.56; Fri, 11 Nov 2022 06:07:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=VugTZQCc; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234450AbiKKOGD (ORCPT + 99 others); Fri, 11 Nov 2022 09:06:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234387AbiKKOFl (ORCPT ); Fri, 11 Nov 2022 09:05:41 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D72877E4A; Fri, 11 Nov 2022 05:59:18 -0800 (PST) Message-ID: <20221111135205.775535289@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175106; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EEWX0fbjpip4mXWc4fSurpBy9Wsz+XqDUPDSbTVukvY=; b=VugTZQCcKm2vyhQ8cIixt7Lppk9UkraAxMIl07e4x+0S3mrioeGKqoxRRpo5MU0J44GBn8 bVkn6sZ9Tq4gCMxxNqqAHmFikMJ33iCaQ4Clqy9Q+gXf92CzwA1yc+R/qF52YrAOTsFFBA 3PyidW83A9h0Q9TyNAf5Z2A3xn/fJd7rkzsduR37j0NrMoCUagaHeu8diaXqZBm339Lt7+ Eyi/J/naPloOoJdiVLKVEgwwAR/EhENSRoqXIqR38SO94BrOXkVmAQ3BbHjalcxIcdl7Io ZTssvnw85QgcFbq7iwEz5fjiCrkWYuuYoOrDNkf+0vobz1AALtX9yHCyVi5iUQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175106; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EEWX0fbjpip4mXWc4fSurpBy9Wsz+XqDUPDSbTVukvY=; b=s8GluLF0Wl8kSe3/ZS0ctqdVE5ewnU85knLEVp2iCmxGJHcglo9BsWpZzgWzSgNx3Ca51Z IlOVO5jXY5bdnfDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 09/33] genirq/msi: Add range checking to msi_insert_desc() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:25 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208930627161688?= X-GMAIL-MSGID: =?utf-8?q?1749208930627161688?= Per device domains provide the domain size to the core code. This allows range checking on insertion of MSI descriptors and also paves the way for dynamic index allocations which are required e.g. for IMS. This avoids external mechanisms like bitmaps on the device side and just utilizes the core internal MSI descriptor store for it. Signed-off-by: Thomas Gleixner --- kernel/irq/msi.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -73,6 +73,7 @@ static int msi_get_domain_base_index(str return domid * MSI_XA_DOMAIN_SIZE; } +static unsigned int msi_domain_get_hwsize(struct device *dev, unsigned int domid); /** * msi_alloc_desc - Allocate an initialized msi_desc @@ -115,6 +116,7 @@ static int msi_insert_desc(struct device unsigned int domid, unsigned int index) { struct msi_device_data *md = dev->msi.data; + unsigned int hwsize; int baseidx, ret; baseidx = msi_get_domain_base_index(dev, domid); @@ -123,6 +125,12 @@ static int msi_insert_desc(struct device goto fail; } + hwsize = msi_domain_get_hwsize(dev, domid); + if (index >= hwsize) { + ret = -ERANGE; + goto fail; + } + desc->msi_index = index; index += baseidx; ret = xa_insert(&md->__store, index, desc, GFP_KERNEL); @@ -181,9 +189,11 @@ static bool msi_desc_match(struct msi_de static bool msi_ctrl_valid(struct device *dev, struct msi_ctrl *ctrl) { + unsigned int hwsize = msi_domain_get_hwsize(dev, ctrl->domid); + if (WARN_ON_ONCE(ctrl->first > ctrl->last || - ctrl->first >= MSI_MAX_INDEX || - ctrl->last >= MSI_MAX_INDEX)) + ctrl->first >= hwsize || + ctrl->last >= hwsize)) return false; return true; } @@ -613,6 +623,25 @@ static struct irq_domain *msi_get_device return domain; } +static unsigned int msi_domain_get_hwsize(struct device *dev, unsigned int domid) +{ + struct msi_domain_info *info; + struct irq_domain *domain; + + /* + * Retrieve the MSI domain for range checking. If there is no + * domain or the domain is not a per device domain, then assume + * full MSI range and pray that the calling subsystem knows what it + * is doing. + */ + domain = msi_get_device_domain(dev, domid); + if (domain && irq_domain_is_msi_device(domain)) { + info = domain->host_data; + return info->hwsize; + } + return MSI_MAX_INDEX; +} + static inline void irq_chip_write_msi_msg(struct irq_data *data, struct msi_msg *msg) { @@ -1380,7 +1409,7 @@ int msi_domain_alloc_irqs_all_locked(str struct msi_ctrl ctrl = { .domid = domid, .first = 0, - .last = MSI_MAX_INDEX, + .last = msi_domain_get_hwsize(dev, domid) - 1, .nirqs = nirqs, }; @@ -1496,7 +1525,8 @@ void msi_domain_free_irqs_range(struct d */ void msi_domain_free_irqs_all_locked(struct device *dev, unsigned int domid) { - msi_domain_free_irqs_range_locked(dev, domid, 0, MSI_MAX_INDEX); + msi_domain_free_irqs_range_locked(dev, domid, 0, + msi_domain_get_hwsize(dev, domid) - 1); } /** From patchwork Fri Nov 11 13:58:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18833 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760304wru; Fri, 11 Nov 2022 06:08:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf7Q5b3eTYppW76WYVhQ1vRgFc3mvemRiAF509mOrjvxcajy64zN/eBt+iJ2ky8RreRNAD5U X-Received: by 2002:a63:114b:0:b0:470:5b0d:b50e with SMTP id 11-20020a63114b000000b004705b0db50emr1730535pgr.488.1668175722009; Fri, 11 Nov 2022 06:08:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175722; cv=none; d=google.com; s=arc-20160816; b=hJSJPBzVTMEvIVrhth/YrbmNjmVr4pvAiC0N809/pIWcGYmmlPtzYMJsiFcfCyM2+i vGY2FnPnPB27ELbmcmDre8Vk6JWSk4eQDaJRdLjJ5TjGPQW2RV0VPdIrpLabxly5zQVK vd+mzqo589qGJfg0c7QGkzH/TGlKXMRp6PgQ7j1LLJ/EeBpuP39PZGle7sJMx0gRpL7z RotsxUJPKC/YsYkVFVm91jFfXZv4IADpO9lR7z/Z9rx7r++YkfVIT0rdylR4jB13CwUi GPTVUrpKFVyWXMPuevVAlm6yVco1mLK47a9BSgWc8ZtmjAl8axiJD8CUnDrExGu6p4tG jK9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=IySA7q2kc9s+Hs2L8EoPsrfP4Hl32p6yL0Sk0XoI7lE=; b=zcZPERIHrjlMNlC4THEr3aImnXSR8GZIWakX3K9GhgsK+ooBL+OzDOEqV3Klnzu+8f aaAjNExwO3VP1hqyN6sWwV3tde3246vu4c1/ZOhyvaWghXva4IBJGrwTkqhfiE8SGkZ1 eMaQsTnoR45ttjvpbP0u+tKpnvNqnOhLs/PdunpEMjzHQQqz7aVihohXQcQu8KWC5Anj zReNo9ezhI3y/aQ9VZEVMjtw1DVX2SFIFx3NHHxfdWT08o3vNL26PGGD63lD4GpID2qk yLuZ9R8NcHR7YiBiYOxDscytm0OTlXfmywzstKlUuUUXeTQH+i+1bneYfVFAk98wvI2+ yEcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=JhXIZ3xs; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c20-20020a170902b69400b0018875b7692esi2372529pls.456.2022.11.11.06.08.28; Fri, 11 Nov 2022 06:08:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=JhXIZ3xs; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234344AbiKKOH5 (ORCPT + 99 others); Fri, 11 Nov 2022 09:07:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234506AbiKKOHB (ORCPT ); Fri, 11 Nov 2022 09:07:01 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE2E48BA88; Fri, 11 Nov 2022 05:59:50 -0800 (PST) Message-ID: <20221111135205.836259395@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IySA7q2kc9s+Hs2L8EoPsrfP4Hl32p6yL0Sk0XoI7lE=; b=JhXIZ3xsgiGBibsCVxO6poVIfqA3RfwjsYLK6ETSgHmOBOnf5lZkYicqflqh4WKiAHTvbE tb77jodb251i75+vdbnBVrFd1xap2qLNb8EnYl09l/gQr1BKA8LyQOxGDUDJ0SAeQ5xbfL nb3HjnkMhdlldRQrseLQwCxqopB96aa+3px1xjzEYCzOR/8aqKLoiRl2bNTlEeZOYVy9MF YQwtbyIgmY7bRlOqKni3FAFVxyW6Xo9XbFvsnQA89gJsVec57EkqJunAok4tXo3JsY9rsp sKoFm95RLojk+LWAC16cKgADNk0kDD9DfPqAPtx86VcTSa0IOjA3vuSDKwWTXQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IySA7q2kc9s+Hs2L8EoPsrfP4Hl32p6yL0Sk0XoI7lE=; b=xlQZ+n5DInBwbdrr1qkyYkeaiT8YEj8UaNfj+sy/2EmMN33nWc8Ei0pO6FAJYG1FlmPaYo DkCche6zOoSLFwAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 10/33] PCI/MSI: Split __pci_write_msi_msg() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:27 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209026208773320?= X-GMAIL-MSGID: =?utf-8?q?1749209026208773320?= The upcoming per device MSI domains will create different domains for MSI and MSI-X. Split the write message function into MSI and MSI-X helpers so they can be used by those new domain functions seperately. Signed-off-by: Ahmed S. Darwish Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/msi.c | 104 +++++++++++++++++++++++++------------------------- 1 file changed, 54 insertions(+), 50 deletions(-) --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -180,6 +180,58 @@ void __pci_read_msi_msg(struct msi_desc } } +static inline void pci_write_msg_msi(struct pci_dev *dev, struct msi_desc *desc, + struct msi_msg *msg) +{ + int pos = dev->msi_cap; + u16 msgctl; + + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); + msgctl &= ~PCI_MSI_FLAGS_QSIZE; + msgctl |= desc->pci.msi_attrib.multiple << 4; + pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); + + pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, msg->address_lo); + if (desc->pci.msi_attrib.is_64) { + pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, msg->address_hi); + pci_write_config_word(dev, pos + PCI_MSI_DATA_64, msg->data); + } else { + pci_write_config_word(dev, pos + PCI_MSI_DATA_32, msg->data); + } + /* Ensure that the writes are visible in the device */ + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); +} + +static inline void pci_write_msg_msix(struct msi_desc *desc, struct msi_msg *msg) +{ + void __iomem *base = pci_msix_desc_addr(desc); + u32 ctrl = desc->pci.msix_ctrl; + bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); + + if (desc->pci.msi_attrib.is_virtual) + return; + /* + * The specification mandates that the entry is masked + * when the message is modified: + * + * "If software changes the Address or Data value of an + * entry while the entry is unmasked, the result is + * undefined." + */ + if (unmasked) + pci_msix_write_vector_ctrl(desc, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT); + + writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); + writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); + writel(msg->data, base + PCI_MSIX_ENTRY_DATA); + + if (unmasked) + pci_msix_write_vector_ctrl(desc, ctrl); + + /* Ensure that the writes are visible in the device */ + readl(base + PCI_MSIX_ENTRY_DATA); +} + void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { struct pci_dev *dev = msi_desc_to_pci_dev(entry); @@ -187,63 +239,15 @@ void __pci_write_msi_msg(struct msi_desc if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) { /* Don't touch the hardware now */ } else if (entry->pci.msi_attrib.is_msix) { - void __iomem *base = pci_msix_desc_addr(entry); - u32 ctrl = entry->pci.msix_ctrl; - bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); - - if (entry->pci.msi_attrib.is_virtual) - goto skip; - - /* - * The specification mandates that the entry is masked - * when the message is modified: - * - * "If software changes the Address or Data value of an - * entry while the entry is unmasked, the result is - * undefined." - */ - if (unmasked) - pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT); - - writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); - writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); - writel(msg->data, base + PCI_MSIX_ENTRY_DATA); - - if (unmasked) - pci_msix_write_vector_ctrl(entry, ctrl); - - /* Ensure that the writes are visible in the device */ - readl(base + PCI_MSIX_ENTRY_DATA); + pci_write_msg_msix(entry, msg); } else { - int pos = dev->msi_cap; - u16 msgctl; - - pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); - msgctl &= ~PCI_MSI_FLAGS_QSIZE; - msgctl |= entry->pci.msi_attrib.multiple << 4; - pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); - - pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, - msg->address_lo); - if (entry->pci.msi_attrib.is_64) { - pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, - msg->address_hi); - pci_write_config_word(dev, pos + PCI_MSI_DATA_64, - msg->data); - } else { - pci_write_config_word(dev, pos + PCI_MSI_DATA_32, - msg->data); - } - /* Ensure that the writes are visible in the device */ - pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); + pci_write_msg_msi(dev, entry, msg); } -skip: entry->msg = *msg; if (entry->write_msi_msg) entry->write_msi_msg(entry, entry->write_msi_msg_data); - } void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) From patchwork Fri Nov 11 13:58:28 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e21-20020a170902d39500b001841134e3b1si2337520pld.160.2022.11.11.06.07.53; Fri, 11 Nov 2022 06:08:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=adlIU4bj; dkim=neutral (no key) header.i=@linutronix.de header.b=tfuw4bF7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234406AbiKKOG0 (ORCPT + 99 others); Fri, 11 Nov 2022 09:06:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234385AbiKKOFz (ORCPT ); Fri, 11 Nov 2022 09:05:55 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 986DA8A8D0; Fri, 11 Nov 2022 05:59:29 -0800 (PST) Message-ID: <20221111135205.894005975@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175109; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3hBKls93a/oZusIKCQSu9YxAwv+FEeKpjbXGqebGohY=; b=adlIU4bjQ02+ZbMdWRRPr+H6SzVbhvjFVfg1F9DMtTtRGLSTJOMT2LiCGhgy19EV6HJDZu LIjodpiR7vzOalFi95tVMV57B2WHvI/xUKtvJEitivW3IuQlAqskjo5pCCMMsgqUMerf8c lT7NpHFOL7LCsNKZ1VWQjaFzSRT+Ql9m1o/8/oSV4c6ClqZ57JYCPwHCmg9Ad+JQdSt8BV krwWqUJrdXXsCU8YS9FPW2EutNGYUNwIGoDivhs7ncYnkeKOm6e00rVSwFVtNVgyzH4lR9 8mDqYiP/hnTBsKGSgris0FWbBd2SzxDgg3nQnaxsyOPfVVZWx3I85fFelPw4Hw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175109; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3hBKls93a/oZusIKCQSu9YxAwv+FEeKpjbXGqebGohY=; b=tfuw4bF7JvEpa0OcCIZ/z2kSL1cmbg+B01s/ZCAa5lqd2Eh7DG3POQBGQx9Sha8mpG1PRc 9xrOGJt+05ILCqBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:28 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208991187842363?= X-GMAIL-MSGID: =?utf-8?q?1749208991187842363?= Provide new bus tokens for the upcoming per device PCI/MSI and PCI/MSIX interrupt domains. Signed-off-by: Thomas Gleixner --- include/linux/irqdomain_defs.h | 2 ++ kernel/irq/msi.c | 4 ++++ 2 files changed, 6 insertions(+) --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -21,6 +21,8 @@ enum irq_domain_bus_token { DOMAIN_BUS_TI_SCI_INTA_MSI, DOMAIN_BUS_WAKEUP, DOMAIN_BUS_VMD_MSI, + DOMAIN_BUS_PCI_DEVICE_MSI, + DOMAIN_BUS_PCI_DEVICE_MSIX, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1137,6 +1137,8 @@ static bool msi_check_reservation_mode(s switch(domain->bus_token) { case DOMAIN_BUS_PCI_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: case DOMAIN_BUS_VMD_MSI: break; default: @@ -1162,6 +1164,8 @@ static int msi_handle_pci_fail(struct ir { switch(domain->bus_token) { case DOMAIN_BUS_PCI_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: case DOMAIN_BUS_VMD_MSI: if (IS_ENABLED(CONFIG_PCI_MSI)) break; From patchwork Fri Nov 11 13:58:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18827 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759915wru; Fri, 11 Nov 2022 06:08:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf5phNsdedy5VNTTwjvsn1klhQA3Ekc5lP+PXR7bliUMhv8isePw0+3ykIwLc5rc+aUtACW1 X-Received: by 2002:a63:fc56:0:b0:46f:584c:7631 with SMTP id r22-20020a63fc56000000b0046f584c7631mr1769670pgk.592.1668175689232; Fri, 11 Nov 2022 06:08:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175689; cv=none; d=google.com; s=arc-20160816; b=Vl2F0GXliXl9f+SyvqPB7DJck5I37fsK+12pRMWRJ4BrceSFYPXFMiSkcqukAlnibg UcRsKNosrCntEo1vEbMu6Ty5yAXavfz+gdYCRyJVP739bY6kjwqT5HF7C2tZI4ZedtCW MsnC4boOVou/3bNnVFezBv5sDNvb0oGjBf2h8QrQSjkJyisY04meLOdZ4p0qYTpiCwU5 TwZDeO1LTRwJnFDzskmyYMB+h1MqS0MgKtSQQQQYs4DFyH3vh2Mfrv1+gFgdOu5GFb8Z yGKU+8iUxMY1xa0505LZwX3bhXh84PzBbWSpfJTTMvH9CQsT4URwaa5BOpRWd9gDJMaf d+6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=x1IMu0Csh8ECW9MxnY8YD9z+cs0Y5WVkthejRMBK+cA=; b=JAOOlZDmhlr2o8pkxU2h9kLxn+hbl1AKyqtTxZcHr6dVucxwr1DGH3W+onBkU125Z/ oVMIjboIFp4tLdNuAhLZsJO6bEPZfkzY8vm2/SbAV89biuatc1exdCzwgsCFAeQvseVo c3BcMhF4+qZV2MwnQKY61d1UTIiubHLrtoWc4k5cJuVRWlnVN1M4utP11tD64RBMOdTg 4oZd80xelpomqmMm1Ncuw4mesISMh3Wu7HLPJgIxMhnHhizuQojdCWst/mwh/4Z1+tqC bTNd7EDokIFEmbebAp+PUVS7K0lh2Wg9Sueg72TRoCBIqm6bBnQRiTfmw2JehYH1VAQF eT4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZE03glJM; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="4+O+T2/A"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d190-20020a6336c7000000b0046eb96c4f90si2739689pga.549.2022.11.11.06.07.55; Fri, 11 Nov 2022 06:08:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZE03glJM; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="4+O+T2/A"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234302AbiKKOG3 (ORCPT + 99 others); Fri, 11 Nov 2022 09:06:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234241AbiKKOFz (ORCPT ); Fri, 11 Nov 2022 09:05:55 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4813D8C58A; Fri, 11 Nov 2022 05:59:29 -0800 (PST) Message-ID: <20221111135205.951710169@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175110; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=x1IMu0Csh8ECW9MxnY8YD9z+cs0Y5WVkthejRMBK+cA=; b=ZE03glJMvdrzKcgza7Wn88G/a/ews/BMK4pBuw2g/ddeOTiYmC2aDptFXHDOOMO3KjRiH2 R3JNsM48FlRTpy0acKzP8KTJBayvI3nGTl6SVmLGQJCFGEz6EBxhmI7xewzs5QfvDtJ2t9 kUpvydo5aEGuYKPoZ7Zew2sKyPPtUo70bxnV0U2xdgaB3Qw7IJFra81E6+fDlwEGOUHU6p Z4Al8OaBoYiQAXRzSTgCYg0BkR4fMuR04w4A7uJEKsxdFZEmR7H6cxC425DUT4AWv6hX/B Ytoi0JRYnlBSNpWUot99sSpb/1JMUgSdHa9eT90Thy1+0aPEGrFgZSDZvlYMBw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175110; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=x1IMu0Csh8ECW9MxnY8YD9z+cs0Y5WVkthejRMBK+cA=; b=4+O+T2/Aozdf5x1cMpzV7wOmObZzbEUangXFWBGWR/c8GevY+2k5KH5pkOoFQ+RLfh5cAS yU+t979f9izrz1CA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 12/33] PCI/MSI: Add support for per device MSI[X] domains References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:30 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208991799564278?= X-GMAIL-MSGID: =?utf-8?q?1749208991799564278?= Provide a template and the necessary callbacks to create PCI/MSI and PCI/MSI-X domains. The domains are created when MSI or MSI-X is enabled. The domains lifetime is either the device life time or in case that e.g. MSI-X was tried first and failed, then the MSI-X domain is removed and a MSI domain is created as both are mutually exclusive and reside in the default domain id slot of the per device domain pointer array. Also expand pci_msi_domain_supports() to handle feature checks correctly even in the case that the per device domain was not yet created by checking the features supported by the MSI parent. Add the necessary setup calls into the MSI and MSI-X enable code path. These setup calls are backwards compatible. They return success when there is no parent domain found, which means the existing global domains or the legacy allocation path keep just working. Co-developed-by: Ahmed S. Darwish Signed-off-by: Ahmed S. Darwish Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/irqdomain.c | 188 +++++++++++++++++++++++++++++++++++++++++++- drivers/pci/msi/msi.c | 16 +++ drivers/pci/msi/msi.h | 2 3 files changed, 201 insertions(+), 5 deletions(-) --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -139,6 +139,170 @@ struct irq_domain *pci_msi_create_irq_do } EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); +/* + * Per device MSI[-X] domain functionality + */ +static void pci_device_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) +{ + arg->desc = desc; + arg->hwirq = desc->msi_index; +} + +static void pci_mask_msi(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + + pci_msi_mask(desc, BIT(data->irq - desc->irq)); +} + +static void pci_unmask_msi(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + + pci_msi_unmask(desc, BIT(data->irq - desc->irq)); +} + +#ifdef CONFIG_GENERIC_IRQ_RESERVATION_MODE +# define MSI_REACTIVATE MSI_FLAG_MUST_REACTIVATE +#else +# define MSI_REACTIVATE 0 +#endif + +#define MSI_COMMON_FLAGS (MSI_FLAG_FREE_MSI_DESCS | \ + MSI_FLAG_ACTIVATE_EARLY | \ + MSI_FLAG_DEV_SYSFS | \ + MSI_REACTIVATE) + +static struct msi_domain_template pci_msi_template = { + .chip = { + .name = "PCI-MSI", + .irq_mask = pci_mask_msi, + .irq_unmask = pci_unmask_msi, + .irq_write_msi_msg = pci_msi_domain_write_msg, + .flags = IRQCHIP_ONESHOT_SAFE, + }, + + .ops = { + .set_desc = pci_device_domain_set_desc, + }, + + .info = { + .flags = MSI_COMMON_FLAGS | MSI_FLAG_MULTI_PCI_MSI, + .bus_token = DOMAIN_BUS_PCI_DEVICE_MSI, + }, +}; + +static void pci_mask_msix(struct irq_data *data) +{ + pci_msix_mask(irq_data_get_msi_desc(data)); +} + +static void pci_unmask_msix(struct irq_data *data) +{ + pci_msix_unmask(irq_data_get_msi_desc(data)); +} + +static struct msi_domain_template pci_msix_template = { + .chip = { + .name = "PCI-MSIX", + .irq_mask = pci_mask_msix, + .irq_unmask = pci_unmask_msix, + .irq_write_msi_msg = pci_msi_domain_write_msg, + .flags = IRQCHIP_ONESHOT_SAFE, + }, + + .ops = { + .set_desc = pci_device_domain_set_desc, + }, + + .info = { + .flags = MSI_COMMON_FLAGS | MSI_FLAG_PCI_MSIX, + .bus_token = DOMAIN_BUS_PCI_DEVICE_MSIX, + }, +}; + +static bool pci_match_device_domain(struct pci_dev *pdev, enum irq_domain_bus_token bus_token) +{ + return msi_match_device_irq_domain(&pdev->dev, MSI_DEFAULT_DOMAIN, bus_token); +} + +static bool pci_create_device_domain(struct pci_dev *pdev, struct msi_domain_template *tmpl, + unsigned int hwsize) +{ + struct irq_domain *domain = dev_get_msi_domain(&pdev->dev); + + if (!domain || !irq_domain_is_msi_parent(domain)) + return true; + + return msi_create_device_irq_domain(&pdev->dev, MSI_DEFAULT_DOMAIN, tmpl, + hwsize, NULL, NULL); +} + +/** + * pci_setup_msi_device_domain - Setup a device MSI interrupt domain + * @pdev: The PCI device to create the domain on + * + * Return: + * True when: + * - The device does not have a MSI parent irq domain associated, + * which keeps the legacy architecture specific and the global + * PCI/MSI domain models working + * - The MSI domain exists already + * - The MSI domain was successfully allocated + * False when: + * - MSI-X is enabled + * - The domain creation fails. + * + * The created MSI domain is preserved until: + * - The device is removed + * - MSI is disabled and a MSI-X domain is created + */ +bool pci_setup_msi_device_domain(struct pci_dev *pdev) +{ + if (WARN_ON_ONCE(pdev->msix_enabled)) + return false; + + if (pci_match_device_domain(pdev, DOMAIN_BUS_PCI_DEVICE_MSI)) + return true; + if (pci_match_device_domain(pdev, DOMAIN_BUS_PCI_DEVICE_MSIX)) + msi_remove_device_irq_domain(&pdev->dev, MSI_DEFAULT_DOMAIN); + + return pci_create_device_domain(pdev, &pci_msi_template, 1); +} + +/** + * pci_setup_msix_device_domain - Setup a device MSI-X interrupt domain + * @pdev: The PCI device to create the domain on + * @hwsize: The size of the MSI-X vector table + * + * Return: + * True when: + * - The device does not have a MSI parent irq domain associated, + * which keeps the legacy architecture specific and the global + * PCI/MSI domain models working + * - The MSI-X domain exists already + * - The MSI-X domain was successfully allocated + * False when: + * - MSI is enabled + * - The domain creation fails. + * + * The created MSI-X domain is preserved until: + * - The device is removed + * - MSI-X is disabled and a MSI domain is created + */ +bool pci_setup_msix_device_domain(struct pci_dev *pdev, unsigned int hwsize) +{ + if (WARN_ON_ONCE(pdev->msix_enabled)) + return false; + + if (pci_match_device_domain(pdev, DOMAIN_BUS_PCI_DEVICE_MSIX)) + return true; + if (pci_match_device_domain(pdev, DOMAIN_BUS_PCI_DEVICE_MSI)) + msi_remove_device_irq_domain(&pdev->dev, MSI_DEFAULT_DOMAIN); + + return pci_create_device_domain(pdev, &pci_msix_template, hwsize); +} + /** * pci_msi_domain_supports - Check for support of a particular feature flag * @pdev: The PCI device to operate on @@ -152,13 +316,33 @@ bool pci_msi_domain_supports(struct pci_ { struct msi_domain_info *info; struct irq_domain *domain; + unsigned int supported; domain = dev_get_msi_domain(&pdev->dev); if (!domain || !irq_domain_is_hierarchy(domain)) return mode == ALLOW_LEGACY; - info = domain->host_data; - return (info->flags & feature_mask) == feature_mask; + + if (!irq_domain_is_msi_parent(domain)) { + /* + * For "global" PCI/MSI interrupt domains the associated + * msi_domain_info::flags is the authoritive source of + * information. + */ + info = domain->host_data; + supported = info->flags; + } else { + /* + * For MSI parent domains the supported feature set + * is avaliable in the parent ops. This makes checks + * possible before actually instantiating the + * per device domain because the parent is never + * expanding the PCI/MSI functionality. + */ + supported = domain->msi_parent_ops->supported_flags; + } + + return (supported & feature_mask) == feature_mask; } /* --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -436,6 +436,9 @@ int __pci_enable_msi_range(struct pci_de if (rc) return rc; + if (!pci_setup_msi_device_domain(dev)) + return -ENODEV; + for (;;) { if (affd) { nvec = irq_calc_affinity_vectors(minvec, nvec, affd); @@ -787,9 +790,13 @@ int __pci_enable_msix_range(struct pci_d if (!pci_msix_validate_entries(dev, entries, nvec, hwsize)) return -EINVAL; - /* PCI_IRQ_VIRTUAL is a horrible hack! */ - if (nvec > hwsize && !(flags & PCI_IRQ_VIRTUAL)) - nvec = hwsize; + if (hwsize < nvec) { + /* Keep the IRQ virtual hackery working */ + if (flags & PCI_IRQ_VIRTUAL) + hwsize = nvec; + else + nvec = hwsize; + } if (nvec < minvec) return -ENOSPC; @@ -798,6 +805,9 @@ int __pci_enable_msix_range(struct pci_d if (rc) return rc; + if (!pci_setup_msix_device_domain(dev, hwsize)) + return -ENODEV; + for (;;) { if (affd) { nvec = irq_calc_affinity_vectors(minvec, nvec, affd); --- a/drivers/pci/msi/msi.h +++ b/drivers/pci/msi/msi.h @@ -105,6 +105,8 @@ enum support_mode { }; bool pci_msi_domain_supports(struct pci_dev *dev, unsigned int feature_mask, enum support_mode mode); +bool pci_setup_msi_device_domain(struct pci_dev *pdev); +bool pci_setup_msix_device_domain(struct pci_dev *pdev, unsigned int hwsize); /* Legacy (!IRQDOMAIN) fallbacks */ From patchwork Fri Nov 11 13:58:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18828 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759988wru; Fri, 11 Nov 2022 06:08:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf5dgo0STR4KK+KA9xqVUH73nYWWabDZe6cH72jef/fjbStBgu63wioCRDFdSbEwoxgOWa+a X-Received: by 2002:a17:903:1245:b0:186:59e9:20f6 with SMTP id u5-20020a170903124500b0018659e920f6mr2852908plh.39.1668175694607; Fri, 11 Nov 2022 06:08:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175694; cv=none; d=google.com; s=arc-20160816; b=nIxnhs6ytwgvJO2rhV1srIS3Uft+BFdij/m+AuSUQqvfKV3YIvorNIy6Oe5SE2sC9n 5G71KDZt/LimdI47NaCl9NEqiu3L1M8h1WGnBMk8gydNiUJJb+B+MlWdc8iqFysFxFSZ AC9RHzmw/wfKXnio0R1Vi03lr6QUBpevFxHg+27nFO2WOYz0yLQVgjvKtadxeXl0oxC+ a5MSFefmW/dSMqNYVu5SRDIZy1C2VQly9C6YWLa/DG4YLVW/muoXOs5IqzuGCIXYMvra jyYgLrV5hyDYRuz6T3zj84J+Npik8IUMeqgfkW9IYdgXkLzlVbulBEvHYjMWUhuL6Mqe P3Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=/09RlM+7gj5K4LfqEL1nau73oAlZS7dH6M7zMmZ6g+c=; b=O4nxKAHIcwPM4zLfS/haScvt7Qe+kb6t1OK1ffXzyL8avBz3FFVWLNB1HggPg+WwTQ 1j0+We+hJGhGzUV/6juLjJWF/IDYxUarjT/epvS0F31O0UFGnaqB+jhZsykCtZNsp2Tv PWe5sH8lNdEQO3Z/C+PlI2YNRvHGZlVKes6uRAXAhvZJXCA6JMSSf00iVuHL0eN8dJLJ lmv7slIh2CWLtFEDyQAzUHHY+H/QnujShqtLDFpv5iV1+RX4iQjk8sappWxZJ8d09UY/ LVmPMsGyftdnrR/woiCX8kxtgnsf0u0Heg+zm/dA9hG+3G6Vn9C3K7sx4jyM2fKDptac 7L/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="QkVh8/Ir"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 13/33] x86/apic/vector: Provide MSI parent domain References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:31 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208997075744795?= X-GMAIL-MSGID: =?utf-8?q?1749208997075744795?= Enable MSI parent domain support in the x86 vector domain and fixup the checks in the iommu implementations to check whether device::msi::domain is the default MSI parent domain. That keeps the existing logic to protect e.g. devices behind VMD working. The interrupt remap PCI/MSI code still works because the underlying vector domain still provides the same functionality. None of the other x86 PCI/MSI, e.g. XEN and HyperV, implementations are affected either. They still work the same way both at the low level and the PCI/MSI implementations they provide. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/msi.h | 6 + arch/x86/include/asm/pci.h | 1 arch/x86/kernel/apic/msi.c | 176 ++++++++++++++++++++++++++---------- drivers/iommu/amd/iommu.c | 2 drivers/iommu/intel/irq_remapping.c | 2 5 files changed, 138 insertions(+), 49 deletions(-) --- a/arch/x86/include/asm/msi.h +++ b/arch/x86/include/asm/msi.h @@ -62,4 +62,10 @@ typedef struct x86_msi_addr_hi { struct msi_msg; u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid); +#define X86_VECTOR_MSI_FLAGS_SUPPORTED \ + (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX) + +#define X86_VECTOR_MSI_FLAGS_REQUIRED \ + (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS) + #endif /* _ASM_X86_MSI_H */ --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -92,6 +92,7 @@ void pcibios_scan_root(int bus); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); +bool pci_dev_has_default_msi_parent_domain(struct pci_dev *dev); #define HAVE_PCI_MMAP #define arch_can_pci_mmap_wc() pat_enabled() --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -142,67 +142,131 @@ msi_set_affinity(struct irq_data *irqd, return ret; } -/* - * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, - * which implement the MSI or MSI-X Capability Structure. +/** + * pci_dev_has_default_msi_parent_domain - Check whether the device has the default + * MSI parent domain associated + * @dev: Pointer to the PCI device */ -static struct irq_chip pci_msi_controller = { - .name = "PCI-MSI", - .irq_unmask = pci_msi_unmask_irq, - .irq_mask = pci_msi_mask_irq, - .irq_ack = irq_chip_ack_parent, - .irq_retrigger = irq_chip_retrigger_hierarchy, - .irq_set_affinity = msi_set_affinity, - .flags = IRQCHIP_SKIP_SET_WAKE | - IRQCHIP_AFFINITY_PRE_STARTUP, -}; +bool pci_dev_has_default_msi_parent_domain(struct pci_dev *dev) +{ + struct irq_domain *domain = dev_get_msi_domain(&dev->dev); -int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, - msi_alloc_info_t *arg) + if (!domain) + domain = dev_get_msi_domain(&dev->bus->dev); + if (!domain) + return false; + + return domain == x86_vector_domain; +} + +/** + * x86_msi_prepare - Setup of msi_alloc_info_t for allocations + * @domain: The domain for which this setup happens + * @dev: The device for which interrupts are allocated + * @nvec: The number of vectors to allocate + * @alloc: The allocation info structure to initialize + * + * This function is to be used for all types of MSI domains above the x86 + * vector domain and any intermediates. It is always invoked from the + * top level interrupt domain. The domain specific allocation + * functionality is determined via the @domain's bus token which allows to + * map the X86 specific allocation type. + */ +static int x86_msi_prepare(struct irq_domain *domain, struct device *dev, + int nvec, msi_alloc_info_t *alloc) { - init_irq_alloc_info(arg, NULL); - if (to_pci_dev(dev)->msix_enabled) - arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX; - else - arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI; + struct msi_domain_info *info = domain->host_data; - return 0; + init_irq_alloc_info(alloc, NULL); + + switch (info->bus_token) { + case DOMAIN_BUS_PCI_DEVICE_MSI: + alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSI; + return 0; + case DOMAIN_BUS_PCI_DEVICE_MSIX: + alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX; + return 0; + default: + return -EINVAL; + } } -EXPORT_SYMBOL_GPL(pci_msi_prepare); -static struct msi_domain_ops pci_msi_domain_ops = { - .msi_prepare = pci_msi_prepare, -}; +/** + * x86_vector_init_dev_msi_info - Domain info setup for MSI domains + * @dev: The device for which the domain should be created + * @domain: The (root) domain providing this callback + * @real_parent: The real parent domain of the to initialize domain + * @info: The domain info for the to initialize domain + * + * This function is to be used for all types of MSI domains above the x86 + * vector domain and any intermediates. The domain specific functionality + * is determined via the @real_parent. + */ +static bool x86_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, struct msi_domain_info *info) +{ + const struct msi_parent_ops *pops = real_parent->msi_parent_ops; + + /* MSI parent domain specific settings */ + switch (real_parent->bus_token) { + case DOMAIN_BUS_ANY: + /* Only the vector domain can have the ANY token */ + if (WARN_ON_ONCE(domain != real_parent)) + return false; + info->chip->irq_set_affinity = msi_set_affinity; + /* See msi_set_affinity() for the gory details */ + info->flags |= MSI_FLAG_NOMASK_QUIRK; + break; + default: + WARN_ON_ONCE(1); + return false; + } + + /* Is the target supported? */ + switch(info->bus_token) { + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: + break; + default: + WARN_ON_ONCE(1); + return false; + } + + /* + * Mask out the domain specific MSI feature flags which are not + * supported by the real parent. + */ + info->flags &= pops->supported_flags; + /* Enforce the required flags */ + info->flags |= X86_VECTOR_MSI_FLAGS_REQUIRED; + + /* This is always invoked from the top level MSI domain! */ + info->ops->msi_prepare = x86_msi_prepare; + + info->chip->irq_ack = irq_chip_ack_parent; + info->chip->irq_retrigger = irq_chip_retrigger_hierarchy; + info->chip->flags |= IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP; -static struct msi_domain_info pci_msi_domain_info = { - .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX | MSI_FLAG_NOMASK_QUIRK, - - .ops = &pci_msi_domain_ops, - .chip = &pci_msi_controller, - .handler = handle_edge_irq, - .handler_name = "edge", + info->handler = handle_edge_irq; + info->handler_name = "edge"; + + return true; +} + +static const struct msi_parent_ops x86_vector_msi_parent_ops = { + .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED, + .init_dev_msi_info = x86_init_dev_msi_info, }; struct irq_domain * __init native_create_pci_msi_domain(void) { - struct fwnode_handle *fn; - struct irq_domain *d; - if (disable_apic) return NULL; - fn = irq_domain_alloc_named_fwnode("PCI-MSI"); - if (!fn) - return NULL; - - d = pci_msi_create_irq_domain(fn, &pci_msi_domain_info, - x86_vector_domain); - if (!d) { - irq_domain_free_fwnode(fn); - pr_warn("Failed to initialize PCI-MSI irqdomain.\n"); - } - return d; + x86_vector_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + x86_vector_domain->msi_parent_ops = &x86_vector_msi_parent_ops; + return x86_vector_domain; } void __init x86_create_pci_msi_domain(void) @@ -210,7 +274,25 @@ void __init x86_create_pci_msi_domain(vo x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain(); } +/* Keep around for hyperV and the remap code below */ +int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, + msi_alloc_info_t *arg) +{ + init_irq_alloc_info(arg, NULL); + + if (to_pci_dev(dev)->msix_enabled) + arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX; + else + arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI; + return 0; +} +EXPORT_SYMBOL_GPL(pci_msi_prepare); + #ifdef CONFIG_IRQ_REMAP +static struct msi_domain_ops pci_msi_domain_ops = { + .msi_prepare = pci_msi_prepare, +}; + static struct irq_chip pci_msi_ir_controller = { .name = "IR-PCI-MSI", .irq_unmask = pci_msi_unmask_irq, --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -812,7 +812,7 @@ static void amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { if (!irq_remapping_enabled || !dev_is_pci(dev) || - pci_dev_has_special_msi_domain(to_pci_dev(dev))) + !pci_dev_has_default_msi_parent_domain(to_pci_dev(dev))) return; dev_set_msi_domain(dev, iommu->msi_domain); --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1107,7 +1107,7 @@ static int reenable_irq_remapping(int ei */ void intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { - if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev)) + if (!irq_remapping_enabled || !pci_dev_has_default_msi_parent_domain(info->dev)) return; dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev)); 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Darwish" , Reinette Chatre Subject: [patch 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:33 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209063529381986?= X-GMAIL-MSGID: =?utf-8?q?1749209063529381986?= The check for special MSI domains like VMD which prevents the interrupt remapping code to overwrite device::msi::domain is not longer required and has been replaced by an x86 specific version which is aware of MSI parent domains. Remove it. Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/irqdomain.c | 21 --------------------- include/linux/msi.h | 2 -- 2 files changed, 23 deletions(-) --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -414,24 +414,3 @@ struct irq_domain *pci_msi_get_device_do DOMAIN_BUS_PCI_MSI); return dom; } - -/** - * pci_dev_has_special_msi_domain - Check whether the device is handled by - * a non-standard PCI-MSI domain - * @pdev: The PCI device to check. - * - * Returns: True if the device irqdomain or the bus irqdomain is - * non-standard PCI/MSI. - */ -bool pci_dev_has_special_msi_domain(struct pci_dev *pdev) -{ - struct irq_domain *dom = dev_get_msi_domain(&pdev->dev); - - if (!dom) - dom = dev_get_msi_domain(&pdev->bus->dev); - - if (!dom) - return true; - - return dom->bus_token != DOMAIN_BUS_PCI_MSI; -} --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -599,8 +599,6 @@ struct irq_domain *pci_msi_create_irq_do struct irq_domain *parent); u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev); struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev); -bool pci_dev_has_special_msi_domain(struct pci_dev *pdev); - #endif /* CONFIG_GENERIC_MSI_IRQ */ #endif /* LINUX_MSI_H */ From patchwork Fri Nov 11 13:58:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18840 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760818wru; Fri, 11 Nov 2022 06:09:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf77eESz9nxv1Kp+RhJhuESd1+lbFIYTyTGV12wosLOXgR9c4OH9stRQRr7DpwQ3+/b2jigX X-Received: by 2002:a17:903:25cd:b0:17f:6aef:3c83 with SMTP id jc13-20020a17090325cd00b0017f6aef3c83mr2788559plb.9.1668175770850; Fri, 11 Nov 2022 06:09:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175770; cv=none; d=google.com; s=arc-20160816; b=OQKkk5EAIJuxym/hkOx+bLwwxCqtxcbHaF48W6ra8pGRP/pBf3E/CVglQdfm3J0moi WycjCemPAkxlitH+3+THI7cCadjQMvNphrSLAHAE3EZH6Qf1CwJk02Zg2l25uoyYCNZX wHD4ZvbA7Uh/Qo2PCp6XYDJhtsjXYCx2fuytvAxMW1W2AHhfir7kBeq0iNl5EM1Me/HS KNgSgIpIS4v3MmSiUdO/D6o0uCKBOcltS0xca6RL701IYde+vfSTHlo3qqlxFrcAIFwq SNLo2SnvB6FTa3ony1WQcnDTR8gAbFSAE7qZ2nSK7gOitp+PWk/L4wowNRiePqBArqBD 91qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=OWDR1HVKygNBsw9mLHuKFZNGcf87XagJ2m0BnhitI40=; b=fZvN3NIfJzaSIq6ojfPTBpcdpQoMaDszqRsPa1rJwSfjP1EDXMtK1CLDoxwpboxN3v UA2dt2BbBPLVQBt5gClkGYKfJDbhIQ6+mC4I5MFuFlXY87gs55AZ1NB8chs5w+0VxAD5 NuNR4YQroMd64BwJ1L6Yg/6tAMNJ/uvxoi1/BSzmAZK2rKNROawQmvqD+Z1szqYwU8AB eWkOqorL6RAfdYBmn494o1TuhX2kBkAG8V1XpECde10BVHIJIaZZrojgZTmh99NVV/6c AM9pdYqyujPbd5AQCiZH2rRuRU2cTdBYEK1ol1nymGl1egf+xU0f1x++C0JVbvxhaG3c vETQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=udW9IcJS; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=fB9FMLcP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 15/33] iommu/vt-d: Switch to MSI parent domains References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:35 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209076949680249?= X-GMAIL-MSGID: =?utf-8?q?1749209076949680249?= Remove the global PCI/MSI irqdomain implementation and provide the required MSI parent ops so the PCI/MSI code can detect the new parent and setup per device domains. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/msi.c | 2 ++ drivers/iommu/intel/iommu.h | 1 - drivers/iommu/intel/irq_remapping.c | 27 ++++++++++++--------------- include/linux/irqdomain_defs.h | 1 + 4 files changed, 15 insertions(+), 16 deletions(-) --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -217,6 +217,8 @@ static bool x86_init_dev_msi_info(struct /* See msi_set_affinity() for the gory details */ info->flags |= MSI_FLAG_NOMASK_QUIRK; break; + case DOMAIN_BUS_DMAR: + break; default: WARN_ON_ONCE(1); return false; --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -600,7 +600,6 @@ struct intel_iommu { #ifdef CONFIG_IRQ_REMAP struct ir_table *ir_table; /* Interrupt remapping info */ struct irq_domain *ir_domain; - struct irq_domain *ir_msi_domain; #endif struct iommu_device iommu; /* IOMMU core code handle */ int node; --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -82,6 +82,7 @@ static const struct irq_domain_ops intel static void iommu_disable_irq_remapping(struct intel_iommu *iommu); static int __init parse_ioapics_under_ir(void); +static const struct msi_parent_ops dmar_msi_parent_ops; static bool ir_pre_enabled(struct intel_iommu *iommu) { @@ -230,7 +231,7 @@ static struct irq_domain *map_dev_to_ir( { struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev); - return drhd ? drhd->iommu->ir_msi_domain : NULL; + return drhd ? drhd->iommu->ir_domain : NULL; } static int clear_entries(struct irq_2_iommu *irq_iommu) @@ -573,10 +574,10 @@ static int intel_setup_irq_remapping(str pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); goto out_free_fwnode; } - iommu->ir_msi_domain = - arch_create_remap_msi_irq_domain(iommu->ir_domain, - "INTEL-IR-MSI", - iommu->seq_id); + + irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_DMAR); + iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + iommu->ir_domain->msi_parent_ops = &dmar_msi_parent_ops; ir_table->base = page_address(pages); ir_table->bitmap = bitmap; @@ -620,9 +621,6 @@ static int intel_setup_irq_remapping(str return 0; out_free_ir_domain: - if (iommu->ir_msi_domain) - irq_domain_remove(iommu->ir_msi_domain); - iommu->ir_msi_domain = NULL; irq_domain_remove(iommu->ir_domain); iommu->ir_domain = NULL; out_free_fwnode: @@ -644,13 +642,6 @@ static void intel_teardown_irq_remapping struct fwnode_handle *fn; if (iommu && iommu->ir_table) { - if (iommu->ir_msi_domain) { - fn = iommu->ir_msi_domain->fwnode; - - irq_domain_remove(iommu->ir_msi_domain); - irq_domain_free_fwnode(fn); - iommu->ir_msi_domain = NULL; - } if (iommu->ir_domain) { fn = iommu->ir_domain->fwnode; @@ -1437,6 +1428,12 @@ static const struct irq_domain_ops intel .deactivate = intel_irq_remapping_deactivate, }; +static const struct msi_parent_ops dmar_msi_parent_ops = { + .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_MSI, + .prefix = "IR-", + .init_dev_msi_info = msi_parent_init_dev_msi_info, +}; + /* * Support of Interrupt Remapping Unit Hotplug */ --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -23,6 +23,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_VMD_MSI, DOMAIN_BUS_PCI_DEVICE_MSI, DOMAIN_BUS_PCI_DEVICE_MSIX, + DOMAIN_BUS_DMAR, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ From patchwork Fri Nov 11 13:58:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18829 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760021wru; Fri, 11 Nov 2022 06:08:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf4+u+NnntmLVOMPBo1BjvJngQEeNNt7RDkBTRKiYqbOPKsK7FCOrhn+xG4lXKnzBvGsXdBB X-Received: by 2002:a17:90b:2784:b0:213:d1d5:d661 with SMTP id pw4-20020a17090b278400b00213d1d5d661mr2158060pjb.43.1668175696846; Fri, 11 Nov 2022 06:08:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175696; cv=none; d=google.com; s=arc-20160816; b=mL6drfIPv48bz6elLug1QfS2KcNWzhJhbFQ7f6bNMiiWkdsuT0MkZVoA+uZD8RWlnx k2Wj9NGY+mx8H9lbAkqP81GNA09fAt9oI/f/E0HjWvE/tjRhEBxQcDh/P7ulLIw3/1xp p4SwJiB7EBuTF3qZsIlpi0cdX0ffPpDUQ6qrhYaqIHNragd/aAZcXT/4H4L8FHtGe97h 2X/E6IirW8MKFa1uEUVZmMtUcXCw5ft6Io5WxBZtFz1m/ya2OAEWjBmmtYa5FF755zwW p3Ekhaht1wacoHCbf4UoQWr0HAMyQsBUJ/6tSTEOyDtQ1Ik2D5e/XBRMUAXx49w0cyBH 4BOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=5F8g3aU97Z6Kyag3K9E0SkLjFZeBlcTh6td6sXBxDio=; b=ukuNnUd8U2gpSEn6LH4BITYINMtkFy1dEujPOiFmGeC8yxJM9Vh8H1kbtULsVdL7xv Ovdj2vUooYZKax/bpEQG5fkQc5XnQ+nsi2zPmEodj0wMEmA57f8uMTrCI3iBAdUttrx9 p6EYgXCfNDUcr3fqZL1hoUplmsIOEhiEm7Yhr8wdOUMVg5OUgufxPAFCJBVvDqbvaFIV UbN+a3ghuExrYjOkm4xuowzdrq7KWyeEsK+sFdPR2b4PJOONC5QkJJfeJZWirhAVPVhb aKo57CwrC/M8aOuh5SNvco42gRipERTXtXE/o6jnej4sUsw2458Eyw1bOQ7pdbGyOzJD Tvkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hCvxiEaR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 16/33] iommu/amd: Switch to MSI base domains References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:36 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749208999261854122?= X-GMAIL-MSGID: =?utf-8?q?1749208999261854122?= Remove the global PCI/MSI irqdomain implementation and provide the required MSI parent ops so the PCI/MSI code can detect the new parent and setup per device domains. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/msi.c | 1 + drivers/iommu/amd/amd_iommu_types.h | 1 - drivers/iommu/amd/iommu.c | 19 +++++++++++++------ include/linux/irqdomain_defs.h | 1 + 4 files changed, 15 insertions(+), 7 deletions(-) --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -218,6 +218,7 @@ static bool x86_init_dev_msi_info(struct info->flags |= MSI_FLAG_NOMASK_QUIRK; break; case DOMAIN_BUS_DMAR: + case DOMAIN_BUS_AMDVI: break; default: WARN_ON_ONCE(1); --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -734,7 +734,6 @@ struct amd_iommu { u8 max_counters; #ifdef CONFIG_IRQ_REMAP struct irq_domain *ir_domain; - struct irq_domain *msi_domain; struct amd_irte_ops *irte_ops; #endif --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -815,7 +815,7 @@ amd_iommu_set_pci_msi_domain(struct devi !pci_dev_has_default_msi_parent_domain(to_pci_dev(dev))) return; - dev_set_msi_domain(dev, iommu->msi_domain); + dev_set_msi_domain(dev, iommu->ir_domain); } #else /* CONFIG_IRQ_REMAP */ @@ -3648,6 +3648,12 @@ static struct irq_chip amd_ir_chip = { .irq_compose_msi_msg = ir_compose_msi_msg, }; +static const struct msi_parent_ops amdvi_msi_parent_ops = { + .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_MSI, + .prefix = "IR-", + .init_dev_msi_info = msi_parent_init_dev_msi_info, +}; + int amd_iommu_create_irq_domain(struct amd_iommu *iommu) { struct fwnode_handle *fn; @@ -3655,16 +3661,17 @@ int amd_iommu_create_irq_domain(struct a fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); if (!fn) return -ENOMEM; - iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); + iommu->ir_domain = irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 0, 0, + fn, &amd_ir_domain_ops, iommu); if (!iommu->ir_domain) { irq_domain_free_fwnode(fn); return -ENOMEM; } - iommu->ir_domain->parent = arch_get_ir_parent_domain(); - iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, - "AMD-IR-MSI", - iommu->index); + irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI); + iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + iommu->ir_domain->msi_parent_ops = &amdvi_msi_parent_ops; + return 0; } --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -24,6 +24,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_PCI_DEVICE_MSI, DOMAIN_BUS_PCI_DEVICE_MSIX, DOMAIN_BUS_DMAR, + DOMAIN_BUS_AMDVI, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ From patchwork Fri Nov 11 13:58:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18831 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760138wru; Fri, 11 Nov 2022 06:08:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf5KOzfLdFzd3J1Ufy5/6MwJhcx+Hi32brF5E9V+ySQsfSjT1aXG0lNaejA+A48mD7MfOz7z X-Received: by 2002:a17:90b:4cc1:b0:213:1143:9886 with SMTP id nd1-20020a17090b4cc100b0021311439886mr2072209pjb.236.1668175706905; Fri, 11 Nov 2022 06:08:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175706; cv=none; d=google.com; s=arc-20160816; b=whMDyccpKBvRoiunJwmdRx9NH5aSccyDCuUjlWc1HzbPW1lUG0jktNHPywlxy7RZdg Ruqf2OK9EeBL0/T164a1liBnX+bisibhcK2KsLDdf9sPIH80unxFrh6l6cvYjrze7nz5 k7tncwcR/dXTlT4V2MVwKM2uCzMkhJIZFOdragaATr8dD+7tOMnPNFc+saAyQEAKBnro 2h6qCfWN2xjS/F21OYUdbnshhST+ZIKsbplwdTvMLEAiT9qHZ9An+wogwQxY/jkQDKw6 bw1lBo+GcHe02Xf4WwwlVr9U823Tlr9rsklaQLL+thKtTc7/1vp1EuiBWRFLnVlW9GCb LjRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=T4PJKhvy3BXQPG8m3pythcilM8fEjCtnrP9dFwguEN8=; b=VCINVb22MvDLxLMO3KfXh8SvvUys9356JJdvHDPiM1IGtZ0lCl4aBSjHATy7CC4TMT Pd23NuL0RJPmcDsBkoYLzxLPv+P5MCxdp289S5iGKygAUHmDmn7tWX2WjFUB2alWnNVX ptS5izoAouLXKjdyC88FWIMY2Rxn0Zi4MZpDyMkRrzSU/LyWB4bklhc0URsr8s1YwxhP DEgBqncOckoPqjUHsQJGqOGYo6iNlKsJl/RM+o+aI5vU2Y6Ndbgy4cWf2fa5V40g1sXj ihFO/O2bBzVEfT8bMbA7LO9v7QwNq0fDg92n6OKdvGC6ya66vEq/uNSjxprhASNSWPKM 9R2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ByEzPpj3; dkim=neutral (no key) header.i=@linutronix.de header.b=EUvCzVBr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:38 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209009911214098?= X-GMAIL-MSGID: =?utf-8?q?1749209009911214098?= and related code which is not longer required now that the interrupt remap code has been converted to MSI parent domains. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/irq_remapping.h | 4 --- arch/x86/kernel/apic/msi.c | 42 ----------------------------------- 2 files changed, 1 insertion(+), 45 deletions(-) --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -44,10 +44,6 @@ extern int irq_remapping_reenable(int); extern int irq_remap_enable_fault_handling(void); extern void panic_if_irq_remap(const char *msg); -/* Create PCI MSI/MSIx irqdomain, use @parent as the parent irqdomain. */ -extern struct irq_domain * -arch_create_remap_msi_irq_domain(struct irq_domain *par, const char *n, int id); - /* Get parent irqdomain for interrupt remapping irqdomain */ static inline struct irq_domain *arch_get_ir_parent_domain(void) { --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -277,7 +277,7 @@ void __init x86_create_pci_msi_domain(vo x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain(); } -/* Keep around for hyperV and the remap code below */ +/* Keep around for hyperV */ int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *arg) { @@ -291,46 +291,6 @@ int pci_msi_prepare(struct irq_domain *d } EXPORT_SYMBOL_GPL(pci_msi_prepare); -#ifdef CONFIG_IRQ_REMAP -static struct msi_domain_ops pci_msi_domain_ops = { - .msi_prepare = pci_msi_prepare, -}; - -static struct irq_chip pci_msi_ir_controller = { - .name = "IR-PCI-MSI", - .irq_unmask = pci_msi_unmask_irq, - .irq_mask = pci_msi_mask_irq, - .irq_ack = irq_chip_ack_parent, - .irq_retrigger = irq_chip_retrigger_hierarchy, - .flags = IRQCHIP_SKIP_SET_WAKE | - IRQCHIP_AFFINITY_PRE_STARTUP, -}; - -static struct msi_domain_info pci_msi_ir_domain_info = { - .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, - .ops = &pci_msi_domain_ops, - .chip = &pci_msi_ir_controller, - .handler = handle_edge_irq, - .handler_name = "edge", -}; - -struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent, - const char *name, int id) -{ - struct fwnode_handle *fn; - struct irq_domain *d; - - fn = irq_domain_alloc_named_id_fwnode(name, id); - if (!fn) - return NULL; - d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent); - if (!d) - irq_domain_free_fwnode(fn); - return d; -} -#endif - #ifdef CONFIG_DMAR_TABLE /* * The Intel IOMMU (ab)uses the high bits of the MSI address to contain the From patchwork Fri Nov 11 13:58:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18841 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp761033wru; Fri, 11 Nov 2022 06:09:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf7V4ZVz68DTg9Rp49nWl0yakL+8nWzD9XCjP7bUnzQnS/3fhPIOZL/x0BKox/QST7LLhjs6 X-Received: by 2002:a17:903:1c7:b0:176:ab43:a48 with SMTP id e7-20020a17090301c700b00176ab430a48mr2769407plh.53.1668175793105; Fri, 11 Nov 2022 06:09:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175793; cv=none; d=google.com; s=arc-20160816; b=OEZpgJiaH1Yh5y24g6uKUnTNMR+AxtS85ZoNfvJJCrSSAH8bK7fCdV634tz+3MfAT3 n2f+yWjZ5ZaO4VhETvPY0CTwn4E5tGPqNFs3sAnEKSbTD+wOl0kkBeBKQLRcyBmlC0Nn J7s/+gwr/+kTwFh8fVeb4OdLNi/rL0tw/AhOlG1twt024DedN/riDa9X4lLmsppxpHX7 YJQx6ztKnoI/vQPca85nOn0Og2nesusAiEz5Z4nD+9pJm/Zv5wQsnkr0D+wQqbXr2GDg tpsCKdTD2NWCnfJFcARs4FEhhi6FAOubPGfd91/RKSTGpIx0cGXBz1zh0OGIxignD1rB 7oaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=cFx6dbaS3ynUGuWTq2v8hXwBFa/HBDy+17s0E2mkPoM=; b=f9OTOSt8h2LzP85qrKrWQ4VuStMVNdAwkuXyhS0IR5+9vTVurqetm/Tq8UaytDyWwZ AgXmJNgwFkKPfx3Jg0a0KeE5dvXy9n/MnJO4F7pFFfQXVnio24+o22MDMXW3s7d738qM qldWyhNL8o9LwDbpvYM+rF4InRcPi5xhoOrl4VzQlKeHTtr8yaADpBCfJUeCRsmzHdub vomF79lErRMhmtsTPztLq801dehW7SuNVoNI2KvfExNxLxU10nLuC8EycCWBDN5OTEr/ yeCguU5kPMcsQG/sj7cA6UVw1Yu9m/GCaFcMyuTCYebYR3uNaqBlaGRQXHPwuwjCwxTz uW1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=atG8rpd9; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 18/33] genirq/msi: Provide struct msi_map References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:39 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209100118342410?= X-GMAIL-MSGID: =?utf-8?q?1749209100118342410?= A simple struct to hold a MSI index / Linux interrupt number pair. It will be returned from the dynamic vector allocation function and handed back to the corresponding free() function. Signed-off-by: Thomas Gleixner --- include/linux/msi_api.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) --- a/include/linux/msi_api.h +++ b/include/linux/msi_api.h @@ -18,6 +18,19 @@ enum msi_domain_ids { MSI_MAX_DEVICE_IRQDOMAINS, }; +/** + * msi_map - Mapping between MSI index and Linux interrupt number + * @index: The MSI index, e.g. slot in the MSI-X table or + * a software managed index if >= 0. If negative + * the allocation function failed and it contains + * the error code. + * @virq: The associated Linux interrupt number + */ +struct msi_map { + int index; + int virq; +}; + unsigned int msi_domain_get_virq(struct device *dev, unsigned int domid, unsigned int index); /** From patchwork Fri Nov 11 13:58:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18830 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760047wru; Fri, 11 Nov 2022 06:08:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf6BdH3ln2/m3SueTu9zWOCz47La+AyaOjd7biQlvCObXbHyuz3OQTUgTZ/fbpga394KyCK8 X-Received: by 2002:a63:e644:0:b0:459:7d5f:293e with SMTP id p4-20020a63e644000000b004597d5f293emr1721224pgj.602.1668175699203; Fri, 11 Nov 2022 06:08:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175699; cv=none; d=google.com; s=arc-20160816; b=Kba51EBOTgLbz7swtTWPNctq4Sae9chg3j+jK39AqnJWmHoxtsQARVzg63CNoqwN8r iCZu/YzFeOzX1k4TH39L0RUjrveowIm0EvgbZXTpVsMwfl9NZustVKHgGp6H6xO+o4KN 8oKmFzb/CxDezVbHi+tsQQBCBUj+6g1llF2kRbgXzK2oe/kol0iSpP0j1M8qfyXB80Hg inwcIQi6LYIgZSEnk6iHPe81r25ZCnh3I2G0n/rypAmRDzTfVSxobbVaE0FFaawSd/QN zy11fa1LLazqlw4a9oS0MmAhd0YoeSvmY88vsnYPQ2xsu8iccHR+Pi6AavM7N1pnilF/ ZT3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=UQ8wGaxCGGl6i2FWioqhnvUbaJkzVnC/Tizkv4RadYs=; b=mTKT0ZJjUoZJ0t5QnN0RmeMAuATO3S/OxoSf8lTzI/JKF+mOQwtoyy7DbQKHSnWcai JVxylnnyFLKkILzy/rXdUYxOjDQMU0AI3pfYdQEZGZVl5RB2p4jpyhnauKvK/FO066DP tDTZQgyEYsiR22GyzteD/grd/d5llsJNTv7hleeBmM+FfONW5/zX3uvcy+wHc5LRZnGv bsn32YaKMnDIAbthMAeid3YnR37+YUBLk8HwekMNIqUrQJM9/oAGxvXdMTB7dcTcAF17 Cif3cNqURuIMLxt0UGETYiHraK653ZfB8fXX7PJFOTT3fmLyLiWvX2+BWvHP/RuPq+pV OjAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=InbvRLz2; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q18-20020a170902789200b001822121c45fsi2357669pll.338.2022.11.11.06.08.04; Fri, 11 Nov 2022 06:08:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=InbvRLz2; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234485AbiKKOGy (ORCPT + 99 others); Fri, 11 Nov 2022 09:06:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234215AbiKKOGV (ORCPT ); Fri, 11 Nov 2022 09:06:21 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9091598BB8; Fri, 11 Nov 2022 05:59:40 -0800 (PST) Message-ID: <20221111135206.346985384@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175121; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UQ8wGaxCGGl6i2FWioqhnvUbaJkzVnC/Tizkv4RadYs=; b=InbvRLz2xiE1xSxHfoXRhru+XjEM5gfiGxuSEQ7Lcj/JvYVrWqnuRqCyOQbXgOZP3a+IrX afUht5oZxyk+AaXMsRFzV3gSY/hfw8vB9zcjWVluI96CJyotpxAVAo7mMcKjj54m9ID8aq muBCRnwtZ+4h/QIWJzK4dJnmMiBw/06/XhL8AxiR/qvLsmXNeHzJn01//ekakzNVQLEW2A enPEZxfcPxnxGzRc58QjjccMWsTbjSD3j5FMH6qVY/a4RRpkrBOYYz21mYNHPexZWNmQfo JKHFdxdT926RfGjIssN/mFK3I9DtOzBaQjuryH4M8Cvl05TXDLJpa+1WW38zqA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175122; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UQ8wGaxCGGl6i2FWioqhnvUbaJkzVnC/Tizkv4RadYs=; b=CZMuJlTc7yrU0Fd0ZAHupzdYF1YUnHqpbn+7nNNm+rX7yFmAGQs8NV5Ytqm12bxK2u1hDq ATinmN2jvy4w6rBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 19/33] genirq/msi: Provide msi_desc::msi_data References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:41 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209001932782574?= X-GMAIL-MSGID: =?utf-8?q?1749209001932782574?= The upcoming support for PCI/IMS requires to store some information related to the message handling in the MSI descriptor, e.g. PASID or a pointer to a queue. Provide a generic storage struct which maps over the existing PCI specific storage which means the size of struct msi_desc is not getting bigger. It contains a iomem pointer for device memory based IMS and a union of a u64 and a void pointer which allows the device specific IMS implementations to store the necessary information. The iomem pointer is set up by the domain allocation functions. The data union msi_dev_cookie is going to be handed in when allocating an interrupt on an IMS domain so the irq chip callbacks of the IMS domain have the necessary per vector information available. It also comes in handy when cleaning up the platform MSI code for wire to MSI bridges which need to hand down the type information to the underlying interrupt domain. For the core code the cookie is opaque and meaningless. It just stores it during an allocation through the upcoming interfaces for IMS and wire to MSI brigdes. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 19 ++++++++++++++++++- include/linux/msi_api.h | 17 +++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -121,6 +121,19 @@ struct pci_msi_desc { }; }; +/** + * struct msi_desc_data - Generic MSI descriptor data + * @iobase: Pointer to the IOMEM base adress for interrupt callbacks + * @cookie: Device cookie provided at allocation time + * + * The content of this data is implementation defined, e.g. PCI/IMS + * implementations will define the meaning of the data. + */ +struct msi_desc_data { + void __iomem *iobase; + union msi_dev_cookie cookie; +}; + #define MSI_MAX_INDEX ((unsigned int)USHRT_MAX) /** @@ -138,6 +151,7 @@ struct pci_msi_desc { * * @msi_index: Index of the msi descriptor * @pci: PCI specific msi descriptor data + * @data: Generic MSI descriptor data */ struct msi_desc { /* Shared device/bus type independent data */ @@ -157,7 +171,10 @@ struct msi_desc { void *write_msi_msg_data; u16 msi_index; - struct pci_msi_desc pci; + union { + struct pci_msi_desc pci; + struct msi_desc_data data; + }; }; /* --- a/include/linux/msi_api.h +++ b/include/linux/msi_api.h @@ -19,6 +19,23 @@ enum msi_domain_ids { }; /** + * union msi_dev_cookie - MSI device cookie + * @value: u64 value store + * @ptr: Pointer + * + * This data is handed to the IMS allocation function and stored + * in the MSI descriptor for the interrupt chip callbacks. + * + * The content of this data is implementation defined, e.g. PCI/IMS + * implementations will define the meaning of the data, e.g. PASID or a + * pointer to queue memory. + */ +union msi_dev_cookie { + u64 value; + void *ptr; +}; + +/** * msi_map - Mapping between MSI index and Linux interrupt number * @index: The MSI index, e.g. slot in the MSI-X table or * a software managed index if >= 0. If negative From patchwork Fri Nov 11 13:58:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18839 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760772wru; Fri, 11 Nov 2022 06:09:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf4AxpT1046FwDItEMXILxuVsEza5HVbM9c+MbKeTgAILWEonprCBWuHsHtxnJN2C8n0d40C X-Received: by 2002:a17:902:9684:b0:187:4467:7aba with SMTP id n4-20020a170902968400b0018744677abamr2427983plp.61.1668175766274; Fri, 11 Nov 2022 06:09:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175766; cv=none; d=google.com; s=arc-20160816; b=n3I/I4gTPkrghELHiXhIapmusgcAjuUKzDpFar4PSmyfVhw14rhAkYqM//2Tca7UMF NhoD0Y9ZncVpDTsRqS3J2hrV27aS/rxSWLyMR3uAUlMawJhYRIIXcnz38a0tJ9Udg7VD lAqfxWUaWtbLj8mdnlddOQtgxGnHrruPZJWV+LRiLA176p6Zi73sIyrQKxV7qkD6B4n7 /aTznZS2lqHmLKRDvXLtld1VyRpiAOdNhCeU6jpsAr0CorpcCFQP858hRC/Ti2bVTLeS nMeilofAIkRqKqkSDDx/CNrOv1Gh6x/H1JTU1QfcM6AfaNfcVK0FD5H0aOQaxdlt5JHL dqTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=cGLnImP++QaosYDzBZBUnGto50NkhFSNjBnCsi02MnQ=; b=1CI5s4JbsD5rgBXXq79M055z5vZQAbuwbyj6gq1C0oP7F93Gz9/JE0A/b02pVJP2bS vtbU97AaA/t79sHfTwXsdrAwMhbTUWcd0c+CDLl12Hdz1i16HzDUNbfVgGda07TZBzng qT93Rwh7ryFuH7itOdHjqA4RDHsTHylXEkEjEX+nGSQl5HU37yNPAauUdlYRGIa6bMOv C1Ds/uxLkaKrxMgmBuAR6+QjtUrmzPox7MqQumwgVAS3kyBQhEe8Psu6JypzoDUZXVYx oQTFWdz3+GOy+S03ko4gi+mhgxNjBoWLvSgQTQPjIWTKBjgW9OIlUHrXHYosD3yLNcXC bevw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=qfvperWG; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=v3L5zUf2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 189-20020a6306c6000000b0044fb332e9c2si2416081pgg.560.2022.11.11.06.09.10; Fri, 11 Nov 2022 06:09:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=qfvperWG; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=v3L5zUf2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234477AbiKKOIQ (ORCPT + 99 others); Fri, 11 Nov 2022 09:08:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234602AbiKKOHM (ORCPT ); Fri, 11 Nov 2022 09:07:12 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC7C78A8D5; Fri, 11 Nov 2022 06:00:01 -0800 (PST) Message-ID: <20221111135206.406883343@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175123; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cGLnImP++QaosYDzBZBUnGto50NkhFSNjBnCsi02MnQ=; b=qfvperWGjkfJNozEsSouIgE/VudvhsIG+is6vXIvkjLnCjmFki9GuooJijW/Cpw6Qc+yDt qIXGBdaoV4Zeh5D6WGe19uU39+vMnK6XMJzCY4jzDKeWfMLyA103H++zWnsFbqQTHP3MIm PkLVBpHRAQimzZJ1O3wPmXgumKW8NGCNmc4FsUa6XzpmC1UD7sZ1SKD2cZH0cXjm99iBjI F1f6fFs0r3O6aTYjC6xt03EcNAe/OvYD5OLQ3oACZM+pkVrSiFPfQ6G5Z8ArVHIn3QOHR/ A7Z22jQVC/K94tgBn4t2mWhn0rqB1wMkTrlM8Ryd3+qtvxpeQ/MX0GN29/pmaQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175123; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cGLnImP++QaosYDzBZBUnGto50NkhFSNjBnCsi02MnQ=; b=v3L5zUf2VLairh9ucPPjVk/k1bfNBGpvEaxB1GV5CF1yCXHMMLFwnrchUDBnz30PbLtKuc J63HQhQgwqN53MDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:43 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209072554097289?= X-GMAIL-MSGID: =?utf-8?q?1749209072554097289?= The existing MSI domain ops msi_prepare() and set_desc() turned out to be unsuitable for implementing IMS support. msi_prepare() does not operate on the MSI descriptors. set_desc() lacks an irq_domain pointer and has a completely different purpose. Introduce a prepare_desc() op which allows IMS implementations to amend an MSI descriptor which was allocated by the core code, e.g. by adjusting the iomem base or adding some data based on the allocated index. This is way better than requiring that all IMS domain implementations preallocate the MSI descriptor and then allocate the interrupt. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 6 +++++- kernel/irq/msi.c | 3 +++ 2 files changed, 8 insertions(+), 1 deletion(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -379,6 +379,8 @@ struct msi_domain_info; * @msi_init: Domain specific init function for MSI interrupts * @msi_free: Domain specific function to free a MSI interrupts * @msi_prepare: Prepare the allocation of the interrupts in the domain + * @prepare_desc: Optional function to prepare the allocated MSI descriptor + * in the domain * @set_desc: Set the msi descriptor for an interrupt * @domain_alloc_irqs: Optional function to override the default allocation * function. @@ -390,7 +392,7 @@ struct msi_domain_info; * @get_hwirq, @msi_init and @msi_free are callbacks used by the underlying * irqdomain. * - * @msi_check, @msi_prepare and @set_desc are callbacks used by the + * @msi_check, @msi_prepare, @prepare_desc and @set_desc are callbacks used by the * msi_domain_alloc/free_irqs*() variants. * * @domain_alloc_irqs, @domain_free_irqs can be used to override the @@ -413,6 +415,8 @@ struct msi_domain_ops { int (*msi_prepare)(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *arg); + void (*prepare_desc)(struct irq_domain *domain, msi_alloc_info_t *arg, + struct msi_desc *desc); void (*set_desc)(msi_alloc_info_t *arg, struct msi_desc *desc); int (*domain_alloc_irqs)(struct irq_domain *domain, --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1275,6 +1275,9 @@ static int __msi_domain_alloc_irqs(struc if (WARN_ON_ONCE(allocated >= ctrl->nirqs)) return -EINVAL; + if (ops->prepare_desc) + ops->prepare_desc(domain, &arg, desc); + ops->set_desc(&arg, desc); virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used, From patchwork Fri Nov 11 13:58:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18853 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp779854wru; Fri, 11 Nov 2022 06:43:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf75h/v2h7RDJK/99cV89QsdScShzA2VLeb5x0Co/ZptGLKUR8Y651O5r/2emH6yVejZYCBF X-Received: by 2002:a17:90a:8990:b0:212:dc2f:7ee7 with SMTP id v16-20020a17090a899000b00212dc2f7ee7mr2161379pjn.172.1668177823834; Fri, 11 Nov 2022 06:43:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668177823; cv=none; d=google.com; s=arc-20160816; b=ETsWx3I6lxyjL+omdSsuLnTx2hLQWAsgQI6c+SK5q5TaRY/Qm60uCYqQl5pSd3bYPK qJfpyeq0zr07oZyhwUDwTTXt64Nx3bNsABjnNO1aacMPpJRo9SGkHstDEoUk/mANrA5d 6AGd1XIJC3HwCANFYym3a7lz0xxuX5K7zGn5KnLvzQfYLBVPAUNrYx3H0Xu9ZepZv454 eQ01Pakd+yFYYwtefqPLBwUnlX9kVWpPWiv1/pU31XVOkdIznrq1eUsqQJLyKZLHnzoq BBoATbtXTReGhAJiaqTlLx6xajyTDu0al+4d68mHV79sqS6ADbFBEu1aFxpCdpeM4pya kBPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=fxLPSxIR9ZSTFaDUWsnR87RJL6z40jyNrKWhIshWH24=; b=E2sxfZBXLhwpDC1nlB58dPLMGQu1WmY9ORbHTYgrlOi25xMh+5uA5eo6BzCVjad+si 4dUjF0LRbS9bj5MbNoi46bD9AnmB4U8GvENd4jfXz+pTYmRBYP+AEgfIP9H7FyoFLIUw wYBqVFAMo5/5h9dLS7tGeeV60uEn7Ip3hAagBmRlY2QlPwGeFwEI6XCDpCQQmnJjBsuJ thwU9GaRDpFU6/VDivhc4UXiuuPvvJKY6keZzY6MvRzV32qvvmPUnxeNcgnh4cBuQZqZ LwoqUiRiAbXXP8VpmRNdSSEIxetcBDm632pgp8KLZpR4zDqepGfJO8L9xzGYKmOMPKTp u7Qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gr6TbLeA; dkim=neutral (no key) header.i=@linutronix.de header.b=ATFUOEfB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h4-20020a056a00170400b0056334b72215si2808282pfc.86.2022.11.11.06.43.28; Fri, 11 Nov 2022 06:43:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gr6TbLeA; dkim=neutral (no key) header.i=@linutronix.de header.b=ATFUOEfB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234555AbiKKOJP (ORCPT + 99 others); Fri, 11 Nov 2022 09:09:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234717AbiKKOH2 (ORCPT ); Fri, 11 Nov 2022 09:07:28 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 689EB8D7DF; Fri, 11 Nov 2022 06:00:09 -0800 (PST) Message-ID: <20221111135206.463650635@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=fxLPSxIR9ZSTFaDUWsnR87RJL6z40jyNrKWhIshWH24=; b=gr6TbLeAglJQA4CkKIu8La2LR+j4NvxNLSxGDetxfKPxYNQav72vYnviCrYCDLCAa9Atq5 1jV4Z+lPfKTkbz/YKiyiLdoovniJ8XpJrfOGpOJXWb68ygvUN3hYt/8IDwpLQBVfmFkfzp iCpcWLaMsa1W5cbBivMyZD4Z77BxlB4F5+EqAc8eacAku1E38KI/LjpBCc5DIyEO9vWkAW BD+L0znlUIDFS4DD2QNC2aIBPxziZnKVPlidD9PdefTVwuywXjk+a+igZCRDnTEkHbuTTS W00hpg+Y9axfBokUSrSmTvGXSofS3/FYJ47CC+LZrIMwJ2A0Mci5BkuVS+So6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=fxLPSxIR9ZSTFaDUWsnR87RJL6z40jyNrKWhIshWH24=; b=ATFUOEfBPF+bLWCFt9RheygXADG6b2cWwhn4hwR4Ev/sGKw76fIcEoGvjTj7FZE+F0Sv9u PI37+4wDpNkeCiBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:44 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749211230123732790?= X-GMAIL-MSGID: =?utf-8?q?1749211230123732790?= For supporting post MSI-X enable allocations and for the upcoming PCI/IMS support a seperate interface is required which allows not only the allocation of a specific index, but also the allocation of any, i.e. the next free index. The latter is especially required for IMS because IMS completely does away with index to functionality mappings which are often found in MSI/MSI-X implementation. But even with MSI-X there are devices where only the first few indices have a fixed functionality and the rest is freely assignable by software, e.g. to queues. msi_domain_alloc_irq_at() is also different from the range based interfaces as it always enforces that the MSI descriptor is allocated by the core code and not preallocated by the caller like the PCI/MSI[-X] enable code path does. msi_domain_alloc_irq_at() can be invoked with the index argument set to MSI_ANY_INDEX which makes the core code pick the next free index. The irq domain can provide a prepare_desc() operation callback in its msi_domain_ops to do domain specific post allocation initialization before the actual Linux interrupt and the associated interrupt descriptor and hierarchy alloccations are conducted. The function also takes an optional @cookie argument which is of type union msi_dev_cookie. This cookie is not used by the core code and is stored in the allocated msi_desc::data::cookie. The meaning of the cookie is completely implementation defined. In case of IMS this might be a PASID or a pointer to a device queue, but for the MSI core it's opaque and not used in any way. The function returns a struct msi_map which on success contains the allocated index number and the Linux interrupt number so the caller can spare the index to Linux interrupt number lookup. On failure map::index contains the error code and map::virq is 0. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 4 + include/linux/msi_api.h | 7 +++ kernel/irq/msi.c | 105 ++++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 105 insertions(+), 11 deletions(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -80,6 +80,7 @@ struct pci_dev; struct platform_msi_priv_data; struct device_attribute; struct irq_domain; +struct irq_affinity_desc; void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg); void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg); @@ -567,6 +568,9 @@ int msi_domain_alloc_irqs_range(struct d unsigned int first, unsigned int last); int msi_domain_alloc_irqs_all_locked(struct device *dev, unsigned int domid, int nirqs); +struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, unsigned int index, + const struct irq_affinity_desc *affdesc, + union msi_dev_cookie *cookie); void msi_domain_free_irqs_range_locked(struct device *dev, unsigned int domid, unsigned int first, unsigned int last); --- a/include/linux/msi_api.h +++ b/include/linux/msi_api.h @@ -48,6 +48,13 @@ struct msi_map { int virq; }; +/* + * Constant to be used for dynamic allocations when the allocation + * is any free MSI index (entry in the MSI-X table or a software + * managed index. + */ +#define MSI_ANY_INDEX UINT_MAX + unsigned int msi_domain_get_virq(struct device *dev, unsigned int domid, unsigned int index); /** --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -39,6 +39,7 @@ static inline int msi_sysfs_create_group /* Invalid XA index which is outside of any searchable range */ #define MSI_XA_MAX_INDEX (ULONG_MAX - 1) #define MSI_XA_DOMAIN_SIZE (MSI_MAX_INDEX + 1) +#define MSI_ANY_INDEX UINT_MAX static inline void msi_setup_default_irqdomain(struct device *dev, struct msi_device_data *md) { @@ -126,18 +127,34 @@ static int msi_insert_desc(struct device } hwsize = msi_domain_get_hwsize(dev, domid); - if (index >= hwsize) { - ret = -ERANGE; - goto fail; - } - desc->msi_index = index; - index += baseidx; - ret = xa_insert(&md->__store, index, desc, GFP_KERNEL); - if (ret) - goto fail; - return 0; + if (index == MSI_ANY_INDEX) { + struct xa_limit limit; + unsigned int index; + + limit.min = baseidx; + limit.max = baseidx + hwsize - 1; + /* Let the xarray allocate a free index within the limits */ + ret = xa_alloc(&md->__store, &index, desc, limit, GFP_KERNEL); + if (ret) + goto fail; + + desc->msi_index = index; + return 0; + } else { + if (index >= hwsize) { + ret = -ERANGE; + goto fail; + } + + desc->msi_index = index; + index += baseidx; + ret = xa_insert(&md->__store, index, desc, GFP_KERNEL); + if (ret) + goto fail; + return 0; + } fail: msi_free_desc(desc); return ret; @@ -335,7 +352,7 @@ int msi_setup_device_data(struct device msi_setup_default_irqdomain(dev, md); - xa_init(&md->__store); + xa_init_flags(&md->__store, XA_FLAGS_ALLOC); mutex_init(&md->mutex); md->__iter_idx = MSI_XA_MAX_INDEX; dev->msi.data = md; @@ -1423,6 +1440,72 @@ int msi_domain_alloc_irqs_all_locked(str return msi_domain_alloc_locked(dev, &ctrl); } +/** + * msi_domain_alloc_irq_at - Allocate an interrupt from a MSI interrupt domain at + * a given index - or at the next free index + * + * @dev: Pointer to device struct of the device for which the interrupts + * are allocated + * @domid: Id of the interrupt domain to operate on + * @index: Index for allocation. If @index == %MSI_ANY_INDEX the allocation + * uses the next free index. + * @affdesc: Optional pointer to an interrupt affinity descriptor structure + * @cookie: Optional pointer to a descriptor specific cookie to be stored + * in msi_desc::data. Must be NULL for MSI-X allocations + * + * This requires a MSI interrupt domain which lets the core code manage the + * MSI descriptors. + * + * Return: struct msi_map + * + * On success msi_map::index contains the allocated index number and + * msi_map::virq the corresponding Linux interrupt number + * + * On failure msi_map::index contains the error code and msi_map::virq + * is %0. + */ +struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, unsigned int index, + const struct irq_affinity_desc *affdesc, + union msi_dev_cookie *cookie) +{ + struct irq_domain *domain; + struct msi_map map = { }; + struct msi_desc *desc; + int ret; + + msi_lock_descs(dev); + domain = msi_get_device_domain(dev, domid); + if (!domain) { + map.index = -ENODEV; + goto unlock; + } + + desc = msi_alloc_desc(dev, 1, affdesc); + if (!desc) { + map.index = -ENOMEM; + goto unlock; + } + + if (cookie) + desc->data.cookie = *cookie; + + ret = msi_insert_desc(dev, desc, domid, index); + if (ret) { + map.index = ret; + goto unlock; + } + + map.index = desc->msi_index; + ret = msi_domain_alloc_irqs_range_locked(dev, domid, map.index, map.index); + if (ret) + map.index = ret; + else + map.virq = desc->irq; +unlock: + msi_unlock_descs(dev); + return map; +} + static void __msi_domain_free_irqs(struct device *dev, struct irq_domain *domain, struct msi_ctrl *ctrl) { From patchwork Fri Nov 11 13:58:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18834 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760516wru; Fri, 11 Nov 2022 06:08:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf6WV0KBbgu1+BDus3RQMB/WHvtTFBrSidyYCDOkdzTlKG9rsFOAxLv9J+9joFdhbHupNKpF X-Received: by 2002:a63:dd4f:0:b0:470:14fa:a294 with SMTP id g15-20020a63dd4f000000b0047014faa294mr1794324pgj.361.1668175739517; Fri, 11 Nov 2022 06:08:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175739; cv=none; d=google.com; s=arc-20160816; b=uPY88Hf0V+Q5mqasYCYUl1bKJd19Bn1j7dAac4xYWwWQefpALAkcLwbBygfg/izuuG yh0oPx7d6CzZIcgMrLINwASlKzJPthwRZuPZD85kZd6Ul3wdDtz9TZDH0LKSYQJLZZLO stPbLzxOsMLeTE4qdEkDNf60oW49BO8g1Encx6kch15wsDArkMvkPOEfbhudoENG3jeq P+UkM+uGGn3PdrEI7C3OQDKcZ7bSxF9tOfdJQkVwBoqPoccLC2jN1/3tx9b3JOeF3v13 gjjKEsOE5dR8QBbP/B6xEoiHtfDciMeqZLouOZVyL4onNSonR9gpy4jy4Io32vgTsAJr B96g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=LtweMGx7oKuU2/h3mTO1bStczI1HafJrlhjPsVZ18gQ=; b=Zd+vXdtjmA0c/8Uk0uXc+pL4OtMyqzRaFJBac5EOFYi5HzyBd1aHbdN201IGiQ8j9Y +Nbmjs8C1Y52uYkvIQs0iqX6XtdjPL5zqNWihyJ8rpq0vlASui1DGjkzs/TuLyUfFIi3 EoLzZBJN2r+8Y3OO/1ZBwDXB1vqbBkqKGlrNTo2JYS5wjl5v3CrjcuKCYHVuFr4uZPWA VRr/ywSgAfU0zg+cAYUZUrlObPQcY1a8CMC2ab3QIDXym3AKHPqYX6uUI5DowYjRPhvW tVdmTyA32I8D0ZDU3No3rknqMSIsG/bsbrJA3XIyVeIJWlHqozGnKbmSD+ucMwCUUmNe cVxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Ctm1DuFD; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:46 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209044188890648?= X-GMAIL-MSGID: =?utf-8?q?1749209044188890648?= Provide a new MSI feature flag in preparation for dynamic MSIX allocation after the initial MSI-X enable has been done. This needs to be an explicit MSI interrupt domain feature because quite some implementations (both interrupt domains and legacy allocation mode) have clear expectations that the allocation code is only invoked when MSI-X is about to be enabled. They either talk to hypervisors or do some other work and are not prepared to be invoked on an already MSI-X enabled device. This is also explicit MSI-X only because rewriting the size of the MSI entries is only possible when disabling MSI which in turn might cause lost interrupts on the device. Signed-off-by: Thomas Gleixner Reviewed-by: Jason Gunthorpe --- include/linux/msi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -523,7 +523,8 @@ enum { MSI_FLAG_LEVEL_CAPABLE = (1 << 18), /* MSI-X entries must be contiguous */ MSI_FLAG_MSIX_CONTIGUOUS = (1 << 19), - + /* PCI/MSI-X vectors can be dynamically allocated/freed post MSI-X enable */ + MSI_FLAG_PCI_MSIX_ALLOC_DYN = (1 << 20), }; /** From patchwork Fri Nov 11 13:58:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18837 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760608wru; Fri, 11 Nov 2022 06:09:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf4n9cbLehh020kbmE/9ppyqhawMg0jJbXF13iPgzanjNcPARM8crVaLzmrlO0UP1SGJwvAD X-Received: by 2002:a17:90a:73cf:b0:213:7f5:a972 with SMTP id n15-20020a17090a73cf00b0021307f5a972mr2132304pjk.159.1668175750570; Fri, 11 Nov 2022 06:09:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175750; cv=none; d=google.com; s=arc-20160816; b=b74dNDBJYMGI6w/jgv6VY9MjhEg/8gadlYomIUCbwe2Nltxjhg3UzB2F+6JAWlx6uK b8EnK0fJoHklcIUZrKOFs5EovOSAWTcEuzXknlFI5qiXefcCeOvL8M6/OW34ZJh2aOog hlK8LoEm6o96xdPcirpIL8SHhtKG5aTA+Io98yvLTrLhghvSb+c7ul34/ccFsFKWu7t5 VdKMRcegjjBm02160rtqoflEnOOYmqiUlVXpePpge2zg7MPaKZosYalJ66sLBGQCMi6v Uhj57iEjQtKNMyyVVVlhswWeJ/6F7/+ig6Q2pq6vQt5tPrZLAazsMTXkEORhZyjcxLNK fV4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=mJmHAB47qeb6IUi2Y32Du0kAFRIPWB4ryIU41lcPdlU=; b=g8eK7DoVyGd+YQQvoI2XUtMRoADRRllwGBanYUajkCd9NqXDf+8igKQc53kvZGtqlM cjqMb2SQGumtwlwgN42Z4PVxCdYbs/yBum/HJBhozISWWvjdzoNW9IBDlvss+Is9uha7 L6Bhac/aNvIvzDOyNX5nE052cMSAar35xOgfpbXiCMkunZgVgAZo+XHRN9Sh2GI8SLDl wMWUQ9jf/Lx9as1oekLOJHmqGA5MjXDNY3fevTW+xsXiDnrXBiyampWUyBy6nB4f4uSn dxw7R4dPmXW+oPv2XAowEJdk8aWMB6rHW1OUv6xKlNsPlyizZZUVKVy71WjEmk4Ir2OB Wxcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Es3G7f5r; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=6ykBQdi9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j189-20020a6380c6000000b0046fad96095esi2404308pgd.478.2022.11.11.06.08.56; Fri, 11 Nov 2022 06:09:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Es3G7f5r; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=6ykBQdi9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234463AbiKKOII (ORCPT + 99 others); Fri, 11 Nov 2022 09:08:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234538AbiKKOHE (ORCPT ); Fri, 11 Nov 2022 09:07:04 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BABF8BA9A; Fri, 11 Nov 2022 05:59:54 -0800 (PST) Message-ID: <20221111135206.577311313@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175128; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=mJmHAB47qeb6IUi2Y32Du0kAFRIPWB4ryIU41lcPdlU=; b=Es3G7f5rs9OUwN0q+XJwuuFDMW8Sa2dIkA12T5rGe149QBr/Clg5tg3h8KS6Y3lqOa7DKX kRVv6kb2e1gjqdIFdViIls/t/v7qWcRjlwusBOAPvVXM5t4H8Esa7Q+iMTqIR5+AJzwiXs IW6Gooq0mT56hnTJuFQXGQXcIj1u4OEyGOLCgAn01oR1ZupSRLuzXFYR5tcxQDzui+mBD/ 2xQ7yV6JTIadLwBURynsakqriTw8lPNKvEliTG5+gUmnTqjxx7ikY5tPYJ2h2eBxDP1tKN Vx04jvfc/6f67c//TP5yJY2hJRNY/TI7zHpp3Jwm9igMThHROOXGFSOhSr3Tqg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175128; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=mJmHAB47qeb6IUi2Y32Du0kAFRIPWB4ryIU41lcPdlU=; b=6ykBQdi9Jjv/HQF5V93KoQiWqbkwO8yTGjUI40h6Kqi9dJ6z7H6qF/h2kI9Cag9s/igkqe zkr2QnymqOLTMXDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 23/33] PCI/MSI: Split MSIX descriptor setup References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:47 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209055527899525?= X-GMAIL-MSGID: =?utf-8?q?1749209055527899525?= The upcoming mechanism to allocate MSI-X vectors after enabling MSI-X needs to share some of the MSI-X descriptor setup. The regular descriptor setup on enable has the following code flow: 1) Allocate descriptor 2) Setup descriptor with PCI specific data 3) Insert descriptor 4) Allocate interrupts which in turn scans the inserted descriptors This cannot be easily changed because the PCI/MSI code needs to handle the legacy architecture specific allocation model and the irq domain model where quite some domains have the assumption that the above flow is how it works. Ideally the code flow should look like this: 1) Invoke allocation at the MSI core 2) MSI core allocates descriptor 3) MSI core calls back into the irq domain which fills in the domain specific parts This could be done for underlying parent MSI domains which support post-enable allocation/free but that would create significantly different code pathes for MSI/MSI-X enable. Though for dynamic allocation which wants to share the allocation code with the upcoming PCI/IMS support its the right thing to do. Split the MSIX descriptor setup into the preallocation part which just sets the index and fills in the horrible hack of virtual IRQs and the real PCI specific MSI-X setup part which solely depends on the index in the descriptor. This allows to provide a common dynami allocation interface at the MSI core level for both PCI/MSI-X and PCI/IMS. Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/msi.c | 72 +++++++++++++++++++++++++++++++------------------- drivers/pci/msi/msi.h | 2 + 2 files changed, 47 insertions(+), 27 deletions(-) --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -569,34 +569,56 @@ static void __iomem *msix_map_region(str return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); } -static int msix_setup_msi_descs(struct pci_dev *dev, void __iomem *base, - struct msix_entry *entries, int nvec, - struct irq_affinity_desc *masks) +/** + * msix_prepare_msi_desc - Prepare a half initialized MSI descriptor for operation + * @dev: The PCI device for which the descriptor is prepared + * @desc: The MSI descriptor for preparation + * + * This is seperate from msix_setup_msi_descs() below to handle dynamic + * allocations for MSIX after initial enablement. + * + * Ideally the whole MSIX setup would work that way, but there is no way to + * support this for the legacy arch_setup_msi_irqs() mechanism and for the + * fake irq domains like the x86 XEN one. Sigh... + * + * The descriptor is zeroed and only @desc::msi_index and @desc::affinity + * are set. When called from msix_setup_msi_descs() then the is_virtual + * attribute is initialized as well. + * + * Fill in the rest. + */ +void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc) +{ + desc->nvec_used = 1; + desc->pci.msi_attrib.is_msix = 1; + desc->pci.msi_attrib.is_64 = 1; + desc->pci.msi_attrib.default_irq = dev->irq; + desc->pci.mask_base = dev->msix_base; + desc->pci.msi_attrib.can_mask = !pci_msi_ignore_mask && + !desc->pci.msi_attrib.is_virtual; + + if (desc->pci.msi_attrib.can_mask) { + void __iomem *addr = pci_msix_desc_addr(desc); + + desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + } +} + +static int msix_setup_msi_descs(struct pci_dev *dev, struct msix_entry *entries, + int nvec, struct irq_affinity_desc *masks) { int ret = 0, i, vec_count = pci_msix_vec_count(dev); struct irq_affinity_desc *curmsk; struct msi_desc desc; - void __iomem *addr; memset(&desc, 0, sizeof(desc)); - desc.nvec_used = 1; - desc.pci.msi_attrib.is_msix = 1; - desc.pci.msi_attrib.is_64 = 1; - desc.pci.msi_attrib.default_irq = dev->irq; - desc.pci.mask_base = base; - for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) { desc.msi_index = entries ? entries[i].entry : i; desc.affinity = masks ? curmsk : NULL; desc.pci.msi_attrib.is_virtual = desc.msi_index >= vec_count; - desc.pci.msi_attrib.can_mask = !pci_msi_ignore_mask && - !desc.pci.msi_attrib.is_virtual; - if (desc.pci.msi_attrib.can_mask) { - addr = pci_msix_desc_addr(&desc); - desc.pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); - } + msix_prepare_msi_desc(dev, &desc); ret = msi_insert_msi_desc(&dev->dev, &desc); if (ret) @@ -629,9 +651,8 @@ static void msix_mask_all(void __iomem * writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL); } -static int msix_setup_interrupts(struct pci_dev *dev, void __iomem *base, - struct msix_entry *entries, int nvec, - struct irq_affinity *affd) +static int msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries, + int nvec, struct irq_affinity *affd) { struct irq_affinity_desc *masks = NULL; int ret; @@ -640,7 +661,7 @@ static int msix_setup_interrupts(struct masks = irq_create_affinity_masks(nvec, affd); msi_lock_descs(&dev->dev); - ret = msix_setup_msi_descs(dev, base, entries, nvec, masks); + ret = msix_setup_msi_descs(dev, entries, nvec, masks); if (ret) goto out_free; @@ -678,7 +699,6 @@ static int msix_setup_interrupts(struct static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, int nvec, struct irq_affinity *affd) { - void __iomem *base; int ret, tsize; u16 control; @@ -696,15 +716,13 @@ static int msix_capability_init(struct p pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); /* Request & Map MSI-X table region */ tsize = msix_table_size(control); - base = msix_map_region(dev, tsize); - if (!base) { + dev->msix_base = msix_map_region(dev, tsize); + if (!dev->msix_base) { ret = -ENOMEM; goto out_disable; } - dev->msix_base = base; - - ret = msix_setup_interrupts(dev, base, entries, nvec, affd); + ret = msix_setup_interrupts(dev, entries, nvec, affd); if (ret) goto out_disable; @@ -719,7 +737,7 @@ static int msix_capability_init(struct p * which takes the MSI-X mask bits into account even * when MSI-X is disabled, which prevents MSI delivery. */ - msix_mask_all(base, tsize); + msix_mask_all(dev->msix_base, tsize); pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); pcibios_free_irq(dev); --- a/drivers/pci/msi/msi.h +++ b/drivers/pci/msi/msi.h @@ -84,6 +84,8 @@ static inline __attribute_const__ u32 ms return (1 << (1 << desc->pci.msi_attrib.multi_cap)) - 1; } +void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc); + /* Subsystem variables */ extern int pci_msi_enable; From patchwork Fri Nov 11 13:58:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18835 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp760574wru; Fri, 11 Nov 2022 06:09:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf4TC+c5BY23wAHN4e1nP5ie/sFXMmiqm+sBIsPpejffBRbdABnbgOEdAbdCOfJQr0iDn6ly X-Received: by 2002:a63:4146:0:b0:46f:8c3a:8b2b with SMTP id o67-20020a634146000000b0046f8c3a8b2bmr1816644pga.477.1668175746582; Fri, 11 Nov 2022 06:09:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175746; cv=none; d=google.com; s=arc-20160816; b=ajsMbKJp0qTWFF1GDjq32+MB14WQAwthw6CBrE7/UEL5vC0M90bIomwvOsvq6CA4Lp AWB17EwzQ49km5w0GnQmA4ilazL7xNoiQ+JOy0mGDg2ICZO2czysO5h50ZAwgsvvIOqF 2a0MOhFEwp57WhJVn+5sAY/ChrF5Z8ynWApsFJtGtL6peKFclL/8xpNxur6flszzfdaj EdxuppfNtCwC7dEkfinbeBKZZgA822/EW4G1UVcg5hiYWJABkCIz31Jt3BDlOcbQzbOk YVjUfoqVlyE4C4FGMJtgNr8E8eWwL5rT2OQxm5w6+OvtownjNfviA/EZTBXBj1gBbwDr vpjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=JjWom/9kwklaxMWDn9npHnU2VscMDs0fiXQjZmDEcT0=; b=wC3zklymvqhpG0znMrfWJkNaeWcFwt2K1jqaUmFQFF+qKIJxSEDbOC01TGIEA+alGp sjt9uvDk0b8R16/aVGr8CdmV1tYKxJxhro/GMm8oyl6ds8YRx648BoNOs6yyGBg+Jya1 q8Ras4hLgfhaML6TPIvksq7LcBR3bs82gmatASRBe1nT45PqcuQYIltlTRcl7RjS8n4w bqSlRIKdUc44ArNk+qXrwptpWz5HxTmpQkEg4LfVIve1q1bR48abCWfrGwAPCbZDRUHx RkCZMKrg+nI9J7JFGQ1Y8VtIKUY4VSdyfdNsTBkOHVuNgoluXlDyhyRBiQBHiimcyoSg lk2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ahkaO7sq; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="+b/g6Jio"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 24/33] PCI/MSI: Provide prepare_desc() MSI domain op References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:49 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209052120306999?= X-GMAIL-MSGID: =?utf-8?q?1749209052120306999?= Dynamic MSI-X vector allocation post MSI-X allows to allocate vectors at a given index or at any free index in the available table range. The latter requires that the core code selects the index at descriptor allocation time. This requires that the PCI/MSI-X specific setup of the MSI-X descriptor, which is partially depending on the chosen index happens after allocation. Implement the prepare_desc() op in the PCI/MSI-X specific msi_domain_ops which is invoked before the core interrupt descriptor and the associated Linux interrupt number is allocated. That callback is also provided for the upcoming PCI/IMS implementations so the implementation specific interrupt domain can do their domain specific initialization of the MSI descriptors. Signed-off-by: Thomas Gleixner Reviewed-by: Jason Gunthorpe Acked-by: Bjorn Helgaas --- drivers/pci/msi/irqdomain.c | 9 +++++++++ 1 file changed, 9 insertions(+) --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -202,6 +202,14 @@ static void pci_unmask_msix(struct irq_d pci_msix_unmask(irq_data_get_msi_desc(data)); } +static void pci_msix_prepare_desc(struct irq_domain *domain, msi_alloc_info_t *arg, + struct msi_desc *desc) +{ + /* Don't fiddle with preallocated MSI descriptors */ + if (!desc->pci.mask_base) + msix_prepare_msi_desc(to_pci_dev(desc->dev), desc); +} + static struct msi_domain_template pci_msix_template = { .chip = { .name = "PCI-MSIX", @@ -212,6 +220,7 @@ static struct msi_domain_template pci_ms }, .ops = { + .prepare_desc = pci_msix_prepare_desc, .set_desc = pci_device_domain_set_desc, }, From patchwork Fri Nov 11 13:58:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18852 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp777667wru; Fri, 11 Nov 2022 06:39:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf4ntmhb6p8OxBlPhCXCO2L6VgTifw5qLCShXteHs7eLc7dRi60KsD5eVu3MpfiPd9aspAOy X-Received: by 2002:a05:6402:205c:b0:461:9e1f:222b with SMTP id bc28-20020a056402205c00b004619e1f222bmr1632831edb.312.1668177572466; Fri, 11 Nov 2022 06:39:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668177572; cv=none; d=google.com; s=arc-20160816; b=zWCpD+8re24wAqY37hcU9OkEbKQREuFMLTImDfbWVE6Qka/Rc9oRJzShyviPkAt5JV v4n0UiG7YN1+EChi2JXe1pxWwgtonAODwTo2+xa6+et/7/E2k11FkVuyB7gGPp9M8Heq OO4G/OcK5hUN2tgUTbePaHqpqprb6A9p86/hemWfziNOLOCVvKkVvihMLo6jKHF0c7I6 YDcUVF3gWGj2FNR0mFDVMrdTnYaKMfxaDgtuhoPs27JLatdkguKVIldWWMZzGhWxaiST ELNebrbQviQjrsUR4nbBWPdJ+JKdA9S1+ghtr0VSFsf4iMlbL0UPxEJ5Gb1bxG68xD/a qF1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=8LlK3JaLUlNPvY1OMKf4DIZ6KPBnqoAfjrM8HhykhKw=; b=R0A9qD26CrrvdseKhJ9dXPen5eDq+pijZwL6n6ncUtM0qqsdMdIuDvyfDdX0aUVaWO LB1PH6nLQf+Pn5q2X50C7mrSuaU6j1g8WefYwNHuvNH6SbbnXt4Fc4LPSuR90TqcJRfS X/JbFJe3WEKRlCDiLRoELrjy/3Y71WPcToFP9Bo3JzFhKkpbMoi/JF98H2pedhDIXMgb 8WqQKBhU14+WwXP5WLrqT3Ri86H7Y8hqJql/Z2CMT5eQrZR2DPbamZUFiTwOruOQV4Ho bFlf/1T3bnb68a3kH2AjOf52SV/bQA0BC9SZ4YleFcXRQXXlSf0AFuKPaIyD4tWhXgTF cFlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Er05wIV3; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gb17-20020a170907961100b007827639faffsi2192381ejc.760.2022.11.11.06.39.07; Fri, 11 Nov 2022 06:39:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Er05wIV3; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234506AbiKKOJn (ORCPT + 99 others); Fri, 11 Nov 2022 09:09:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234874AbiKKOHs (ORCPT ); Fri, 11 Nov 2022 09:07:48 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E25C09B55B; Fri, 11 Nov 2022 06:00:23 -0800 (PST) Message-ID: <20221111135206.688367117@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175131; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8LlK3JaLUlNPvY1OMKf4DIZ6KPBnqoAfjrM8HhykhKw=; b=Er05wIV3y7qyjvKHAe9RHM3QTy3fJwOqgzu/VcwYLfx7ZwsTTFjMF6+0Imrtr3ibuoQ0nN 55tOvYFkgvSXcp5RTRpXkGT0EUEnkV9etxGpkhwWAnEF4da/H3bR7ENs0l2Uj5i4y58FPU PQkdHSe0AbeD/q90EluphJalKYr2NRkxgM/LisWMiKJPG5dUCZKIaZFJwRM+yTnN477C7U tu97FdP0R5lnrjOOT3FavfkvBmoKlTYvojRlIrwPWRr3Qi/JJcVRBMNESn1EmknKSqS9ve RFbq3mdQjyh9b+8Mvp1U2fd4/3AglhXpr0krNJsEg72XetXqTtEe1PSlOFL34A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175131; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8LlK3JaLUlNPvY1OMKf4DIZ6KPBnqoAfjrM8HhykhKw=; b=ptkecwef/JW8RO3aUBfzxGKEs8ZReI0FnVOn86e6JdzESmIs6tI37lSrIEayOc1aaQ1gCb PgR6vQUlhV/dEnAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:51 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749210966566924018?= X-GMAIL-MSGID: =?utf-8?q?1749210966566924018?= MSI-X vectors can be allocated after the initial MSI-X enablement, but this needs explicit support of the underlying interrupt domains. Provide a function to query the ability and functions to allocate/free individual vectors post-enable. The allocation can either request a specific index in the MSI-X table or with the index argument MSI_ANY_INDEX it allocates the next free vector. The return value is a struct msi_map which on success contains both index and the Linux interrupt number. In case of failure index is negative and the Linux interrupt number is 0. The allocation function is for a single MSI-X index at a time as that's sufficient for the most urgent use case VFIO to get rid of the 'disable MSI-X, reallocate, enable-MSI-X' cycle which is prone to lost interrupts and redirections to the legacy and obviously unhandled INTx. Also for the use cases Jason Gunthorpe pointed a single index allocation is sufficient. Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/api.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/msi/irqdomain.c | 3 + include/linux/pci.h | 6 +++ 3 files changed, 75 insertions(+), 1 deletion(-) --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -113,6 +113,73 @@ int pci_enable_msix_range(struct pci_dev EXPORT_SYMBOL(pci_enable_msix_range); /** + * pci_msix_can_alloc_dyn - Query whether dynamic allocation after enabling + * MSI-X is supported + * + * @dev: PCI device to operate on + * + * Return: True if supported, false otherwise + */ +bool pci_msix_can_alloc_dyn(struct pci_dev *dev) +{ + if (!dev->msix_cap) + return false; + + return pci_msi_domain_supports(dev, MSI_FLAG_PCI_MSIX_ALLOC_DYN, DENY_LEGACY); +} +EXPORT_SYMBOL_GPL(pci_msix_can_alloc_dyn); + +/** + * pci_msix_alloc_irq_at - Allocate an MSI-X interrupt after enabling MSI-X + * at a given MSI-X vector index or any free vector index + * + * @dev: PCI device to operate on + * @index: Index to allocate. If @index == MSI_ANY_INDEX this allocates + * the next free index in the MSI-X table + * @affdesc: Optional pointer to an affinity descriptor structure. NULL otherwise + * + * Return: A struct msi_map + * + * On success msi_map::index contains the allocated index (>= 0) and + * msi_map::virq the allocated Linux interrupt number (> 0). + * + * On fail msi_map::index contains the error code and msi_map::virq + * is set to 0. + */ +struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, + const struct irq_affinity_desc *affdesc) +{ + struct msi_map map = { .index = -ENOTSUPP }; + + if (!dev->msix_enabled) + return map; + + if (!pci_msix_can_alloc_dyn(dev)) + return map; + + return msi_domain_alloc_irq_at(&dev->dev, MSI_DEFAULT_DOMAIN, index, affdesc, NULL); +} +EXPORT_SYMBOL_GPL(pci_msix_alloc_irq_at); + +/** + * pci_msix_free_irq - Free an interrupt on a PCI/MSIX interrupt domain + * which was allocated via pci_msix_alloc_irq_at() + * + * @dev: The PCI device to operate on + * @map: A struct msi_map describing the interrupt to free + * as returned from the allocation function. + */ +void pci_msix_free_irq(struct pci_dev *dev, struct msi_map map) +{ + if (WARN_ON_ONCE(map.index < 0 || map.virq <= 0)) + return; + if (WARN_ON_ONCE(!pci_msix_can_alloc_dyn(dev))) + return; + msi_domain_free_irqs_range(&dev->dev, MSI_DEFAULT_DOMAIN, map.index, map.index); +} +EXPORT_SYMBOL_GPL(pci_msix_free_irq); + +/** * pci_disable_msix() - Disable MSI-X interrupt mode on device * @dev: the PCI device to operate on * --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -225,7 +225,8 @@ static struct msi_domain_template pci_ms }, .info = { - .flags = MSI_COMMON_FLAGS | MSI_FLAG_PCI_MSIX, + .flags = MSI_COMMON_FLAGS | MSI_FLAG_PCI_MSIX | + MSI_FLAG_PCI_MSIX_ALLOC_DYN, .bus_token = DOMAIN_BUS_PCI_DEVICE_MSIX, }, }; --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -1559,6 +1560,11 @@ int pci_alloc_irq_vectors_affinity(struc unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd); +bool pci_msix_can_alloc_dyn(struct pci_dev *dev); +struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, + const struct irq_affinity_desc *affdesc); +void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); + void pci_free_irq_vectors(struct pci_dev *dev); int pci_irq_vector(struct pci_dev *dev, unsigned int nr); const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); From patchwork Fri Nov 11 13:58:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp774007wru; Fri, 11 Nov 2022 06:32:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf6ZVDeXF8Rs5/1NzOnIqsnY5+u5Jyig3DGYKhvRXUfII8/IEmlPpXZsHuuD5gvO079W21tQ X-Received: by 2002:a05:6402:4447:b0:461:9f41:2960 with SMTP id o7-20020a056402444700b004619f412960mr1630670edb.242.1668177172336; Fri, 11 Nov 2022 06:32:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668177172; cv=none; d=google.com; s=arc-20160816; b=Go4OMUOHdOGzMZ5lxeq3nO4sRE6Swqgm6TMqI+s3lrJmPLSm5/a8CpvQK96qHHR8bW lFZponE+94uL+1TB/RpZ/9cvRf25dCz0Gy65VHlCYo/HacLtn6DHyHgw8IAxHiDi0RmT kL75N/L8VHsPRgFDQOVMhMK6BFlTBn9hkcxQPmj+ff6rGek2beyq2a8SqvawdLm1qp9j 70jTKX50Egz/XjKi8X9wTGHOl5ANJi3XquS0sEuKUxNCKexvwzYW55GsCT2FGOaY/sXb 0M+seP93M89wb6fl8M7evwET8DaDgEj77BKkJ9D1n6uUWqTQpeGRcJdRGTwm/R1m7uji 1ATw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=IEK08cS7O6Uv3gBo3cg3kU1MfAmms/KMIPye21Vs0c0=; b=P6SS0uaN/RgvhU0XcL4JUOaR8Q6HWfGNM3HC8It67+8QW4J44ZQ2+9mF2XnSJK2rT+ wh0KLs/L2w5TxmFoqXfmPHat4WPfxniw+FYtTBFVfoRjb06061mx29aQ5LRLQvSBuxkF HLSupC5xDKvjXitkTt3gELW8y9u3oiFqjdrdLjcM3/KvWPzF6tFi1Ciu46I6V28AfOhU TsOyW+IV7WV/hNCa4oTAwniirfe2twmUdDUwG++ByGnRclA5cA99hzdMnWV54iXlRGlJ r4+vI36rf2cSZwATcEnUJrrf8+ndLH3bPHRf5LfhvcEBOXiLN6X5hjDm1e/gtrG93r1A YyEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IAhJ5osT; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=RmDxjYpt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:52 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749210546314471310?= X-GMAIL-MSGID: =?utf-8?q?1749210546314471310?= x86 MSI irqdomains can handle MSI-X allocation post MSI-X enable just out of the box - on the vector domain and on the remapping domains, Add the feature flag to the supported feature list Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/msi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/include/asm/msi.h +++ b/arch/x86/include/asm/msi.h @@ -63,7 +63,7 @@ struct msi_msg; u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid); #define X86_VECTOR_MSI_FLAGS_SUPPORTED \ - (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX) + (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX | MSI_FLAG_PCI_MSIX_ALLOC_DYN) #define X86_VECTOR_MSI_FLAGS_REQUIRED \ (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS) From patchwork Fri Nov 11 13:58:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18845 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp762154wru; Fri, 11 Nov 2022 06:11:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf5h+V8hypDJT1IpqpPmOsbwCrZImomQR9mw8UKPkXQKZRUN2JsFfBAuFbV/WFXfo30geEZ3 X-Received: by 2002:a17:902:cf01:b0:176:90e2:7d6d with SMTP id i1-20020a170902cf0100b0017690e27d6dmr2545856plg.10.1668175904212; Fri, 11 Nov 2022 06:11:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175904; cv=none; d=google.com; s=arc-20160816; b=I1SZHVwzoWFo/zP1tvjUytiiTppg5sZrzDmTo3k1UkjFBqAu+f1JPzyUSR4KA2r0Dz 7gJIbRxedyfzcgVjRQpXn6ByUmxJCI2AD8+GBtsECIYEV/QMZkHGuGJRx2XKlJVt8KT7 JxI3atV5RWlPfY/HsFU0eMho2DXpQ/3epJyol4PBaDUl/yUfQsTlMJv0Z36W2WpfKdDb ks+dQwR2Rc2p1zbxNOo8+D9F+hfrVsgwFi3jHw/g662S9O+TShhVis3H0nkM+A17vkj7 9JOw9tcdbNgaNh46TAgkvH+3V6kW8MMZYruLkq8vm3R5HOOFYQwQTGGDHnF24Pb9UrMI /3qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=7fmcFX1MJSQKPJVgurNTrf9/R1xe0is9IBLZWgzTjmw=; b=JmIjIdrwIVQeFmSYCvh9iE9sVrMdyPgc6N2yDk4b54tQkUk0GYlQiU0gKBdjLJNTk8 lbr4Y1Ot176RAGsEt9QHbNK047wq18mK7JKT1IoRam4D15qIqDX6nLWZq95vUt52Vyab druD9ih08CXnMXd3/SWMVrTtsUiQwmPBTOAPMkW/jDdl/CEQ1xhZwS8kNv2I8C4b1bnh K8jZApP8Gr9JsdiRZi+qbA2xrAEBO8stoNg4tVWIK06Obw5pqhQaVRkAxaUo1RmDCWt+ g8CAJbUX0pMqadv/JICJ66I0wxXK3BizThfN7jSZb4BxXEoB0iMo3aG/zsLB/thB8UG2 M2wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="ikIR/AeS"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=L5+0eNKf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 27/33] genirq/msi: Provide constants for PCI/IMS support References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:54 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209216830506650?= X-GMAIL-MSGID: =?utf-8?q?1749209216830506650?= Provide the necessary constants for PCI/IMS support: - A new bus token for MSI irqdomain identification - A MSI feature flag for the MSI irqdomains to signal support - A secondary domain id The latter expands the device internal domain pointer storage array from 1 to 2 entries. That extra pointer is mostly unused today, but the alternative solutions would not be free either and would introduce more complexity all over the place. Trade the 8bytes for simplicity. Signed-off-by: Thomas Gleixner --- include/linux/irqdomain_defs.h | 1 + include/linux/msi.h | 2 ++ include/linux/msi_api.h | 1 + 3 files changed, 4 insertions(+) --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -25,6 +25,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_PCI_DEVICE_MSIX, DOMAIN_BUS_DMAR, DOMAIN_BUS_AMDVI, + DOMAIN_BUS_PCI_DEVICE_IMS, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -525,6 +525,8 @@ enum { MSI_FLAG_MSIX_CONTIGUOUS = (1 << 19), /* PCI/MSI-X vectors can be dynamically allocated/freed post MSI-X enable */ MSI_FLAG_PCI_MSIX_ALLOC_DYN = (1 << 20), + /* Support for PCI/IMS */ + MSI_FLAG_PCI_IMS = (1 << 21), }; /** --- a/include/linux/msi_api.h +++ b/include/linux/msi_api.h @@ -15,6 +15,7 @@ struct device; */ enum msi_domain_ids { MSI_DEFAULT_DOMAIN, + MSI_SECONDARY_DOMAIN, MSI_MAX_DEVICE_IRQDOMAINS, }; From patchwork Fri Nov 11 13:58:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18843 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp761088wru; Fri, 11 Nov 2022 06:09:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf50VVY3GyoT7Clob8onMf02/RphJXg2RCfU4mF8CZTXgMogvpMQswBos4p+ku0xtPVRvTyo X-Received: by 2002:a63:5859:0:b0:470:537c:1092 with SMTP id i25-20020a635859000000b00470537c1092mr1830048pgm.287.1668175799330; Fri, 11 Nov 2022 06:09:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175799; cv=none; d=google.com; s=arc-20160816; b=JVf7cLonuhjOXxPOVSUZF/Hz1tduPbm/WP3+K95jcHXTW76zTtOPQKVeyjQSBe+BJn Gu6G0Bu/KczHiPvyzTznmoR+FpvXdhK1UMbiT6BhjFp0C5KNpp+THfhPIIBtpUmV+HNe kZqRIDPWx2+Oq9j+8WdTNxNsu7rR38dO9bLne8QP+RjdaSe4kerV3GfVnS/Snx10EB55 8ihZQRyDsaiflUjlQ7tz8LRacm/D3soUv4feGOUrSXdNG8frIppnsI3Mf9ZUkcOgE7HE XsYoaV3kzeqIHvb8iRuRPsC3srcgaYvdmOwpD0r8krEdCPjbMlkbSHOT8E5ESoBBckQM 0Lbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=c9JDBZM977tVyvqvJg00lI013oKo3dOFRASxZv3UZ8g=; b=DpiOQa9K2r8r5C/HwtaXCF/IHmALAOIZXa2bLdsScvIYp4lBfo3ZJWcNUzoxN56Fx5 TwCLtq1N4R8NVxzU/u+bnoZc4rUFrAB3jXSe36M9RhcrNmxY8jpiewk9yKy5eglsT7ur y5jU9xfHz4bS1/713g6YgVUHFcCkC6TBIJrkJi0qlNmHcSKqx0VAQ+QE1hRRyh3GjTB4 cWLXAjvaB2OYbXlUbgJnZ/vm4zdUaQX369Ww/Gw8hHy4wS1bsohMrZ9q2OBfMp8iTvcb t/S3ZFuDQ+5cgIeumuUKYogg3uqpAYptiZhTkeKGRbtUILjuD4Nzs0rZ0dEg2tCu8rlY Zdbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=q2n47ka+; dkim=neutral (no key) header.i=@linutronix.de header.b=g5YUbC+w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i10-20020a1709026aca00b0017deb323079si2451921plt.142.2022.11.11.06.09.45; Fri, 11 Nov 2022 06:09:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=q2n47ka+; dkim=neutral (no key) header.i=@linutronix.de header.b=g5YUbC+w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234524AbiKKOIq (ORCPT + 99 others); Fri, 11 Nov 2022 09:08:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234661AbiKKOHU (ORCPT ); Fri, 11 Nov 2022 09:07:20 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 389458BAAE; Fri, 11 Nov 2022 06:00:05 -0800 (PST) Message-ID: <20221111135206.855773120@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1668175136; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=c9JDBZM977tVyvqvJg00lI013oKo3dOFRASxZv3UZ8g=; b=q2n47ka+68YaG2yfEg3JjMEqBvlfMw+HAAVmfrlUIzHf/hVn9tC4G73cZH4sgE7h/hFhjp qxr3IfDx24nO5xUGb25jZsF0uKHf179qiyWk6lnRbX9ILRvabBtWuvIOwXldNT9ZBboTTs PgdDqWxOIddAEFSFwb9SIv72XNuMb97d7jG9xpGK1Kf4xJsicv8HuVfpfsjCC5vffZ1jxj xGsZR88YLVNmL6HOn9Jk995+vgSrk+02/4prrg4niVOZMbiTPpuZa+1FT4amlFv4ihFRn9 LHfFmb8m13vorv94hbuxTzs8dTzTOjYSHaVvHAMRj/iOrf/KyUs0dVPhfV6xgQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1668175136; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=c9JDBZM977tVyvqvJg00lI013oKo3dOFRASxZv3UZ8g=; b=g5YUbC+wZzhZLEQOjK7d4wtRAIdgARUsULHH+Sh+bi8sCZJAGFGrXCJgknnzYPLyDxVsDB LfqJdBHAqn2s+8Ag== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Joerg Roedel , Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Dave Jiang , Alex Williamson , Kevin Tian , Dan Williams , Logan Gunthorpe , Ashok Raj , Jon Mason , Allen Hubbe , "Ahmed S. Darwish" , Reinette Chatre Subject: [patch 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:55 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209107017071412?= X-GMAIL-MSGID: =?utf-8?q?1749209107017071412?= IMS (Interrupt Message Store) is a new specification which allows implementation specific storage of MSI messages contrary to the strict standard specified MSI and MSI-X message stores. This requires new device specific interrupt domains to handle the implementation defined storage which can be an array in device memory or host/guest memory which is shared with hardware queues. Add a function to create IMS domains for PCI devices. IMS domains are using the new per device domain mechanism and are configured by the device driver via a template. IMS domains are created as secondary device domains so they work side on side with MSI[-X] on the same device. The IMS domains have a few constraints: - The index space is managed by the core code. Device memory based IMS provides a storage array with a fixed size which obviously requires an index. But there is no association between index and functionality so the core can randomly allocate an index in the array. Queue memory based IMS does not have the concept of an index as the storage is somewhere in memory. In that case the index is purely software based to keep track of the allocations. - There is no requirement for consecutive index ranges This is currently a limitation of the MSI core and can be implemented if there is a justified use case by changing the internal storage from xarray to maple_tree. For now it's single vector allocation. - The interrupt chip must provide the following callbacks: - irq_mask() - irq_unmask() - irq_write_msi_msg() - The interrupt chip must provide the following optional callbacks when the irq_mask(), irq_unmask() and irq_write_msi_msg() callbacks cannot operate directly on hardware, e.g. in the case that the interrupt message store is in queue memory: - irq_bus_lock() - irq_bus_unlock() These callbacks are invoked from preemptible task context and are allowed to sleep. In this case the mandatory callbacks above just store the information. The irq_bus_unlock() callback is supposed to make the change effective before returning. - Interrupt affinity setting is handled by the underlying parent interrupt domain and communicated to the IMS domain via irq_write_msi_msg(). IMS domains cannot have a irq_set_affinity() callback. That's a reasonable restriction similar to the PCI/MSI device domain implementations. The domain is automatically destroyed when the PCI device is removed. Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/irqdomain.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 5 +++ 2 files changed, 64 insertions(+) --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -355,6 +355,65 @@ bool pci_msi_domain_supports(struct pci_ return (supported & feature_mask) == feature_mask; } +/** + * pci_create_ims_domain - Create a secondary IMS domain for a PCI device + * @pdev: The PCI device to operate on + * @template: The MSI info template which describes the domain + * @hwsize: The size of the hardware entry table or 0 if the domain + * is purely software managed + * @data: Optional pointer to domain specific data to be stored + * in msi_domain_info::data + * + * Return: True on success, false otherwise + * + * A IMS domain is expected to have the following constraints: + * - The index space is managed by the core code + * + * - There is no requirement for consecutive index ranges + * + * - The interrupt chip must provide the following callbacks: + * - irq_mask() + * - irq_unmask() + * - irq_write_msi_msg() + * + * - The interrupt chip must provide the following optional callbacks + * when the irq_mask(), irq_unmask() and irq_write_msi_msg() callbacks + * cannot operate directly on hardware, e.g. in the case that the + * interrupt message store is in queue memory: + * - irq_bus_lock() + * - irq_bus_unlock() + * + * These callbacks are invoked from preemptible task context and are + * allowed to sleep. In this case the mandatory callbacks above just + * store the information. The irq_bus_unlock() callback is supposed + * to make the change effective before returning. + * + * - Interrupt affinity setting is handled by the underlying parent + * interrupt domain and communicated to the IMS domain via + * irq_write_msi_msg(). + * + * The domain is automatically destroyed when the PCI device is removed. + */ +bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, + unsigned int hwsize, void *data) +{ + struct irq_domain *domain = dev_get_msi_domain(&pdev->dev); + + if (!domain || !irq_domain_is_msi_parent(domain)) + return -ENOTSUPP; + + if (template->info.bus_token != DOMAIN_BUS_PCI_DEVICE_IMS || + !(template->info.flags & MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS) || + !(template->info.flags & MSI_FLAG_FREE_MSI_DESCS) || + !template->chip.irq_mask || !template->chip.irq_unmask || + !template->chip.irq_write_msi_msg || template->chip.irq_set_affinity) + return -EINVAL; + + return msi_create_device_irq_domain(&pdev->dev, MSI_SECONDARY_DOMAIN, template, + hwsize, data, NULL); +} +EXPORT_SYMBOL_GPL(pci_create_ims_domain); + /* * Users of the generic MSI infrastructure expect a device to have a single ID, * so with DMA aliases we have to pick the least-worst compromise. Devices with --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2481,6 +2481,11 @@ static inline bool pci_is_thunderbolt_at void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); #endif +struct msi_domain_template; + +bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, + unsigned int hwsize, void *data); + #include #define pci_printk(level, pdev, fmt, arg...) \ From patchwork Fri Nov 11 13:58:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18842 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp761079wru; Fri, 11 Nov 2022 06:09:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf52Nk22Htw7iuIsvTk6IR4u+Qyas5y6rq1GbefQHzGNEa1QuSpuGuGDSIC40SNTdKyBkEVu X-Received: by 2002:a17:902:f791:b0:184:40f5:b88a with SMTP id q17-20020a170902f79100b0018440f5b88amr2590022pln.172.1668175798130; Fri, 11 Nov 2022 06:09:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175798; cv=none; d=google.com; s=arc-20160816; b=P/AcY78WGmRjttxN2++M7CsX+8PDMnsRtr7IHL9brRxu3AuGj9fjgKWC/tSmfNI8x9 vT0/vv/Z/spqxyDX44+e7MkFlnyKAF8ORGYNnpv7TqkO0ihfHrU98GmmDd9qtGcA5TsV a2OtTCoyUiQvHjwPu6M7GjaqeolSEOX5xTlA8glhNFA/oYN9seulO9wImcqsswfI0mty sU33Y3GLzs2MfqysQl69feAYIL6EfZDaW72Ck6n2o7J3KU/JECqnBNx/XlftR6aGhi2j 7foJ4UCjGpomTmDYdQP4kj5SWS2rL0aczqNRYMSp++V3pamOvhHFdnw50HeyJKhLB545 Kb5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=R8X/63rO52IiLYrJWmoKP44/nsK9YU8Bw0NawruV3mM=; b=zja9Ldt1uYbsgbIbQ2WCTWDnF6KbaePZto1fjyuaL+/7UxT1hmC5T792WCbux4jIRk gqJDIaF2ApaiLQwm1c+s5dqnaqFgJLWG+IP9Dz9geTATvDz3GJ8ePacfw7S1+a+k3KbM SZZMVTy9JMAGdkr8nfsq6yhDTuxHOu6CANPHdR/Do9tq6vcPZIoT3u5OBLqQzWGiaf7F XQabJoJ5ZSB4GOIYEKK07GLtIfBvOsGSmQq1gZ7WOBE/wKTJUobntkHi2idx0fh+iuEc yiVenmIZDTlPY1y5Bny0TQm8rji52vZSup8Fr9+rsQ33MDROeA+4sH22WBxLH0AQ08jB Mobw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Y52rqaQE; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:57 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209105424978927?= X-GMAIL-MSGID: =?utf-8?q?1749209105424978927?= Single vector allocation which allocates the next free index in the IMS space. The free function releases. All allocated vectors are released also via pci_free_vectors() which is also releasing MSI/MSI-X vectors. Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- drivers/pci/msi/api.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 3 +++ 2 files changed, 53 insertions(+) --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -361,6 +361,56 @@ const struct cpumask *pci_irq_get_affini EXPORT_SYMBOL(pci_irq_get_affinity); /** + * pci_ims_alloc_irq - Allocate an interrupt on a PCI/IMS interrupt domain + * @dev: The PCI device to operate on + * @cookie: Pointer to an IMS implementation specific device cookie + * (PASID, queue id, pointer...). The cookie content is stored + * in the MSI descriptor for the interrupt chip callbacks or + * domain specific setup functions + * @affdesc: Optional pointer to an interrupt affinity descriptor + * + * Return: A struct msi_map + * + * On success msi_map::index contains the allocated index (>= 0) and + * msi_map::virq the allocated Linux interrupt number (> 0). + * + * On fail msi_map::index contains the error code and msi_map::virq + * is set to 0. + * + * Note: There is no index for IMS allocations as IMS is an implementation + * specific storage and does not have any direct associations between + * index, which might be a pure software construct, and device + * functionality. This association is established by the driver either + * via the index - if there is a hardware table - or in case of purely + * software managed IMS implementation the association happens via + * the irq_write_msi_msg() callback of the implementation specific + * interrupt chip, which utilizes the provided @cookie to store the MSI + * message in the appropriate place. + */ +struct msi_map pci_ims_alloc_irq(struct pci_dev *dev, union msi_dev_cookie *cookie, + const struct irq_affinity_desc *affdesc) +{ + return msi_domain_alloc_irq_at(&dev->dev, MSI_SECONDARY_DOMAIN, MSI_ANY_INDEX, + affdesc, cookie); +} +EXPORT_SYMBOL_GPL(pci_ims_alloc_irq); + +/** + * pci_ims_free_irq - Allocate an interrupt on a PCI/IMS interrupt domain + * which was allocated via pci_ims_alloc_irq() + * @dev: The PCI device to operate on + * @map: A struct msi_map describing the interrupt to free as + * returned from pci_ims_alloc_irq() + */ +void pci_ims_free_irq(struct pci_dev *dev, struct msi_map map) +{ + if (WARN_ON_ONCE(map.index < 0 || !map.virq)) + return; + msi_domain_free_irqs_range(&dev->dev, MSI_SECONDARY_DOMAIN, map.index, map.index); +} +EXPORT_SYMBOL_GPL(pci_ims_free_irq); + +/** * pci_free_irq_vectors() - Free previously allocated IRQs for a device * @dev: the PCI device to operate on * --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2485,6 +2485,9 @@ struct msi_domain_template; bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, unsigned int hwsize, void *data); +struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_dev_cookie *cookie, + const struct irq_affinity_desc *affdesc); +void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map); #include From patchwork Fri Nov 11 13:58:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18847 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp769485wru; Fri, 11 Nov 2022 06:25:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf53FZU/mgK6jkFDIxFJdlJeGJwO4vaIu6JAwJ8rh4z2qgPuhKPOe8l9ZqDsawhzlxel9Xw9 X-Received: by 2002:aa7:90cf:0:b0:563:4643:db33 with SMTP id k15-20020aa790cf000000b005634643db33mr2943366pfk.22.1668176702583; Fri, 11 Nov 2022 06:25:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668176702; cv=none; d=google.com; s=arc-20160816; b=NqlaqrS7AovY9ikvSlz07vZXbaCpyqOOx4Aasvm/UufDV6WRrroyRGrYfTYfYp2uR+ 4XKAxRN/huH+IoiiYEiB/vA07ynY+C6OwleEVe8lRYUkpYhqVTz1DQvvzi2muQqe3jsy ARvXd1rvjuk5QFN6eKXl0/po9jg0tEqi7TVyD+SOhwu1qjvxBl6BdYqEJkcBLajMGJt+ IOuOgHdB8Yyhu6ikuSQovZ6m9Ug3B1CTH8r3/H9HNDVKcb6wQq64p1Htr+/h40Mytzfe y5wzSdktgCWM2plKuHMaBugfsO0dxi/TbPvqpZ4CGrqbebkxuPHepKW7LbHIlBh34qS3 vPiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=QDMaEx7ktXTUaBjXhcwy3JcriisNhamDQjdxbqkUVcQ=; b=w5+UdBC9WbAF3M182Kr5JQH55qLJ8NqoC2Ojs0gLK+BRKjGDSDBJXK4S8I6dNfRhZH efEEHRRU43DtS6WDf/kVhZIZml3FmsNzYk95zpQT8m2DDFx4cSu9yLQK8zA7/9sY43Tp H9qDO0y2TCGvclpaE2LDmfA4V4SRuj99Ktqm2fRVzssQ8vNi4LmsGGv5tn10qv9RUQ9p gYnCOAjncwlpHsUrS1b06v0xEB/Eu//cMYlogz0TlmQkG04yIiOIlxkPv9LVs3gKYImw N1u9Tst3i4YBv0EdDVf1hmnFUV+u/AXRlwukpvuYI2yxNqUKcOyb27EW3dBuJUuzdtbE BDqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=sricQG6o; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 30/33] x86/apic/msi: Enable PCI/IMS References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:58:59 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749210054089532670?= X-GMAIL-MSGID: =?utf-8?q?1749210054089532670?= Enable IMS in the domain init and allocation mapping code, but do not enable it on the vector domain as discussed in various threads on LKML. The interrupt remap domains can expand this setting like they do with PCI multi MSI. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/msi.c | 5 +++++ 1 file changed, 5 insertions(+) --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -184,6 +184,7 @@ static int x86_msi_prepare(struct irq_do alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSI; return 0; case DOMAIN_BUS_PCI_DEVICE_MSIX: + case DOMAIN_BUS_PCI_DEVICE_IMS: alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX; return 0; default: @@ -230,6 +231,10 @@ static bool x86_init_dev_msi_info(struct case DOMAIN_BUS_PCI_DEVICE_MSI: case DOMAIN_BUS_PCI_DEVICE_MSIX: break; + case DOMAIN_BUS_PCI_DEVICE_IMS: + if (!(pops->supported_flags & MSI_FLAG_PCI_IMS)) + return false; + break; default: WARN_ON_ONCE(1); return false; From patchwork Fri Nov 11 13:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18850 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp775826wru; Fri, 11 Nov 2022 06:36:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf5jjxyCbOElOXE/fAZfhCI0eQDANKhFywq7Dn3eTZ3ShJ7ZRNHSbGe/kBGIBQDo+9pecRdP X-Received: by 2002:a17:90a:ebc9:b0:205:d3f8:5241 with SMTP id cf9-20020a17090aebc900b00205d3f85241mr2091689pjb.188.1668177359836; Fri, 11 Nov 2022 06:35:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668177359; cv=none; d=google.com; s=arc-20160816; b=MVjpPSC4v+YEYwEN08t0oJVzVv07lzQQM6kjWSDGS5T0jDKGlZMKy0XoG/Z03jNMU6 1K6jR9m67YbeCr1Uz5povhLWhKeXN/zoIQt6D6pQ8LX5JLBOvuFj1oou5bR2dhknBdDX xLJMdYAqQJHkLXFl8z3IosF6kM0u+3uRJIuXhaSiVFxBn/uI1d3kwm441HTScRZzxFT+ WwP9njYQwOrtDlMdRG724DRqkoCbAhu0OzdkO83hLd1W0jyffzjM5C/5DBnVOLiW+iJX Bqb6Rco0tQvZ0qzl+1aEtaej9DCnKbbot98B4D6yfkc4yw9JSyOZ2UPTJaD2rMBYG4pd KzeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=SuhbIxDBU+pgQkYaRbDZDx3XYR1ZMR159u+r/p3oNuI=; b=TygpILyUQ4NX1yfT9nQTLPpm7ikA+tYwNIhoMG7t+1DhP+uLe4d+jfJj9R38QUxTo8 ZfLzlHWmtHZWq9K1lB52FBplf3ssiboGprqTCDosfGNOpoj54ZzsIxtiITUGhQt7f3T5 yb7XOxtcP4Ee/jKsdGGVLwJu8mEluF36Y3BO+8BpSa4MBFPYg4ekI/5Yni/xZwBjWNJj sOaMLzDU7p9VOfYKGFo83wh8GXnxILvM2cjVOCDcEVYi/lDJ/Qwu0lB4R6A1UMA6eYpO hwiEoEinixGzvKOzOS2Yawh0H1lEBqk/t5fBAYoUH1qqs7d2sC22G2ZOzfZ75Fgsr029 62Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wVlQvkP6; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=U5xnjfVP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 31/33] iommu/vt-d: Enable PCI/IMS References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:59:00 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749210742857660409?= X-GMAIL-MSGID: =?utf-8?q?1749210742857660409?= PCI/IMS works like PCI/MSI-X in the remapping. Just add the feature flag. Signed-off-by: Thomas Gleixner --- drivers/iommu/intel/irq_remapping.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1429,7 +1429,9 @@ static const struct irq_domain_ops intel }; static const struct msi_parent_ops dmar_msi_parent_ops = { - .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_MSI, + .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | + MSI_FLAG_MULTI_PCI_MSI | + MSI_FLAG_PCI_IMS, .prefix = "IR-", .init_dev_msi_info = msi_parent_init_dev_msi_info, }; From patchwork Fri Nov 11 13:59:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18848 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp770191wru; Fri, 11 Nov 2022 06:26:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf4hpI/SDVwxVE/scxfSbn40h/8EQ13jcioiUY14aXNhjhwT32jiKPpftFRVczvhuksWmYR9 X-Received: by 2002:a17:90a:24d:b0:212:e2e9:4b1f with SMTP id t13-20020a17090a024d00b00212e2e94b1fmr2139577pje.20.1668176786702; Fri, 11 Nov 2022 06:26:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668176786; cv=none; d=google.com; s=arc-20160816; b=Lm56I8IE+4zPaG/ho9mZS3W0xI1VK7PdGWActH6HoYZlg7X2Nm5arIHDU95GVbWYhd g7odE77vAJEPoVKj6Ku7h+jU1Nagq9SOM+C+3mxUCsIa9XPcpMpcQaQ9r8Nefx7xGc86 2T8LBbgKhiIhOV72p4eCOg93vYMVabIqi4B5KHmcwLzQeXAOhNwl0NKl+jT4Edci+BQd nJREOET4jbK9qUdM44dY3uEBaEjN2lcw7mrRKsj5kwqqzXteFrvv2Z96e13H5lMkpCdW mSmeV8iEi4B2viZELvI53r3t8TsGpavgDKbVuPd5iCt1X7mz9EU2iupBcUY+ZTjcZaxs 6rPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=vuCfp3+0SFn3kyyf+6t5pZzLC+oocOyU3+0CroYzbSc=; b=Y1+vKwP4Ht8HTex65tNBhrjJCAsw1udm9MfEl4chiPUxYjCRll48/YxeuZzZIhUcB7 HPhYq3r7kFBx0F3UDoDuu8OYGdSjEQdVps13HK0QONjqbAETxvff2TKL1TfCrfkU7s/S 0tyJxpkAwxPjqocqP2RxzDI00aDTwrxKG13aWK/ZqesEIKmG5Qwv3WuY7LS1okOpdHnI MdtHKS7tsJtPZQeo3EjDBBphhJLuXD2dM91pl6+iuL50oD6T2YZ0lgZO4A0OukaigDja oW5KrBqv14X1g2ZWxix5RPLxyy7TMGTQIc0DDZNaYBCWiuhVFY13MS2zeVT52CQx3zHN T5Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EYt8PyTc; dkim=neutral (no key) header.i=@linutronix.de header.b=B5oBtBjh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 32/33] iommu/amd: Enable PCI/IMS References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:59:02 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749210142156498111?= X-GMAIL-MSGID: =?utf-8?q?1749210142156498111?= PCI/IMS works like PCI/MSI-X in the remapping. Just add the feature flag. Signed-off-by: Thomas Gleixner --- drivers/iommu/amd/iommu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3649,7 +3649,9 @@ static struct irq_chip amd_ir_chip = { }; static const struct msi_parent_ops amdvi_msi_parent_ops = { - .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_MSI, + .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | + MSI_FLAG_MULTI_PCI_MSI | + MSI_FLAG_PCI_IMS, .prefix = "IR-", .init_dev_msi_info = msi_parent_init_dev_msi_info, }; From patchwork Fri Nov 11 13:59:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 18844 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp761176wru; Fri, 11 Nov 2022 06:10:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf60ShdvvTgU3vmuNjZ33+e+qfyUL8jnC6V6H0DjbodP4EfLYL6oEJuH5WiOr9y1wT3tTzAO X-Received: by 2002:a63:2264:0:b0:438:a46b:63f2 with SMTP id t36-20020a632264000000b00438a46b63f2mr1806866pgm.572.1668175807328; Fri, 11 Nov 2022 06:10:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668175807; cv=none; d=google.com; s=arc-20160816; b=Xm0fq9cI/CYor85r8hv5BWdILyyw7nOUMIUCmOqqIojKTRvQ7EY0WtnzPpnavAUWKY 1z7C1kg5kDl94hyefSnXoJTpU2d3BUNVKLKexrQx/MF84mt92BKdUY4mzujNeBHa+jKi MI5UIf77QkQhFosrOS2qIjhrSJNDpMND1vhwuXLfo6gz/FFgvzg1GXrzfKUIsHdt/PKz UwMjICcYUj1MejepjyRK43XDVLb7D1/dDl9cqewQn2A67lsVrdAezuq2ERNR/zIVbXd0 Y8x5uFrLmOZ3AA/jnMTvJgSPo5UPQWk5SXw905F68ZYsIsKQozaaYl9HQ9LbnHRLx05z 53vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Hc23zLtu5ea7f06ZX0yBhdnBmnsVxTw6REgVU2riWiY=; b=pTD/nFZz/xSemjw06xcRcq1xO1WOYo4mC490lGJ4TnNu4lTNydKnUl0U0tTYL8ov/i QMVsFdBv7d1onhXW4HUyoA8DDMx1wpcDmsNuqbxfXVSnUglUv2r3z6B0RwryQa6sLY01 T7PNgLewFzqHvfeS3fQXfQDgIK+E50BMAWBEGXaI/7G/uGw1woU7XwJg+tqYhoNlNiSe yRwdNPeF6sGdr3Vitfybkjadsa0izGBBRq2jT7BW7aeTtg0fKVSW0qpRSP4XMae3Fx0e xCLqY6gbm1NXgkZ9BwLiCgAs2vXB8A6YcsNUkcSthuj8QeQ1ELXPUWvzdo8ysx1oLcCf u96g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=42yudJdW; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=+1YN7GL1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Darwish" , Reinette Chatre Subject: [patch 33/33] irqchip: Add IDXD Interrupt Message Store driver References: <20221111133158.196269823@linutronix.de> MIME-Version: 1.0 Date: Fri, 11 Nov 2022 14:59:03 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749209115326317748?= X-GMAIL-MSGID: =?utf-8?q?1749209115326317748?= Provide a driver for the Intel IDXD IMS implementation. The implementation uses a large message store array in device memory. The IMS domain implementation is minimal and just provides the required irq_chip callbacks and one domain callback which prepares the MSI descriptor which is allocated by the core for easy usage in the irq_chip callbacks. The necessary iobase is stored in the irqdomain and the PASID which is required for operation is handed in via msi_dev_cookie in the allocation function. Not much to see here. A few lines of code and a filled in template is all what's needed. Signed-off-by: Thomas Gleixner --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 1 drivers/irqchip/irq-pci-intel-idxd.c | 143 +++++++++++++++++++++++++++++ include/linux/irqchip/irq-pci-intel-idxd.h | 22 ++++ 4 files changed, 173 insertions(+) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -695,4 +695,11 @@ config SUNPLUS_SP7021_INTC chained controller, routing all interrupt source in P-Chip to the primary controller on C-Chip. +config PCI_INTEL_IDXD_IMS + tristate "Intel IDXD Interrupt Message Store controller" + depends on PCI_MSI + help + Support for Intel IDXD IMS Interrupt Message Store controller + with IMS slot storage in a slot array in device memory + endmenu --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -121,3 +121,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt32 obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_PCI_INTEL_IDXD_IMS) += irq-pci-intel-idxd.o --- /dev/null +++ b/drivers/irqchip/irq-pci-intel-idxd.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interrupt chip and domain for Intel IDXD with hardware array based + * interrupt message store (IMS). + */ +#include +#include +#include +#include +#include + +#include + +MODULE_LICENSE("GPL"); + +/** + * struct ims_slot - The hardware layout of a slot in the memory table + * @address_lo: Lower 32bit address + * @address_hi: Upper 32bit address + * @data: Message data + * @ctrl: Control word + */ +struct ims_slot { + u32 address_lo; + u32 address_hi; + u32 data; + u32 ctrl; +} __packed; + +/* Bit to mask the interrupt in the control word */ +#define CTRL_VECTOR_MASKBIT BIT(0) +/* Bit to enable PASID in the control word */ +#define CTRL_PASID_ENABLE BIT(3) +/* Position of PASID.LSB in the control word */ +#define CTRL_PASID_SHIFT 12 + +static inline void iowrite32_and_flush(u32 value, void __iomem *addr) +{ + iowrite32(value, addr); + ioread32(addr); +} + +static void idxd_mask(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + struct ims_slot __iomem *slot = desc->data.iobase; + u32 cval = desc->data.cookie.value; + + iowrite32_and_flush(cval | CTRL_VECTOR_MASKBIT, &slot->ctrl); +} + +static void idxd_unmask(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + struct ims_slot __iomem *slot = desc->data.iobase; + u32 cval = desc->data.cookie.value; + + iowrite32_and_flush(cval, &slot->ctrl); +} + +static void idxd_write_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + struct ims_slot __iomem *slot = desc->data.iobase; + + iowrite32(msg->address_lo, &slot->address_lo); + iowrite32(msg->address_hi, &slot->address_hi); + iowrite32_and_flush(msg->data, &slot->data); +} + +static void idxd_shutdown(struct irq_data *data) +{ + struct msi_desc *desc = irq_data_get_msi_desc(data); + struct ims_slot __iomem *slot = desc->data.iobase; + + iowrite32(0, &slot->address_lo); + iowrite32(0, &slot->address_hi); + iowrite32(0, &slot->data); + iowrite32_and_flush(CTRL_VECTOR_MASKBIT, &slot->ctrl); +} + +static void idxd_prepare_desc(struct irq_domain *domain, msi_alloc_info_t *arg, + struct msi_desc *desc) +{ + struct msi_domain_info *info = domain->host_data; + struct ims_slot __iomem *slot; + + /* Set up the slot address for the irq_chip callbacks */ + slot = (__force struct ims_slot __iomem *) info->data; + slot += desc->msi_index; + desc->data.iobase = slot; + + /* Mask the interrupt for paranoia sake */ + iowrite32_and_flush(CTRL_VECTOR_MASKBIT, &slot->ctrl); + + /* + * The caller provided PASID. Shift it to the proper position + * and set the PASID enable bit. + */ + desc->data.cookie.value <<= CTRL_PASID_SHIFT; + desc->data.cookie.value |= CTRL_PASID_ENABLE; + + arg->hwirq = desc->msi_index; +} + +static const struct msi_domain_template idxd_ims_template = { + .chip = { + .name = "PCI-IDXD", + .irq_mask = idxd_mask, + .irq_unmask = idxd_unmask, + .irq_write_msi_msg = idxd_write_msi_msg, + .irq_shutdown = idxd_shutdown, + .flags = IRQCHIP_ONESHOT_SAFE, + }, + + .ops = { + .prepare_desc = idxd_prepare_desc, + }, + + .info = { + .flags = MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | + MSI_FLAG_FREE_MSI_DESCS | + MSI_FLAG_PCI_IMS, + .bus_token = DOMAIN_BUS_PCI_DEVICE_IMS, + }, +}; + +/** + * pci_intel_idxd_create_ims_domain - Create a IDXD IMS domain + * @pdev: IDXD PCI device to operate on + * @slots: Pointer to the mapped slot memory arrray + * @nr_slots: The number of slots in the array + * + * Returns: True on success, false otherwise + * + * The domain is automatically destroyed when the @pdev is destroyed + */ +bool pci_intel_idxd_create_ims_domain(struct pci_dev *pdev, void __iomem *slots, + unsigned int nr_slots) +{ + return pci_create_ims_domain(pdev, &idxd_ims_template, nr_slots, (__force void *)slots); +} +EXPORT_SYMBOL_GPL(pci_intel_idxd_create_ims_domain); --- /dev/null +++ b/include/linux/irqchip/irq-pci-intel-idxd.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* (C) Copyright 2022 Thomas Gleixner */ + +#ifndef _LINUX_IRQCHIP_IRQ_PCI_INTEL_IDXD_H +#define _LINUX_IRQCHIP_IRQ_PCI_INTEL_IDXD_H + +#include +#include +#include + +/* + * Conveniance macro to wrap the PASID for interrupt allocation + * via pci_ims_alloc_irq(pdev, INTEL_IDXD_DEV_COOKIE(pasid)) + */ +#define INTEL_IDXD_DEV_COOKIE(pasid) (union msi_dev_cookie) { .value = (pasid), } + +struct pci_dev; + +bool pci_intel_idxd_create_ims_domain(struct pci_dev *pdev, void __iomem *slots, + unsigned int nr_slots); + +#endif