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Fri, 15 Dec 2023 07:40:31 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:26 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , , Russell King Subject: [PATCH v8 01/14] net: phy: introduce core support for phy-mode = "10g-qxgmii" Date: Fri, 15 Dec 2023 15:39:51 +0800 Message-ID: <20231215074005.26976-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: eC44DPYKKp4gnutReU_KR3V7XSv0_AGw X-Proofpoint-GUID: eC44DPYKKp4gnutReU_KR3V7XSv0_AGw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1011 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333090151613780 X-GMAIL-MSGID: 1785333090151613780 From: Vladimir Oltean 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Reviewed-by: Andrew Lunn Reviewed-by: Russell King (Oracle) --- Documentation/networking/phy.rst | 6 ++++++ drivers/net/phy/phy-core.c | 1 + drivers/net/phy/phylink.c | 11 +++++++++-- include/linux/phy.h | 4 ++++ include/linux/phylink.h | 2 ++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 1283240d7620..f64641417c54 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -327,6 +327,12 @@ Some of the interface modes are described below: This is the Penta SGMII mode, it is similar to QSGMII but it combines 5 SGMII lines into a single link compared to 4 on QSGMII. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..1cd58723d6d0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; case PHY_INTERFACE_MODE_PSGMII: return 5; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 48d3bd3e9fc7..938faac14930 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -941,6 +946,7 @@ static int phylink_parse_mode(struct phylink *pl, phylink_set(pl->supported, 25000baseSR_Full); fallthrough; case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: phylink_set(pl->supported, 10baseT_Half); @@ -1837,7 +1843,8 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy, if (phy->is_c45 && state->rate_matching == RATE_MATCH_NONE && state->interface != PHY_INTERFACE_MODE_RXAUI && state->interface != PHY_INTERFACE_MODE_XAUI && - state->interface != PHY_INTERFACE_MODE_USXGMII) + state->interface != PHY_INTERFACE_MODE_USXGMII && + state->interface != PHY_INTERFACE_MODE_10G_QXGMII) state->interface = PHY_INTERFACE_MODE_NA; return phylink_validate(pl, supported, state); diff --git a/include/linux/phy.h b/include/linux/phy.h index dbb5e13e3e1b..87859a32f6ef 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -165,6 +166,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; default: return "unknown"; } diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..92bd2726cc8a 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -128,6 +128,7 @@ static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: /* These protocols are designed for use with a PHY which * communicates its negotiation result back to the MAC via * inband communication. Note: there exist PHYs that run @@ -680,6 +681,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface) case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 1600000; case PHY_INTERFACE_MODE_1000BASEX: From patchwork Fri Dec 15 07:39:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179064 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9104609dys; Thu, 14 Dec 2023 23:43:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXsMi/oUKm6v/heo1dpXF/Tyw651CQLgGmyVtkktWz4v2inLWxU8kLJZaA9dxLkSvkWJeg X-Received: by 2002:a05:620a:10a9:b0:77f:3dbe:8a80 with SMTP id h9-20020a05620a10a900b0077f3dbe8a80mr11711500qkk.83.1702626198993; Thu, 14 Dec 2023 23:43:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626198; cv=none; d=google.com; s=arc-20160816; b=ljOJh1DPGQF0alXuF5mf7kcf3Xzwgw/X14qRKYWQpE5ELzzz4mQxBogcifcAL37Bew h7hkIpUVuqrxMOsanfNX5abrvKfR5hDxhhAjlcbA0gOkName34wkjzn+o38mrhaTnUix tjrgo+s7AR5GlBvOWPwPaYswdssW9L0ijne9Kz4QIrSammMzAVs9G3PClUJYsUidqn44 c0iN69baAu3QoieXz2b7ZcsKcqgVvHHo4k39wpzy8EJsNg25w59bO7lLdKjErvPT8PtR v4s1xz60mD6pGpgrxYBYw/eeRY+DOeXcH4WpDBskEVCsaJKkg3KGhfDK1A+JQ6oscqRq dxYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=8TbqspJYbdL/IuX/TEac0i9VshMmSvoHEJ8s53kuZdY=; fh=HxbeNJFBBSGCgfRKKU9atdiMjw5Zc0lm+FcRGUvQ0W4=; b=GXkLbNEwJa5Dk30Y8QHnzeGrNJWGkM2DfdvsnkTZqd6Qma6DLO3/Xop79NFZifPXqC NEVsVenEtg3xM+Z1Ne5fmgVu2wojY/zfo0rckoSJFyzpCPvuxrN7qLZKLzch4jJ5IDKR xfKRpje0NVR2D6K6jv+0qSekT0BWGxyONLK1beezcX34eyD318bKxYeAb/0a0HrOiDd3 qoETUnH+/xtYstCpJco/g/SNQX89r8HduwzQvw4vX+XyOKyHjeVxyWDb6eOpOMk68dFS 8o/mqYrkcqXigoJVXgiPOZ3Yi2mGx+lG4LPvYKxX82kK6/8FbFIvB4N1HrMidVb+P0GO ep3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="UDXA9K0/"; spf=pass (google.com: domain of linux-kernel+bounces-544-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-544-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:40:35 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:31 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , , Conor Dooley Subject: [PATCH v8 02/14] dt-bindings: net: ethernet-controller: add 10g-qxgmii mode Date: Fri, 15 Dec 2023 15:39:52 +0800 Message-ID: <20231215074005.26976-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: R1Ht2yVbj2hPwiEkHlZPJ_baP76zoO6l X-Proofpoint-GUID: R1Ht2yVbj2hPwiEkHlZPJ_baP76zoO6l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=966 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785332968833394859 X-GMAIL-MSGID: 1785332968833394859 From: Vladimir Oltean Add the new interface mode 10g-qxgmii, which is similar to usxgmii but extend to 4 channels to support maximum of 4 ports with the link speed 10M/100M/1G/2.5G. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Acked-by: Conor Dooley Reviewed-by: Andrew Lunn --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index d14d123ad7a0..0ef6103c5fd8 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -104,6 +104,7 @@ properties: - usxgmii - 10gbase-r - 25gbase-r + - 10g-qxgmii phy-mode: $ref: "#/properties/phy-connection-type" From patchwork Fri Dec 15 07:39:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179065 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9104694dys; Thu, 14 Dec 2023 23:43:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IFMwAKKoXvW69DdYgFAClDPQAlL/jHhC7UGTlGZaugoWOiZ3p8MLUi0p2p+eqBMbgAlOpJ7 X-Received: by 2002:a0c:e6a7:0:b0:67e:f246:6a56 with SMTP id j7-20020a0ce6a7000000b0067ef2466a56mr4714811qvn.17.1702626209055; Thu, 14 Dec 2023 23:43:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626209; cv=none; d=google.com; s=arc-20160816; b=pEZDA7w6V7L1G3wQCz3PGt4JzXlwxbKU3odfqjp6mhq1o4wT4qfsmmfrJIdMnBoFh8 mwP2pTkRdKxyEDEc3sB9e4/KbJVgIO44AuvXdezSnhM12znz9QXWAlUrd69F/gYP+b9H m2hvUszxT7Nx5opSMYWWAiQ5X2swoAnZz3s6FMYsbf1NnjQHgU/z9oOb3AL9SVsUEAsQ shprh+SilL1cZqDQo7gzo/SWv3S/YyaKQW0dbz2NZPv+iz+giaxFyIhjERnwKKFLHb2F f8ZoTspYwC3jQAYUGSosnkjGkye2L4TWT4r+3oQa4HEJAZBx8JkmnC5vYbh6RnFLtmdz Atkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7EcrWuVPNPlFIOb9ibXQQvSvBKt1s8SH1X++e787ah0=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=V6kgSa82IA9/6892iMFnOIaabfrbFB4fcr+LbK1tQ9c27yefeAPJ9nH70I8jOFvVav 9/dq5XXpoCZbtsnDC2iqeiwpjHLSeljg+q6IbUtPC9SwJavw2ftY4exXwnlBwYDBltOM rIioy+OJk5TD8tlM56UuuvT9BUzIxhAtO5ykTt5nN7q2iqI1eNdTIZlyzgjhS7pXKV+S gX5k+wEnzLSBemeTGbDLDZuHQ9hQbBOJbT8L1J3CoRYeAsyDjPo2WuBq15XM8q5oPBuH 43Fl65GrIUFw3sX1N/f3IiEP9eYR1vAJicsqqFSD96nXfPVCkeD9gaL+s+0DVbZu2tPo jCew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WjChY9h4; spf=pass (google.com: domain of linux-kernel+bounces-545-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-545-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:40:40 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:35 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 03/14] net: phy: at803x: add QCA8084 ethernet phy support Date: Fri, 15 Dec 2023 15:39:53 +0800 Message-ID: <20231215074005.26976-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ocxn7EI-dBn93S0TsSc28NXxt-HcBvy_ X-Proofpoint-GUID: Ocxn7EI-dBn93S0TsSc28NXxt-HcBvy_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxscore=0 bulkscore=0 mlxlogscore=965 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785332979613339720 X-GMAIL-MSGID: 1785332979613339720 Add qca8084 PHY support, which is four-port PHY with maximum link capability 2.5G, the features of each port is almost same as QCA8081 and slave seed config is not needed. Three kind of interface modes supported by qca8084. PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. The PCS(serdes) and clock are also needed to be configured to bringup qca8084 PHY, which will be added in the pcs driver. The additional CDT configurations used for qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b9d3a26cf6dc..eacde4fa5d6c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -176,6 +176,7 @@ #define AT8030_PHY_ID_MASK 0xffffffef #define QCA8081_PHY_ID 0x004dd101 +#define QCA8084_PHY_ID 0x004dd180 #define QCA8327_A_PHY_ID 0x004dd033 #define QCA8327_B_PHY_ID 0x004dd034 @@ -1835,6 +1836,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev) static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) { + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return false; + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); } @@ -1899,6 +1903,23 @@ static int qca808x_read_status(struct phy_device *phydev) return ret; if (phydev->link) { + /* There are two PCSs available for QCA8084, which support the + * following interface modes. + * + * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all + * available 4 ports, which is for all link speeds. + * + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the + * fourth port, which is only for the link speed 2500M same + * as QCA8081. + * + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth + * port, which is for the link speed 10M, 100M and 1000M same + * as QCA8081. + */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + return 0; + if (phydev->speed == SPEED_2500) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; else @@ -2033,6 +2054,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { + /* Adjust the positive and negative pulse thereshold of CDT */ + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060); + + /* Disable the near echo bypass */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0); + } + return 0; } @@ -2304,6 +2333,25 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, +}, { + /* Qualcomm QCA8084 */ + PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), + .name = "Qualcomm QCA8084", + .flags = PHY_POLL_CABLE_TEST, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = qca808x_get_features, + .config_aneg = at803x_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, }, }; module_phy_driver(at803x_driver); @@ -2319,6 +2367,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, { } }; From patchwork Fri Dec 15 07:39:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179066 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9104807dys; Thu, 14 Dec 2023 23:43:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IGQnLWkDvpYEpapYCQO5bJsZvb725AGJjrDzKknOQ4yBldpm+lGE1Kiz1OrxRHRCYdvfrwA X-Received: by 2002:a05:620a:3:b0:77f:3535:87ca with SMTP id j3-20020a05620a000300b0077f353587camr13096595qki.106.1702626233013; Thu, 14 Dec 2023 23:43:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626233; cv=none; d=google.com; s=arc-20160816; b=HdczlLVogQxBEnKIOPu9Oew7P2pPdmuMLaupUqhvccjnYhMH9Eeput3bqCL1aQFPrC OK0dU4qjw1BxUxbtctbN7niCp0liOsptWkmN0dKArdUH4hq9Jeg03MjwMTmnm0pCxX43 bTbER1heL9XaZjdbZ92PgEFphCzsAspqbtsBEXVcxO/1gCXY0fUWKutJ2wQ/VuZnaaos /UkolF8nNxNZHXbv1bShMBt/Jzkj8OyOuLHvKV5SG7QAzFrH7eo20J3ickyovXQZ/LDG BRUBTOdLmEL7xCaKGBjUpE+BnBG5YGZyTeDyyvcNHLT0RV4ERJEj3O6SI6sRYLBnc1No +n/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=COfUyW12yKbUJKTrvajK+hp9Yxx6QQ5yu09VqYHfOPo=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=nYSTffSM6bl91pwTugwpEAk4Ge2R7IFe6nWUc4VIhzLM5Qd2YpyfRt4axquGNqEt2X McvWfeTI5ZCimwZJOuA5HJoUyRXY9HG/yW+4/wt2mJTMQZ2yFS0HwoLZenCMBlnxgWpI Xg/AkO1mtoZE4qlEsIymDgEgwRqGqgwYbk99kdmxp1d2x4SwHvn3LNsu/Ozn8TGtlKEP vV7vrfO6MO7GGH96SMPPu0yMyBe5+txftpYT4Pyc4vDUUMW/pCwUPLHVqx/p7PZKSzZP USOkgc94SNJhLomp3spOsph83OlC1zrtOnutbHiqbSkXPnPYp964A27F5fYxRmFLyeXt LHrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=AvK0MXAZ; spf=pass (google.com: domain of linux-kernel+bounces-546-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-546-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:40:44 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:40 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 04/14] net: phy: at803x: add the function phydev_id_is_qca808x Date: Fri, 15 Dec 2023 15:39:54 +0800 Message-ID: <20231215074005.26976-5-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: vkpgm86QGS0hbMM7UgUen8kf5lIeZtyh X-Proofpoint-GUID: vkpgm86QGS0hbMM7UgUen8kf5lIeZtyh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333005174384113 X-GMAIL-MSGID: 1785333005174384113 The function phydev_id_is_qca808x is applicable to the PHY qca8081 and qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index eacde4fa5d6c..1030896dd546 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -922,6 +922,12 @@ static void at803x_link_change_notify(struct phy_device *phydev) } } +static bool phydev_id_is_qca808x(struct phy_device *phydev) +{ + return phydev_id_compare(phydev, QCA8081_PHY_ID) || + phydev_id_compare(phydev, QCA8084_PHY_ID); +} + static int at803x_read_specific_status(struct phy_device *phydev) { int ss; @@ -941,8 +947,8 @@ static int at803x_read_specific_status(struct phy_device *phydev) if (sfc < 0) return sfc; - /* qca8081 takes the different bits for speed value from at803x */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bits for speed value from at803x */ + if (phydev_id_is_qca808x(phydev)) speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); else speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); @@ -1073,7 +1079,7 @@ static int at803x_config_aneg(struct phy_device *phydev) */ ret = 0; - if (phydev->drv->phy_id == QCA8081_PHY_ID) { + if (phydev_id_is_qca808x(phydev)) { int phy_ctrl = 0; /* The reg MII_BMCR also needs to be configured for force mode, the From patchwork Fri Dec 15 07:39:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179067 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9105119dys; Thu, 14 Dec 2023 23:44:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IEK9NCXZ1uk3+oVFlDa2vK03DAZb+w0edaM68ZDv2MHcPvL4DVS3+2Pdmk0TlkOVYbp4Ajg X-Received: by 2002:a17:903:44a:b0:1d3:5f7f:c882 with SMTP id iw10-20020a170903044a00b001d35f7fc882mr2186916plb.30.1702626290779; Thu, 14 Dec 2023 23:44:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626290; cv=none; d=google.com; s=arc-20160816; b=ZhohZYkp2tPuD6xRpSWWtzahLApAojG6pjLBput4cArWJEgwzR5/9uT2PKPqqTfEg7 32u7HZZ3HlD9IV495605yEqU7UMPYAlkX78Iv/CBE4XB1o60PmlOpejd8yWRXh2MZlqI RWPh58EGO/VJWTmEh6sOyXfVY9Q7G9eHLGhGQX/Xv9frWutPG0oR6nBWWxsWIQW4apvu 0vorhBjJ4JmP+RfZKZWQh/+dEu2/V7SaQfrczPjSZ9/K4OY9oLUhEkAysn36+pH9kXCq yLZkj3ttbCnC1POEyqzBKDMnBWpON0njAP3g5cNqodBKvucqvyqBhIVGXBblo4h0mBjr smjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oMKb/bC0IiOLVdW8TS1QSiGeJrouun61X6rrwSQSgZ4=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=GHWfBUR5K7O/+8xBtVkAgxHKdOLlDsw+F9aif803qFabNzY1fd77yA9/o16s7EuUbo /bhZ3GddB6fmgt2YFONm8hRUkm9EUJZz+opJ+BPRn4fcpJ85GpyakGKqWKLyRkUzIpzS CAPTifTsSc7YiFaJ4GCdiqR7IfRLsttvo2Hwp2F7dVUMleUKkQ9iglCGeSYKhqVJeVjJ 4CZOnw3YTXZQzj/Z3lDNxAIbdY/EVs9ve0Whq7jcEQwGe2OZKlup0WsDj/7doMfFuspJ okdxGCu4HojNhfqneMeFWSj6SoHgEpZEm/evYKoO2c2B4nTA08DVzGbOwP7rAkXyLDZj fERw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ooL6fgF0; spf=pass (google.com: domain of linux-kernel+bounces-547-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-547-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 1030896dd546..252fae4329cc 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -280,6 +280,15 @@ #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 #define QCA8081_PHY_FIFO_RSTN BIT(11) +/* QCA8084 ADC clock edge */ +#define QCA8084_ADC_CLK_SEL 0x8b80 +#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) +#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf +#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 + +#define QCA8084_MSE_THRESHOLD 0x800a +#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2163,6 +2172,26 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca8084_config_init(struct phy_device *phydev) +{ + int ret; + + /* Invert ADC clock edge */ + ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, + QCA8084_ADC_CLK_SEL_ACLK, + FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, + QCA8084_ADC_CLK_SEL_ACLK_FALL)); + if (ret < 0) + return ret; + + /* Adjust MSE threshold value to avoid link issue with + * some link partner. + */ + return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, + QCA8084_MSE_THRESHOLD, + QCA8084_MSE_THRESHOLD_2P5G_VAL); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2358,6 +2387,7 @@ static struct phy_driver at803x_driver[] = { .soft_reset = qca808x_soft_reset, .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, }, }; module_phy_driver(at803x_driver); From patchwork Fri Dec 15 07:39:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179068 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9105252dys; Thu, 14 Dec 2023 23:45:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IGqyHgieN3AQSxxcj09cmRS/YI5Ks1YAkcXY3tDFyUZ076tKOxMjyPzoBdXrnVs9AlQ99em X-Received: by 2002:a05:620a:5599:b0:77e:fe60:ed30 with SMTP id vq25-20020a05620a559900b0077efe60ed30mr12652042qkn.125.1702626313505; Thu, 14 Dec 2023 23:45:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626313; cv=none; d=google.com; s=arc-20160816; b=hWmZWkf1Y88togXxCe7ptkLy51RdC5EDMolepHuWIm/fvXkMe4BiSE7qA9S7DUeo16 kqB5z6mohfPz91GaPacnL13/RFcpm9mn6iJsI+G6ShGm+0aEUpjCY/jWGunrcK1e9oVR frtVtmDr2IJGxC783OJtn6LnH/Jbnqwf6z5GZIHo8Ea9kJ+FUibwtdj4KgUQho6iulNk w25sIhZiNf3aDeu7NhnNCobV4VanvTU6cRn+4LPLMMsMNZNdCwGPvm66SODWNCh1Lmar Iu/zf4xRwM94yblI8kubQ+yJOKqKhHEAmEdfZCurFS3Wl3iR3MGlNrJzktuHl/mCTP9D LNig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7+uJJsu7r1bUFsYmXKjWyci5NkWtJ9QfDE/bEKYNGi4=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=FuH94LyyZhsn82NfAFIfsHaKioYQaG49I5CqtWnnoJjgIG/aNfi3pQaS3JS+5HFHca K4mLqKRNNUNa6L9vc+DVxXk8VOhA8yLHVwd3MeT5Y7kX+uFvlOs5IMWdO4fmDlkECkIV HPaAHT6j7brv8mmAhsr6bi2Ubp+TDWqMws7d1qjnHzo69hy8cw4IyupZrAW20VowaPwz tKC+1ybfTWGQmhe28n+aTkegdhDgXKy9WA1XCOvD/v6YA5aq7McFc2laKIWPZDqboCH5 5aK5153jXZSMSS1bkpiWe9VJ8wvOtpu7nAMUr1OgJ8i0fAu2k1HO5PuuWx59Ly1cj3oa Hkyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kOfX8EMg; spf=pass (google.com: domain of linux-kernel+bounces-549-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-549-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:40:53 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:48 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 06/14] net: phy: at803x: add qca8084_link_change_notify Date: Fri, 15 Dec 2023 15:39:56 +0800 Message-ID: <20231215074005.26976-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gqoNSi-LJIoA_ez-vGOEIq0HPfvfEzZ9 X-Proofpoint-GUID: gqoNSi-LJIoA_ez-vGOEIq0HPfvfEzZ9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333089060012698 X-GMAIL-MSGID: 1785333089060012698 When the link is changed, qca8084 needs to do the fifo reset and adjust the IPG level for the qusgmii link speed 1000M. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 252fae4329cc..bb382089ab77 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -289,6 +289,13 @@ #define QCA8084_MSE_THRESHOLD 0x800a #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 +#define QCA8084_FIFO_CONTROL 0x19 +#define QCA8084_FIFO_MAC_2_PHY BIT(1) +#define QCA8084_FIFO_PHY_2_MAC BIT(0) + +#define QCA8084_MMD7_IPG_OP 0x901d +#define QCA8084_IPG_10_TO_11_EN BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2192,6 +2199,39 @@ static int qca8084_config_init(struct phy_device *phydev) QCA8084_MSE_THRESHOLD_2P5G_VAL); } +static void qca8084_link_change_notify(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, + 0); + if (ret) + return; + + /* If the PHY works on PHY_INTERFACE_MODE_10G_QXGMII mode, the fifo + * needs to be kept as reset state in link down status. + */ + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || + phydev->link) { + msleep(50); + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC); + if (ret) + return; + } + + /* Enable IPG 10 to 11 tuning on link speed 1000M of QUSGMII mode. */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP, + QCA8084_IPG_10_TO_11_EN, + phydev->speed == SPEED_1000 ? + QCA8084_IPG_10_TO_11_EN : 0); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2388,6 +2428,7 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .config_init = qca8084_config_init, + .link_change_notify = qca8084_link_change_notify, }, }; module_phy_driver(at803x_driver); From patchwork Fri Dec 15 07:39:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179076 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9106793dys; Thu, 14 Dec 2023 23:49:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IFrjR7h6AM5va88aPUIdDl8NahPI4u7Oza250AhgTipkhSPo6yfTo+rY2E7P34P1GXdRYR6 X-Received: by 2002:a17:902:e885:b0:1d0:bb65:685c with SMTP id w5-20020a170902e88500b001d0bb65685cmr6736129plg.31.1702626579700; Thu, 14 Dec 2023 23:49:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626579; cv=none; d=google.com; s=arc-20160816; b=MynoTb8XybiyU/iCubGEu/g2hi6uA1R1K1FBJjLFsRkQnhl1DLsecj3baMedzFgkQT NmRfGW9sSpXYsUzJVPKslYz8l/FQHkP05kgyRGRtpKB7e99hrT2p8PrwaAaO+JsFVoWN w6E6gHz4z/FqRvWmf9aZawGfLXSxZrou3CHQ2JckWunCWmWxRm/nGKPPzZ7DVpUyzPJT TFKmgbz+oiWx4l27vAIQZcrrcFLM4d6/DIUZFBaNp9L9ThKu55H4v/43BptrKPXzBbyb Is9bvmHOqWjvdhP8Sjlf6dG8LtZ+t72L4XN2+cv5HDtfKsApqbeFtS1uPvghb//+5lYx +ukQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=dJ5kQvuoEbVrG4WmjFAM8eSccltqgqQY4QEeEFSI+gk=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=ZwTDR5SWJg8BHalECkWM57OZ9do22bCsKxVeLvJ5FRNhM9JzQRLo+p1I4nJfO+5x9P tIY/ifp8iOqpqWTfd2ppPdWLDN7Q6pM307QmgYRv7D++KWWKAOin8PklLny1ItKV+37n jmBfSGphsyR0Tum1m9l5lNDjh9DlRupt2sb5/a2WSrDZPog9QanIg8KSat4B7UidavX9 G7kBvsc30VNX4niiJM7TDNNl20gyY4vMVblHcgLqbqbyYcw5zwV66oRBk+bkePB2dWW2 11BXl6mpodpcImWH8+hjsgG2eyK0IW2S0HfAv/h1Jak5dfVN+/u5/8HcuVtGB59WHbSR wHOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=HlI6XGqb; spf=pass (google.com: domain of linux-kernel+bounces-548-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-548-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:40:57 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:53 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 07/14] net: phy: at803x: add the possible_interfaces Date: Fri, 15 Dec 2023 15:39:57 +0800 Message-ID: <20231215074005.26976-8-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9Z0uW0s37wvLdjGJ4fJsZZfAowzMiEOz X-Proofpoint-ORIG-GUID: 9Z0uW0s37wvLdjGJ4fJsZZfAowzMiEOz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=954 mlxscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333368611115367 X-GMAIL-MSGID: 1785333368611115367 When qca808x works on the interface mode sgmii or 2500base-x, the interface mode can be switched according to the PHY link speed. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index bb382089ab77..cd1bdb61d122 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -2179,10 +2179,22 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static void qca808x_fill_possible_interfaces(struct phy_device *phydev) +{ + unsigned long *possible = phydev->possible_interfaces; + + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII) { + __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible); + __set_bit(PHY_INTERFACE_MODE_SGMII, possible); + } +} + static int qca8084_config_init(struct phy_device *phydev) { int ret; + qca808x_fill_possible_interfaces(phydev); + /* Invert ADC clock edge */ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, QCA8084_ADC_CLK_SEL_ACLK, From patchwork Fri Dec 15 07:39:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179079 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9107288dys; Thu, 14 Dec 2023 23:51:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFmqz2utGG6eSlCQS+g6awEdI5ap1MGlYAI+mfuM0OFje96bn5e444PzIrgv7000sKWK7t5 X-Received: by 2002:a05:6358:2612:b0:170:5522:597b with SMTP id l18-20020a056358261200b001705522597bmr17540964rwc.56.1702626667644; Thu, 14 Dec 2023 23:51:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626667; cv=none; d=google.com; s=arc-20160816; b=BWk1jGI3GG3PSrGQe5N8KRnQNloqbRLetZ7jPBwK4d+ZMRVyibyJt9BZ1ZfQ4tuUBU nzF7dNbsOh9TWsOOhMxTnq/4Ecbd96/8W6kQRq9RRLAn7i4YdMWP91iyYQxga9pYPtnS ATByqlYPHBpYvAhXnz0kd4Pcq6NQ6VUg3h6VYBQlPArMzF0WItrI0zUiXF0T8sq1lBb8 q0FgcgBFIiCvOtCTq1Q6OahCayXkEuXlSHvKDcEdyN1GfLExmwHW9R+4veEjwnQ1FyL5 YnRVB6jC82MFSBr8kI4d9x3Nbho13ugKi3Er/3Fd7lKE3hjDBzzYHaWCuzmvWrGeDT5o 7rZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=aIflHOg5j1TD5f9dlGljKMBH2UICanRLywB993J/YwY=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=NPn0MxgkmfLv+erc7T0Vu9kWbZYwIwqVqVFSdsHE0olo1MlYoZ7hNXIM2uZpyShcFV wn7Hii3CAlLCfLIYf1k8PD9NvTk8P6SZjnsy9brqXBhCzWbFmAxdRchXlqQZcYnbdofz 91JeDqWsdpdFPxJIuF2fITU2JfO5+nIe2tWaqVC87O4SlzPbqfkEY+cXJYkm5DKkAzu+ ffbaC/zFjGyeabTmkCPvyZE+owqxfhQSCOQz6aMuO4fgiPE1iFygGhLqtGrRHRo8OCf/ 15ztTMgMGTntBo9cwKYHnMSmcWkMkSaeJMANKI52TZ5t08upENUUzgRd1eMlq+X2Eoy0 AcLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QxRuoIVz; spf=pass (google.com: domain of linux-kernel+bounces-551-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-551-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:41:02 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:57 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 08/14] net: phy: at803x: add qca8084 switch registe access Date: Fri, 15 Dec 2023 15:39:58 +0800 Message-ID: <20231215074005.26976-9-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VS13WMsugyyZgO5FD35iY-Z8g9HFBcn9 X-Proofpoint-ORIG-GUID: VS13WMsugyyZgO5FD35iY-Z8g9HFBcn9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333460993933834 X-GMAIL-MSGID: 1785333460993933834 For qca8084 chip, there are GCC, TLMM and security control modules besides the PHY, these moudles are accessed with 32 bits value, which has the special MDIO sequences to read or write this 32bit register. There are initial configurations configured to make qca8084 PHY probeable, and the MDIO address of qca8084 can be programmed for the PHY device and PCS device. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 85 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index cd1bdb61d122..4982bde5a8a5 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -296,6 +296,13 @@ #define QCA8084_MMD7_IPG_OP 0x901d #define QCA8084_IPG_10_TO_11_EN BIT(0) +/* QCA8084 includes secure control module, which supports customizing the + * MDIO address of PHY device and PCS device, the register of secure control + * is accessed by MDIO bus with the special MDIO sequences. + */ +#define QCA8084_HIGH_ADDR_PREFIX 0x18 +#define QCA8084_LOW_ADDR_PREFIX 0x10 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -408,6 +415,84 @@ static int at803x_read_page(struct phy_device *phydev) return AT803X_PAGE_FIBER; } +static void qca8084_split_addr(u32 regaddr, u16 *r1, u16 *r2, + u16 *page, u16 *sw_addr) +{ + *r1 = regaddr & 0x1c; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0xffff; + + regaddr >>= 16; + *sw_addr = regaddr & 0xff; +} + +static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) +{ + return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5), + sw_addr & 0x1f, page); +} + +static int __qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val) +{ + int ret, data; + + ret = __mdiobus_read(bus, addr, reg); + if (ret >= 0) { + data = ret; + + ret = __mdiobus_read(bus, addr, reg | BIT(1)); + if (ret >= 0) + *val = data | ret << 16; + } + + return ret < 0 ? ret : 0; +} + +static int __qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val) +{ + int ret; + + ret = __mdiobus_write(bus, addr, reg, lower_16_bits(val)); + if (!ret) + ret = __mdiobus_write(bus, addr, reg | BIT(1), upper_16_bits(val)); + + return ret; +} + +static int qca8084_mii_modify(struct phy_device *phydev, u32 regaddr, + u32 clear, u32 set) +{ + struct mii_bus *bus; + u16 reg, addr, page, sw_addr; + u32 val; + int ret; + + bus = phydev->mdio.bus; + mutex_lock(&bus->mdio_lock); + + qca8084_split_addr(regaddr, ®, &addr, &page, &sw_addr); + ret = __qca8084_set_page(bus, sw_addr, page); + if (ret < 0) + goto qca8084_mii_modify_exit; + + ret = __qca8084_mii_read(bus, QCA8084_LOW_ADDR_PREFIX | addr, + reg, &val); + if (ret < 0) + goto qca8084_mii_modify_exit; + + val &= ~clear; + val |= set; + ret = __qca8084_mii_write(bus, QCA8084_LOW_ADDR_PREFIX | addr, + reg, val); +qca8084_mii_modify_exit: + mutex_unlock(&bus->mdio_lock); + return ret; +}; + static int at803x_enable_rx_delay(struct phy_device *phydev) { return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, From patchwork Fri Dec 15 07:39:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179078 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9107121dys; Thu, 14 Dec 2023 23:50:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQfezrVBRqhjTJ7vM4r9E9VrDqUx9zHmCYz2IMoVJSlX0Hk8F+cmRU15PV+oeVjF4YktMH X-Received: by 2002:a17:90a:4f03:b0:28a:f281:4c41 with SMTP id p3-20020a17090a4f0300b0028af2814c41mr1808907pjh.90.1702626638013; Thu, 14 Dec 2023 23:50:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626638; cv=none; d=google.com; s=arc-20160816; b=LvMa7yc3KKu3yvITYgglCub5sbe/K09hreYvx91t70LC7NTlE/j0vfWz34llH0Z43n 888v0VkmTsJq/FhVOasNkx/KmkqWYIQLcoApjlal+YBrezH8Nk6QVnBRQ3T97iHa0u7N ekWyQUn4lgKWvdodJbNHEEq6+AqK9Ew8bu6DjVX0B/B0bjH3oxpoZhtQYzJP1tXG5wSb Djm0owTZE5JLXGS17bBKhhT9tDVBs/84aIPLYhLvSCze+sbsvB3tFZxFS9/1v/gahyJ7 SlyUhQ9oX7/J3TCmHAsun55ySz2vzX4Wrn19Yp3l9FWLKs2PTvDO0IAjjYroWVwDR3yM 7v+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RdEmD3F3bi1zawZ4fZPZaXG3kduxBS2lem2ZYGbtznE=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=XOJkJytAvXfWwpXdJb9/J3XHyvm6STNkzp6Epgq9gpOUWNiujYitPMOJfDpBn9LLQx iJLNQq5RkJL3371AhjNc48K4UmNYCq0YdjgPJfbr4X6fRX6NWSgQMXlnyz/JcaodkNoH pVCsBkTkIIGTFDYJs5OMcVqgEk4T/ger1tlc7jthLMyhD1An6ImRqoUqaWTibL4/dZw9 hIdKgTPrkwwnuAu8AeiMIfZ5jUR686PYLvLGIPvhApf1FLVjuiLG96fJQN8PZa9odFqE ZMSX8TQva72hQuODxSaNQKuQIae+xE8REiZHMnmnbPp7bKsGiOFiPHQgvCIYsslpBPYh M2Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=LGYpKm3L; spf=pass (google.com: domain of linux-kernel+bounces-550-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-550-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:41:06 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:02 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 09/14] net: phy: at803x: set MDIO address of qca8084 PHY Date: Fri, 15 Dec 2023 15:39:59 +0800 Message-ID: <20231215074005.26976-10-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sr5AobqIUzm8XPFAzPsebmS0KoR_PxX4 X-Proofpoint-GUID: sr5AobqIUzm8XPFAzPsebmS0KoR_PxX4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333429786233882 X-GMAIL-MSGID: 1785333429786233882 Program the MDIO address of qca8084 PHY and PCS device in the PHY probe function. The MDIO address of qca8084 device is configured according to the property "qcom,phy-addr-fixup" of phy node, which defines the MDIO address for 4 PHYs and 3 PCSes, each MDIO address occupies 5 bits in the config register. The MDIO address of qca8084 should be configured correctly before doing the clock initialization in the PHY probe function, so the property "reg" can't be used to configure the MDIO address of phy device one by one, the clock initialization will be configured with all 4 PHY devices in one PHY probe function. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 4982bde5a8a5..c8830898ce2e 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -303,6 +303,18 @@ #define QCA8084_HIGH_ADDR_PREFIX 0x18 #define QCA8084_LOW_ADDR_PREFIX 0x10 +#define QCA8084_PCS_CFG 0xc90f014 +#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10) + +#define QCA8084_EPHY_CFG 0xc90f018 +#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10) +#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) +#define QCA8084_EPHY_LDO_EN GENMASK(21, 20) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -764,6 +776,51 @@ static int at803x_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) +{ + struct device_node *node; + u32 addr[7]; + int ret; + + node = phydev->mdio.dev.of_node; + + /* The property "qcom,phy-addr-fixup" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32_array(node, "qcom,phy-addr-fixup", + addr, ARRAY_SIZE(addr)); + if (ret) + return ret == -EINVAL ? 0 : ret; + + /* There are 4 PHYs and 3 PCSes on qca8084 chip, each device address + * occupies 5 bits of the config register to customize the MDIO address. + */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_ADDR0_MASK | + QCA8084_EPHY_ADDR1_MASK | + QCA8084_EPHY_ADDR2_MASK | + QCA8084_EPHY_ADDR3_MASK, + FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]) | + FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]) | + FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]) | + FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3])); + if (ret) + return ret; + + return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, + QCA8084_PCS_ADDR0_MASK | + QCA8084_PCS_ADDR1_MASK | + QCA8084_PCS_ADDR2_MASK, + FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]) | + FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]) | + FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); +} + +static int qca8084_probe(struct phy_device *phydev) +{ + return qca8084_parse_and_set_phyaddr(phydev); +} + static int at803x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -776,6 +833,9 @@ static int at803x_probe(struct phy_device *phydev) phydev->priv = priv; + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return qca8084_probe(phydev); + ret = at803x_parse_dt(phydev); if (ret) return ret; @@ -2510,6 +2570,7 @@ static struct phy_driver at803x_driver[] = { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), .name = "Qualcomm QCA8084", .flags = PHY_POLL_CABLE_TEST, + .probe = at803x_probe, .config_intr = at803x_config_intr, .handle_interrupt = at803x_handle_interrupt, .get_tunable = at803x_get_tunable, From patchwork Fri Dec 15 07:40:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179072 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9105944dys; Thu, 14 Dec 2023 23:47:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IFugQPUU5+sKsPrHWgkrqj62v1NDHJxgIcyQMtaE7Ei5M+Y/yphh/e+qgt0yDBoudDAxG+t X-Received: by 2002:a50:d594:0:b0:54b:3d7e:2afa with SMTP id v20-20020a50d594000000b0054b3d7e2afamr5416981edi.10.1702626435318; Thu, 14 Dec 2023 23:47:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626435; cv=none; d=google.com; s=arc-20160816; b=yyG4ZLrU1iL/hqzTKjbIV9aoMACKwotRhlD/6g4oFRGrU0HKFxBmEP+H55pqIaCPD5 nJNpTNUJu/I/QDEtmmMIzphNnNhN/hL4tuF4ZStpwUscdrLagmvxefssyXTfoq5Do2CQ LDmqQ0UqqCGy2voIoZqWsF5mBgnLjVAzDJIU+wgMG2PI8SJ/gJW8WbpqQpqXil1j+Vwh /Ahgcq8AeTWH3KCeGujRX/6JtvvMFr9KtW6+fEFS7GUty0WEA+3ajJo1pidPX9RulTpG tfnMS2ArEEME113hOROYPd6cAVEIhuSjU4hWFSuaNwFPFy7nPmZ4ReDEC/g/2aTGFyrQ bLUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=0tzAijJ2T6jjsc1+KfY3s2c76n6zIbSFI1AZ27K6OBk=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=JEvpzTOQur17L4B8Pm6kycz9BgMhAqXFEtu21BV+4zBiiXjzl0v98n5QmK3PgHdAwJ YCPQNZglT10EQaisXmoKb3p7NnNRpxCEOcTBiin9BSClJQUkbhanhwC+00WHS2LDqN/n J6Lf7JS69nMxRRe6L1ZEZdkwdHWiybSFJeDch+mi7O49gtvpamvuUlkH/5mY+yo26w5A xK2qN0aWpPjcm/C4pu5Y9N8tHjZ8TSzQgLaBAgcAUj+7Bc3n7iRQ2DEcBa9GQWd/Gxux FoE/EZ8hlxb/C/1nrdV0BkoO+SGY9qaWBkAHtcTBhb//F4mZpscwAuJBOFZjsMH2FZmc F8rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="DXbJe/p4"; spf=pass (google.com: domain of linux-kernel+bounces-554-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-554-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:41:10 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:06 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 10/14] net: phy: at803x: parse qca8084 clocks and resets Date: Fri, 15 Dec 2023 15:40:00 +0800 Message-ID: <20231215074005.26976-11-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: OLesixKOsNH-XVeCyfJ7bjwkc9o125RD X-Proofpoint-GUID: OLesixKOsNH-XVeCyfJ7bjwkc9o125RD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333217217577555 X-GMAIL-MSGID: 1785333217217577555 These clock and reset IDs are needed to bring up qca8084, after the initializations with these clocks and resets, the PHY function can be accessed correctly such as reading the capabilities of PHY. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 87 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c8830898ce2e..4c884d6b60bc 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 #define AT803X_SFC_ASSERT_CRS BIT(11) @@ -337,6 +339,52 @@ static struct at803x_hw_stat qca83xx_hw_stats[] = { { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, }; +enum { + SRDS0_SYS_CLK, + SRDS1_SYS_CLK, + GEPHY0_SYS_CLK, + GEPHY1_SYS_CLK, + GEPHY2_SYS_CLK, + GEPHY3_SYS_CLK, +}; + +enum { + SRDS0_SYS_RESET, + SRDS1_SYS_RESET, + GEPHY0_SYS_RESET, + GEPHY1_SYS_RESET, + GEPHY2_SYS_RESET, + GEPHY3_SYS_RESET, + GEPHY0_RESET, + GEPHY1_RESET, + GEPHY2_RESET, + GEPHY3_RESET, + GEPHY_DSP_RESET, +}; + +static const char *const qca8084_clock_name[] = { + "srds0_sys", + "srds1_sys", + "gephy0_sys", + "gephy1_sys", + "gephy2_sys", + "gephy3_sys", +}; + +static const char *const qca8084_reset_name[] = { + "srds0_sys", + "srds1_sys", + "gephy0_sys", + "gephy1_sys", + "gephy2_sys", + "gephy3_sys", + "gephy0_soft", + "gephy1_soft", + "gephy2_soft", + "gephy3_soft", + "gephy_dsp", +}; + struct at803x_priv { int flags; u16 clk_25m_reg; @@ -348,6 +396,8 @@ struct at803x_priv { struct regulator_dev *vddio_rdev; struct regulator_dev *vddh_rdev; u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; + struct clk *clk[ARRAY_SIZE(qca8084_clock_name)]; + struct reset_control *reset[ARRAY_SIZE(qca8084_reset_name)]; }; struct at803x_context { @@ -816,8 +866,45 @@ static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); } +static int qca8084_parse_dt(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int i; + + priv = phydev->priv; + for (i = 0; i < ARRAY_SIZE(qca8084_clock_name); i++) { + priv->clk[i] = devm_clk_get_optional(&phydev->mdio.dev, + qca8084_clock_name[i]); + if (IS_ERR(priv->clk[i])) { + phydev_err(phydev, "failed to get the clock ID %s!\n", + qca8084_clock_name[i]); + + return PTR_ERR(priv->clk[i]); + } + } + + for (i = 0; i < ARRAY_SIZE(qca8084_reset_name); i++) { + priv->reset[i] = devm_reset_control_get_optional_exclusive(&phydev->mdio.dev, + qca8084_reset_name[i]); + if (IS_ERR(priv->reset[i])) { + phydev_err(phydev, "failed to get the reset ID %s!\n", + qca8084_reset_name[i]); + + return PTR_ERR(priv->reset[i]); + } + } + + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { + int ret; + + ret = qca8084_parse_dt(phydev); + if (ret) + return ret; + return qca8084_parse_and_set_phyaddr(phydev); } From patchwork Fri Dec 15 07:40:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179070 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9105646dys; Thu, 14 Dec 2023 23:46:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IFnp2B+93dGdV+1PmCdxe1j4YEwj8+RCrX3MEE4b8Xz7rEjcXjvQTFx50e6pWi4F947DpWT X-Received: by 2002:a17:906:6a27:b0:a1f:6551:6405 with SMTP id qw39-20020a1709066a2700b00a1f65516405mr13321450ejc.37.1702626385659; Thu, 14 Dec 2023 23:46:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626385; cv=none; d=google.com; s=arc-20160816; b=pCquDPfK2AGyJlDd5xkh95vxFeq3QLHnV/ikSl51JBSkUVF/OgiDBFgw9nfikoA6Ek EkqwPB6jFO1I8RkQ44p9gxBFpBKkGXjShBG9uKNkEx6jjjYkWT/6it776lvz+Pb7ITxQ bwvs+Cb1mgfQOE0hByRCyyuz23BabawQDELgze8+/IYYKuVDmIQ/GiP4NzbsoFcG6hMC 4xYL78KpA86+Doa2PWnEmev25qdl5xegx3tnrr7G/wcSNXltUNohy10ygk61IIW4g+C2 myLfiABay4v9SLCwJ46CWi+26/CYzG3DdnMbilbgRE/xvVcBJ8YitWwa90S6zzhVeo/A x8YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=01YLgR+6wJBf41/THxnAppWhWQ25mr18n1mS+L86Yf8=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=Q4K0/Ub5kGD0P/bdBEixAdjK83NAMnQEKtntvCeFNI4GfR85Vn3fNYV581aPO4yhce 9MKKkYhXTH6Tbl9kRvpJzhZVORygcLlMh5cSr4jP7oWg4PckZoVszL6UNJYlgGFYwq6U Kv4agLk+cbvCSlLwCeB6MOenk8TnH4Eo3chxoaFFN6y/qoFnA/k0XLTijmMp9gam+dm/ Lj4+neCrHzuTBs36zZuRXwfD5DgVOV1/gERbCVdZ48pMWvcoLopeh3EEbADY5EuAl6lS MNC6fLz7BtSGqvGic2zeVp+uHxmdeolnkhx0hTWViCQndjC7nFX67E1LY0IG3mNwqn5M CcOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=dKAe1X2c; spf=pass (google.com: domain of linux-kernel+bounces-552-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-552-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:41:15 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:10 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 11/14] net: phy: at803x: add qca808x initial config sequence Date: Fri, 15 Dec 2023 15:40:01 +0800 Message-ID: <20231215074005.26976-12-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: js2mG3IoUt3K-BjxiWZi_PVM-QOzSeY_ X-Proofpoint-ORIG-GUID: js2mG3IoUt3K-BjxiWZi_PVM-QOzSeY_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333165009945554 X-GMAIL-MSGID: 1785333165009945554 After GPIO reset, these Ethernet clock sequence needs to be configured before reading the features of PHY, the Ethernet system clock works on 25MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 4c884d6b60bc..9885a728c72a 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -897,6 +897,84 @@ static int qca8084_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_clock_config(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + /* The ethernet clock IDs are only defined in one PHY device + * tree node, and these ethernet clocks only needs to be configured + * one time, which work on the clock rate 25MHZ. + */ + priv = phydev->priv; + if (!priv->clk[SRDS0_SYS_CLK]) + return 0; + + ret = clk_set_rate(priv->clk[SRDS0_SYS_CLK], 25000000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS1_SYS_CLK]); + if (ret) + return ret; + + /* Reset PCS system clocks */ + reset_control_assert(priv->reset[SRDS0_SYS_RESET]); + reset_control_assert(priv->reset[SRDS1_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[SRDS0_SYS_RESET]); + reset_control_deassert(priv->reset[SRDS1_SYS_RESET]); + + ret = clk_prepare_enable(priv->clk[GEPHY0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY1_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY2_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY3_SYS_CLK]); + if (ret) + return ret; + + /* Reset ethernet system clocks */ + reset_control_assert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY3_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY3_SYS_RESET]); + + /* Release ethernet DSP reset */ + reset_control_deassert(priv->reset[GEPHY0_RESET]); + reset_control_deassert(priv->reset[GEPHY1_RESET]); + reset_control_deassert(priv->reset[GEPHY2_RESET]); + reset_control_deassert(priv->reset[GEPHY3_RESET]); + reset_control_deassert(priv->reset[GEPHY_DSP_RESET]); + + /* Enable efuse loading into analog circuit */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_LDO_EN, 0); + if (ret) + return ret; + + fsleep(10000); + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -905,7 +983,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_parse_and_set_phyaddr(phydev); + ret = qca8084_parse_and_set_phyaddr(phydev); + if (ret) + return ret; + + return qca8084_clock_config(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Fri Dec 15 07:40:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179071 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9105898dys; 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Fri, 15 Dec 2023 07:41:19 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:15 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 12/14] net: phy: at803x: configure qca8084 common clocks Date: Fri, 15 Dec 2023 15:40:02 +0800 Message-ID: <20231215074005.26976-13-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ydnC9ijGTP51n5Tjq2aUS8FJyQTbYZ78 X-Proofpoint-GUID: ydnC9ijGTP51n5Tjq2aUS8FJyQTbYZ78 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333207254094381 X-GMAIL-MSGID: 1785333207254094381 After initial clock sequence, the clock source 312.5MHZ is available, the common clocks based on clock source 312.5MHZ needs to be configured, which includes APB bridge clock tree with rate 312.5MHZ, AHB clock tree with 104.17MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 9885a728c72a..3ef4eacf40c7 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -340,6 +340,14 @@ static struct at803x_hw_stat qca83xx_hw_stats[] = { }; enum { + APB_BRIDGE_CLK, + AHB_CLK, + SEC_CTRL_AHB_CLK, + TLMM_CLK, + TLMM_AHB_CLK, + CNOC_AHB_CLK, + MDIO_AHB_CLK, + MDIO_MASTER_AHB_CLK, SRDS0_SYS_CLK, SRDS1_SYS_CLK, GEPHY0_SYS_CLK, @@ -363,6 +371,14 @@ enum { }; static const char *const qca8084_clock_name[] = { + "apb_bridge", + "ahb", + "sec_ctrl_ahb", + "tlmm", + "tlmm_ahb", + "cnoc_ahb", + "mdio_ahb", + "mdio_master_ahb", "srds0_sys", "srds1_sys", "gephy0_sys", @@ -975,6 +991,53 @@ static int qca8084_clock_config(struct phy_device *phydev) return 0; } +static int qca8084_common_clock_init(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + priv = phydev->priv; + /* Enable APB bridge tree clock */ + ret = clk_set_rate(priv->clk[APB_BRIDGE_CLK], 312500000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[APB_BRIDGE_CLK]); + if (ret) + return ret; + + /* Enable AHB tree clocks */ + ret = clk_set_rate(priv->clk[AHB_CLK], 104170000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SEC_CTRL_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[TLMM_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[TLMM_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[CNOC_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[MDIO_AHB_CLK]); + if (ret) + return ret; + + return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -987,7 +1050,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_clock_config(phydev); + ret = qca8084_clock_config(phydev); + if (ret) + return ret; + + return qca8084_common_clock_init(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Fri Dec 15 07:40:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179073 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9106062dys; Thu, 14 Dec 2023 23:47:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IEqRZmmiCH5qSNedvTrgf0tCSsBLXDwVqNVFMXlfbm1xbotpLLWhyb7wcow+Mm08xXIuzRe X-Received: by 2002:a05:6402:2227:b0:54f:74e6:5c72 with SMTP id cr7-20020a056402222700b0054f74e65c72mr5511649edb.41.1702626459849; Thu, 14 Dec 2023 23:47:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626459; cv=none; d=google.com; s=arc-20160816; b=wtU4vodyWcgOZ0hqxpWdXyU2HyPJLyDO1D+FKVNlEx8QGDj3pXPxJ5ky2xQMUi7g9U 4N7nQ96fzav9YUrYGIXNIdZx5XpAOFXbmLi7muvYnVTDbnS0BaRvT/VGMkSqHQWfZXHq xDlr0LfcTUnbFp6WRQF00BNO7kUE5+64KRvL6eBmkxw+aZIB4e+NhyLqwnkp9hVqpsya 2EHZIn6qcEX5xugK81gwDA84AhPVCDw1BnoTxDKDEJ2tP6sW+ZNqK/bsYAPJDo93Smo4 qiReJf3g8LKWztuk8vB2vrPdz/yUa38YKUPVgFYTH7YsIp72GP67wlPgGrUA75pXoKTT EoLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DpLGnFLCKSY0tJ27ExzgGixGS/RVtKjkJCrVDkkBLJ0=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=mHeDmPP7spgo1cPEZQtC5M+2pBeM+iSiH/j14/ZOcChFc1eFt8BSIoAvKITSVTWyDN XLMx46Z4l5wqBr/j82Tfp79zxiKiAbmzkp5P8ncTTHrETU52jiLyNRzz8YH2TZg+ZvU/ krl2lyAd2GdZX9Wd9ivx3B/HAWTtNQmWsM79lSH3cunEb8ynC1ZzjAHMtisQvsmgIIvX dF9kvWFdrKjdNr9aZkq8WYBwbZEEkEsQhZNLJOrVioX04ZM3LxYQV8tYVn5ZZ5o6FHPw JxILadzFonRyC29gKkaVI05MU89iememdJ9Dv3rx+yEk/+mSd2zLVcWZ5xmag/WO3miW HMQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=KHUNE3HD; spf=pass (google.com: domain of linux-kernel+bounces-555-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-555-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:41:23 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:19 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 13/14] net: phy: at803x: configure qca8084 work mode Date: Fri, 15 Dec 2023 15:40:03 +0800 Message-ID: <20231215074005.26976-14-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: m2vpYiDdnsP8sPIVRPedSndbDS1d-WoS X-Proofpoint-ORIG-GUID: m2vpYiDdnsP8sPIVRPedSndbDS1d-WoS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333242683090581 X-GMAIL-MSGID: 1785333242683090581 There are four kind of work modes supported by qca8084. 1. Quad PHYs work on 10g-qxgmii. 2. PHY1, PHY2, PHY3 wors on 10g-qxgmii, PHY4 works on sgmii. 3. Quad PHYs connected with internal MACs by GMII, which works on switch mode. 4. PHY1, PHY2, PHY3 connected with internal MACs by GMII, PHY4 works on sgmii. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 53 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 3ef4eacf40c7..ac72b0551ed8 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -317,6 +317,13 @@ #define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) #define QCA8084_EPHY_LDO_EN GENMASK(21, 20) +#define QCA8084_WORK_MODE_CFG 0xc90f030 +#define QCA8084_WORK_MODE_MASK GENMASK(5, 0) +#define QCA8084_WORK_MODE_QXGMII (BIT(5) | GENMASK(3, 0)) +#define QCA8084_WORK_MODE_QXGMII_PORT4_SGMII (BIT(5) | GENMASK(2, 0)) +#define QCA8084_WORK_MODE_SWITCH BIT(4) +#define QCA8084_WORK_MODE_SWITCH_PORT4_SGMII BIT(5) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -1038,6 +1045,46 @@ static int qca8084_common_clock_init(struct phy_device *phydev) return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); } +static int qca8084_parse_and_set_work_mode(struct phy_device *phydev) +{ + struct device_node *node; + struct at803x_priv *priv; + u32 value, work_mode; + int ret; + + node = phydev->mdio.dev.of_node; + priv = phydev->priv; + + /* The property "qcom,phy-work-mode" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32(node, "qcom,phy-work-mode", &value); + if (ret) + return ret == -EINVAL ? 0 : ret; + + switch (value) { + case 0: + work_mode = QCA8084_WORK_MODE_QXGMII; + break; + case 1: + work_mode = QCA8084_WORK_MODE_QXGMII_PORT4_SGMII; + break; + case 2: + work_mode = QCA8084_WORK_MODE_SWITCH; + break; + case 3: + work_mode = QCA8084_WORK_MODE_SWITCH_PORT4_SGMII; + break; + default: + phydev_err(phydev, "invalid qcom,phy-work-mode %d\n", value); + return -EINVAL; + } + + return qca8084_mii_modify(phydev, QCA8084_WORK_MODE_CFG, + QCA8084_WORK_MODE_MASK, + FIELD_PREP(QCA8084_WORK_MODE_MASK, work_mode)); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1054,7 +1101,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_common_clock_init(phydev); + ret = qca8084_common_clock_init(phydev); + if (ret) + return ret; + + return qca8084_parse_and_set_work_mode(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Fri Dec 15 07:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 179074 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp9106207dys; Thu, 14 Dec 2023 23:48:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IE1ShkUWvWQoIuL1pUZENLTMZANX4Qj2XNk9JaCw+F+1frwn8ZKq9+PIE5jkOd67VUmmKlZ X-Received: by 2002:a05:620a:15a2:b0:77f:38c:f03 with SMTP id f2-20020a05620a15a200b0077f038c0f03mr12489512qkk.120.1702626484094; Thu, 14 Dec 2023 23:48:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702626484; cv=none; d=google.com; s=arc-20160816; b=U6kZs3zCsMStMhkDjuH0Pc7FROZJ73qPhEVQfbU3+fvNft2bJDu5m+sm/SAqB31ufJ 4l8Xp/CORTt2EnheECnZY7Wcgm7JMqSNQxBCSNS1/TyG7WAWHbSJirLUlB++b+HIY08+ cDbFDPPKKs0LDCnbwUXgjOr3DwPm5GBEOkLP1AVhpOedQYDB0kB7Wt3V2ne1zRM7Qcwq 6MtEzBYvxAaXOYY28DSx+epuJsuBtMcBV2elHLSLU/gSVpTifuqHGlOIjFIWFAqSlpux q6DW5aSDC4Q4TFPwGxXPSXx8XQbon0X6v4LDwxRSpourDydWWD+XjdKU8TanSIcSgNk7 Vfng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=AhES8Y7x+ZpiqbfFpeHU+5rxqGlvKWJu/Mp3zVbaca0=; fh=/GuWXIFJTb2Z3LVYajHwooJWphp6NrpriHhj5GHcik0=; b=gIyTBrAuOrDY5VTv9nJSUqTOty3G6HwyKmSPHRO1734vilAq/x/Y5TJnO/N6j5ozDW jGWaaCXRuaEEiRl9jNeFy6BeUYCdaPC3apo1Tzd9ys3Ci7/9gD41qGucfIlKgQa3qDAn QpUU6bmprMmKI0+aDkVofD/mGqORfg3Kf1OzExD5D8VexZwMQ4w/3KUtONhQ971GBjSb Z+F96LYuwwovZ6OHIFzC4GnKumDsFij/LU213K3+wjJbGSr1SI1KIwtdC3NxsOFHjFPq 2ZsUuVcfA5BRxLy23CC26RpR2Nwb2TOagIpZPJK6XQDBm7SkfxfAZCgAYSShE75AYZAK oYRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=htNYVwBU; spf=pass (google.com: domain of linux-kernel+bounces-556-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-556-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 15 Dec 2023 07:41:27 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:23 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties Date: Fri, 15 Dec 2023 15:40:04 +0800 Message-ID: <20231215074005.26976-15-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: yx8mAsx_35qSXdlQGbbb70N0gxc5x5Qj X-Proofpoint-GUID: yx8mAsx_35qSXdlQGbbb70N0gxc5x5Qj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=728 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785333268095791259 X-GMAIL-MSGID: 1785333268095791259 The following properties are added for qca8084 PHY. 1. add the compatible string "ethernet-phy-id004d.d180" since the PHY device is not accessible during MDIO bus register. 2. add property "qcom,phy-addr-fixup" for customizing MDIO address. 3. add property "qcom,phy-work-mode" for specifying qca8084 PHY work mode. 4. add the initial clocks and resets. Signed-off-by: Luo Jie --- .../devicetree/bindings/net/qca,ar803x.yaml | 158 +++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da86..febff039a44f 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -14,9 +14,6 @@ maintainers: description: | Bindings for Qualcomm Atheros AR803x PHYs -allOf: - - $ref: ethernet-phy.yaml# - properties: qca,clk-out-frequency: description: Clock output frequency in Hertz. @@ -85,6 +82,161 @@ properties: $ref: /schemas/regulator/regulator.yaml unevaluatedProperties: false + qcom,phy-addr-fixup: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + MDIO address for 4 PHY devices and 3 PCS devices + + qcom,phy-work-mode: + description: PHY device work mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clock + description: PHY initial common clock configs + + clock-names: + items: + - const: apb_bridge + - const: ahb + - const: sec_ctrl_ahb + - const: tlmm + - const: tlmm_ahb + - const: cnoc_ahb + - const: mdio_ahb + - const: mdio_master_ahb + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + + resets: + items: + - description: PCS0 system reset + - description: PCS1 system reset + - description: EPHY0 system reset + - description: EPHY1 system reset + - description: EPHY2 system reset + - description: EPHY3 system reset + - description: EPHY0 software reset + - description: EPHY1 software reset + - description: EPHY2 software reset + - description: EPHY3 software reset + - description: Ethernet DSP reset + description: PHY initial common reset configs + + reset-names: + items: + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + - const: gephy0_soft + - const: gephy1_soft + - const: gephy2_soft + - const: gephy3_soft + - const: gephy_dsp + +allOf: + - $ref: ethernet-phy.yaml# + + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d180 + then: + properties: + clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clock + clock-names: + items: + - const: apb_bridge + - const: ahb + - const: sec_ctrl_ahb + - const: tlmm + - const: tlmm_ahb + - const: cnoc_ahb + - const: mdio_ahb + - const: mdio_master_ahb + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + resets: + items: + - description: PCS0 system reset + - description: PCS1 system reset + - description: EPHY0 system reset + - description: EPHY1 system reset + - description: EPHY2 system reset + - description: EPHY3 system reset + - description: EPHY0 software reset + - description: EPHY1 software reset + - description: EPHY2 software reset + - description: EPHY3 software reset + - description: Ethernet DSP reset + reset-names: + items: + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + - const: gephy0_soft + - const: gephy1_soft + - const: gephy2_soft + - const: gephy3_soft + - const: gephy_dsp + required: + - qcom,phy-addr-fixup + - qcom,phy-work-mode + - clocks + - clock-names + - resets + - reset-names + else: + properties: + qcom,phy-addr-fixup: false + qcom,phy-work-mode: false + unevaluatedProperties: false examples: