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Signed-off-by: Wayne Chang --- V1 -> V2:address the issue on phy-names property .../bindings/usb/nvidia,tegra-xudc.yaml | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index fd6e7c81426e..52488a731c4e 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -22,6 +22,7 @@ properties: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 - nvidia,tegra194-xudc # For Tegra194 + - nvidia,tegra234-xudc # For Tegra234 reg: minItems: 2 @@ -90,21 +91,27 @@ properties: phys: minItems: 1 + maxItems: 8 description: Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. phy-names: minItems: 1 + maxItems: 8 items: - - const: usb2-0 - - const: usb2-1 - - const: usb2-2 - - const: usb2-3 - - const: usb3-0 - - const: usb3-1 - - const: usb3-2 - - const: usb3-3 + enum: + - usb2-0 + - usb2-1 + - usb2-2 + - usb2-3 + - usb3-0 + - usb3-1 + - usb3-2 + - usb3-3 + + dma-coherent: + type: boolean avddio-usb-supply: description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. @@ -153,6 +160,7 @@ allOf: enum: - nvidia,tegra186-xudc - nvidia,tegra194-xudc + - nvidia,tegra234-xudc then: properties: reg: From patchwork Fri Nov 11 10:14:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18649 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656471wru; Fri, 11 Nov 2022 02:19:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf66F2Omyy+A8psBqv4f4xfXcVSlaD0Q9vEMP8OzIZCyVl2gWBSZfDz+Kk+HWO5JGNzc44E9 X-Received: by 2002:a50:bac8:0:b0:459:53dc:adc9 with SMTP id x66-20020a50bac8000000b0045953dcadc9mr862744ede.166.1668161966090; Fri, 11 Nov 2022 02:19:26 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161966; cv=pass; d=google.com; s=arc-20160816; b=yFgEVddZ838LRpj2z87MVSVi4wHBt7LL+JVnNJhe7bhtwtkZbInKVhQeDsHd8EGM0c UwHgamMNGa72ZZrjf1sNl7ZcACqiLm8MD8ceex4NzQMxVQPvJn60HYy3tHSRzzf44dD7 yupgavYuXYZ9iCDuI1R/Ox5lWwsIH320SDgoC6GQVFC/vrOG0o3UI+Fh7HjiXYYFHZV3 efy8pDdLSVJcp17Yn/FO/LWxrxNiFjYDxvtSU8VFSxSebiqnKgsDlgo8xycOFRFv5nau Zmv/CaIX2T9G9wP3cYJQ+Rzx1xMV4JXWc2U7e9mcTJ6BCqCAGXJy8+DiIhdlLzCF6ieH Vyvg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vs/S4cWkFvBdXcr1u/3YfmRTM0i3TVOlY3uRjy0sRLI=; b=bayoWncZaJ7NnJMcCnG2uNwfeII+QxZD2A7MdmxTHanGNoV21HAW5PggZnQIAjSlKQ Zx8G5K+vNGjpBt2KCfmtr9+3BUhORO7FsNCcGkHluceIsoqf0ZxIyBV8EF30GmVkxD5F QrzSjwM1z3RYdGeQlVYbmjNI51Rj8tXKH/3EwvH1WstyGM0Fii+aFWvOjkMa8IHPUwr5 4Jp+tnOPiSsEzB9Ge/W1qyk+n0A3xEoc3fQ46s/4qqLpyWO407snkryUEqgnBAQxGubG nxHg6pN+gdgNoh8F/i6BgXq3hIkxeDRQEluDYKoWviuYsSEuEmSufz31jWWv3R9WgGl5 a9rg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=iQ1Bv276; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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This controller supports the USB 3.1 specification. Signed-off-by: Wayne Chang --- V1 -> V2: new change for adding nvidia,tegra234-xusb.yaml .../bindings/usb/nvidia,tegra234-xusb.yaml | 159 ++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml new file mode 100644 index 000000000000..d78ee88ed208 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 xHCI controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The Tegra xHCI controller supports both USB2 and USB3 interfaces + exposed by the Tegra XUSB pad controller. + +properties: + compatible: + const: nvidia,tegra234-xusb + + reg: + items: + - description: base and length of the xHCI host registers + - description: base and length of the XUSB FPCI registers + - description: base and length of the XUSB bar2 registers + + reg-names: + items: + - const: hcd + - const: fpci + - const: bar2 + + interrupts: + items: + - description: xHCI host interrupt + - description: mailbox interrupt + + clocks: + items: + - description: XUSB host clock + - description: XUSB Falcon source clock + - description: XUSB SuperSpeed clock + - description: XUSB SuperSpeed source clock + - description: XUSB HighSpeed clock source + - description: XUSB FullSpeed clock source + - description: USB PLL + - description: reference clock + - description: I/O PLL + + clock-names: + items: + - const: xusb_host + - const: xusb_falcon_src + - const: xusb_ss + - const: xusb_ss_src + - const: xusb_hs_src + - const: xusb_fs_src + - const: pll_u_480m + - const: clk_m + - const: pll_e + + interconnects: + items: + - description: read client + - description: write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the XUSB pad controller that is used to configure + the USB pads used by the XHCI controller + + phys: + minItems: 1 + maxItems: 8 + + phy-names: + minItems: 1 + maxItems: 8 + items: + enum: + - usb2-0 + - usb2-1 + - usb2-2 + - usb2-3 + - usb3-0 + - usb3-1 + - usb3-2 + - usb3-3 + + power-domains: + items: + - description: XUSBC power domain + - description: XUSBA power domain + + power-domain-names: + items: + - const: xusb_host + - const: xusb_ss + + dma-coherent: + type: boolean + +allOf: + - $ref: usb-xhci.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + + phys = <&pad_lanes_usb2_0>; + phy-names = "usb2-0"; + + }; From patchwork Fri Nov 11 10:14:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18647 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656399wru; Fri, 11 Nov 2022 02:19:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf6kVm4WnJptisAT+vjPAH8fII6SCUiucRJ5n4Jgge8ookoFKZW5JFHfAdWL+Pxa4bMVDgGY X-Received: by 2002:aa7:cdcd:0:b0:461:fdea:bb7d with SMTP id h13-20020aa7cdcd000000b00461fdeabb7dmr866343edw.203.1668161955945; Fri, 11 Nov 2022 02:19:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161955; cv=pass; d=google.com; s=arc-20160816; b=nUv8xIBtPRcyimYCy6LpaPUaZ0VVes+A8R+07gX4tBVjI3MjiiKB7dvAFjMszF89GU 7JYJQKYfalj+SsDVTv79dn1maGVkFEQ5R+wcHVSECxebouklVAcACY/fw8EHE9oVWZLK 6JrE8G7c6wdZ0KAxNPYu8/HcxJAvnkufx//RsoaAlMKHnYUkym71R+5CceFJksdDcGDT Q1jSm2SQH6WPEq5c4Cn60O/3jYm7B2lWZG4iKDEd1UirQRZ9Fiho6EtRjgG11R+S6qCr e5LH86b0mlls2DtRXtQYFWQTb8cmV5k1I6M0s2sYMGruJC9DsY9JoDhB058JH7Ty6YyV kQVg== ARC-Message-Signature: i=2; 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It is a standard I2C slave with GPIO input as IRQ interface. Signed-off-by: Wayne Chang --- V1 -> V2:Based on the review comments. Fix some addressed issues on description, interrupts, cypress,firmware-build, connector, and additionalProperties properties. And also remove the status in the example. .../bindings/usb/cypress,cypd4226.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml diff --git a/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml new file mode 100644 index 000000000000..70db97e0ad31 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cypress,cypd4226.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress cypd4226 UCSI I2C Type-C Controller + +maintainers: + - Wayne Chang + +description: + The Cypress cypd4226 UCSI I2C type-C controller is a I2C interface type-C + controller. + +properties: + compatible: + const: cypress,cypd4226 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 0x08 + + interrupts: + items: + - description: cypd4226 I2C interrupt + + cypress,firmware-build: + enum: + - nvidia,gpu + - nvidia,jetson-agx-xavier + description: | + the name of the CCGx firmware built for product series. + should be set one of following: + - "nvidia,gpu" for the NVIDIA RTX product series + - "nvidia,jetson-agx-xavier" for the NVIDIA Jetson product series + +patternProperties: + '^connector@[0-1]+$': + $ref: /schemas/connector/usb-connector.yaml# + properties: + reg: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <2>; + + ucsi-ccg@8 { + compatible = "cypress,cypd4226"; + interrupt-parent = <&gpio_aon>; + interrupts = ; + reg = <0x08>; + cypress,firmware-build = "nvidia,jetson-agx-xavier"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + port { + ucsi_ccg_p0: endpoint { + remote-endpoint = <&usb_role_switch0>; + }; + }; + }; + }; + }; From patchwork Fri Nov 11 10:15:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18646 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656390wru; Fri, 11 Nov 2022 02:19:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf58+XgAx4jdC+Hj/HRS4JWSPd/4cUknXJm+fVoQWsPjxxK3nHjqvkrqyp/8UeJ/1D62UIdh X-Received: by 2002:aa7:d3da:0:b0:460:9994:1b9b with SMTP id o26-20020aa7d3da000000b0046099941b9bmr841881edr.155.1668161951750; Fri, 11 Nov 2022 02:19:11 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161951; cv=pass; d=google.com; s=arc-20160816; b=N8mJw0zlqZazyGGlZHdkx3sRAGkNYJFd4bjYk+lu6zVgEbI/ae0ViNDj6V3cXpTjiw db1fBDtXCj2y6PwoZCscklie0+rvCiK4CmzqdQM96E4spAktb+4WE8uwsukkrr3Hw4u0 LJhAw+E0Rb9WDvQDL3ijHx+jwjJs1wGvg10SEguOcnxDjqn5+XiQmRE6i2KGeCFf1E94 y17w6kHjzrb/06KBx7iG4MqnTfElWA2qxShhOTyYewUeliM6Yn+XNcwTeYDqJ65p7iyN Fuu4Ua+yx3WJaJdIgvs8F/q/R/88zXfT+4VntywXHKwcCUnZWikNjTfG54MoOY8sIq+Y dsAw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bccZqGIdVeolneIXbEyHaMM9yMo+LF4Ai8UTW1oRA9k=; b=S75reo5PaGHoX1uSE+E2eSMZWMTtCGQfxXOh3rKgZE7xHuHiO/ZGGh5MqV5OswiTd8 uRqtkoh0h8gGGMNE+aEzqC4yqH4CMC/uLdah6mIniUi9jF2B7WRnwIOHkB0fYR0qBkQU vQ0Tt7Bo3+kXDecFr/JeibsBxnJ+3KMxxMeEFgaxB9hBS4G9kRFILorrWG7+7Jx2mZZL EBvdq/YCsC3++OmCwl7DHQ3WBFqWlrvnGEtjBzm7mW8AVBNes9ebZZJu4xvClq2r3iQR CRH0zwwt1LSO4V6V3PUouLY9GIVJPUpWXKZScl1p0fd3/6nC1OF0E1aq/9odJdUdBIJL xSzg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=LL5vSKP2; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:08.1886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 065eee53-733f-4f40-22cd-08dac3cdc000 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6050 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749194586585827759?= X-GMAIL-MSGID: =?utf-8?q?1749194586585827759?= This commit enables XUSB host, device, and pad controller on Jetson AGX Orin. Signed-off-by: Wayne Chang --- V1 -> V2:removed the redundant cells and status in ucsi-ccg. Using dash instead of underscore in the ucsi-ccg node name. Using representive name in cypress,firmware-build property. .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 48 +++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 175 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 170 +++++++++++++++++ 3 files changed, 393 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 9e4d72cfa69f..8acef87a5398 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -61,6 +61,29 @@ mmc@3460000 { non-removable; }; + padctl@3520000 { + vclamp-usb-supply = <&vdd_ao_1v8>; + avdd-usb-supply = <&vdd_ao_3v3>; + + ports { + usb2-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -69,4 +92,29 @@ pmc@c360000 { nvidia,invert-interrupt; }; }; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ao_1v8: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ao_3v3: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 57ab75328814..58baedbd0f93 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2011,6 +2011,181 @@ hda@3510000 { nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; }; + + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + status = "okay"; + }; + + usb2-1 { + status = "okay"; + }; + + usb2-2 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-1 { + status = "okay"; + }; + + usb3-2 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + usb-role-switch; + status = "okay"; + port { + hs_typec_p1: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p1>; + }; + }; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + port { + hs_typec_p0: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p0>; + }; + }; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + port { + ss_typec_p0: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p0>; + }; + }; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + port { + ss_typec_p1: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p1>; + }; + }; + }; + + usb3-2 { + nvidia,usb2-companion = <3>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-1"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; + + i2c@c240000 { + status = "okay"; + ucsi-ccg@8 { + compatible = "cypress,cypd4226"; + cypress,firmware-build = "nvidia,jetson-agx-xavier"; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0x08>; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "host"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ucsi_ccg_p0: endpoint { + remote-endpoint = <&hs_typec_p0>; + }; + }; + port@1 { + reg = <1>; + ss_ucsi_ccg_p0: endpoint { + remote-endpoint = <&ss_typec_p0>; + }; + }; + }; + ccg_typec_con1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "USB-C"; + data-role = "dual"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ucsi_ccg_p1: endpoint { + remote-endpoint = <&hs_typec_p1>; + }; + }; + port@1 { + reg = <1>; + ss_ucsi_ccg_p1: endpoint { + remote-endpoint = <&ss_typec_p1>; + }; + }; + }; + }; + }; }; chosen { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..27635d459e4c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -942,6 +942,174 @@ hda@3510000 { status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra234-xusb-padctl"; + reg = <0x03520000 0x20000>, + <0x03540000 0x10000>; + reg-names = "padctl", "ao"; + interrupts = ; + + resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3550000 { + compatible = "nvidia,tegra234-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x8000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; reg = <0x03810000 0x10000>; @@ -1470,6 +1638,8 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc240000 0x100>; interrupts = ; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C2 From patchwork Fri Nov 11 10:15:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18648 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656406wru; Fri, 11 Nov 2022 02:19:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf7hEB1YpeHRHH0VXGYnSjiHtcJDQvIbjpQAPZVwRXWSuvm/6Xu2s3bEaJOkULASmE3yE+6V X-Received: by 2002:a17:906:170c:b0:78d:3e56:52c with SMTP id c12-20020a170906170c00b0078d3e56052cmr1200960eje.732.1668161956445; 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Signed-off-by: Wayne Chang --- V1 -> V2: nothing has changed drivers/usb/typec/ucsi/ucsi_ccg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 835f1c4372ba..139707a2f3d6 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -643,7 +643,7 @@ static int ccg_request_irq(struct ucsi_ccg *uc) { unsigned long flags = IRQF_ONESHOT; - if (!has_acpi_companion(uc->dev)) + if (!dev_fwnode(uc->dev)) flags |= IRQF_TRIGGER_HIGH; return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc); @@ -1427,6 +1427,12 @@ static void ucsi_ccg_remove(struct i2c_client *client) free_irq(uc->irq, uc); } +static const struct of_device_id ucsi_ccg_of_match_table[] = { + { .compatible = "cypress,cypd4226", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ucsi_ccg_of_match_table); + static const struct i2c_device_id ucsi_ccg_device_id[] = { {"ccgx-ucsi", 0}, {} @@ -1481,6 +1487,7 @@ static struct i2c_driver ucsi_ccg_driver = { .pm = &ucsi_ccg_pm, .dev_groups = ucsi_ccg_groups, .acpi_match_table = amd_i2c_ucsi_match, + .of_match_table = ucsi_ccg_of_match_table, }, .probe = ucsi_ccg_probe, .remove = ucsi_ccg_remove, From patchwork Fri Nov 11 10:15:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18652 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656658wru; Fri, 11 Nov 2022 02:19:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf5XicSDpe9Vw/N4AHTDXP6B/SQv7ijisZlWRN9V4r+149/KeW6UAfGxV5gTbVKt0gVji7Vn X-Received: by 2002:aa7:cd83:0:b0:461:a7f8:c8c7 with SMTP id x3-20020aa7cd83000000b00461a7f8c8c7mr817706edv.325.1668161993185; Fri, 11 Nov 2022 02:19:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161993; cv=pass; d=google.com; s=arc-20160816; b=pc+hWKUJcfkd7QFNQuf+1hnszGs587+m3C1wuSyZdVSuMYaIsKLv6ahiXnZc+bNSAm lRfOzLcLhGLKg6IIdBpWoNzEHqUHC2ZoYruho6NHDSuu7oFSfXgXoRQ4zp8wc9M2+oIe 4HU4FhLpetza01ebSN1L3/F7niGGZ8m5qvOJehe6Gc4i7k2n58jTY6F/DbBXLidqnMS/ CBEyLtrHH5o7HPhRsA50HBagZxt4Z5O1fobspqjmYcc8YG08+tf1hfayX7ETg5ydd5gT F705nS+skrJuxXTpaxx8QhReDiHZ4XNus3lgC+O/vAXsXv8pCkF6oPwkbmS66w1Gv50o nXNg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f65T2XoEhiUfwf8HgFImqiGxkWSY66pNhbk64UYq/og=; b=njnNTCgqizULUXeE14jiQvL6cERRzgUE7lRe327TdJq+AnWPdy+AeqXHaTAdqWqpK+ caX0H3rsb5AXA5IPAcG6dkcthPGsFhuvExVTIhMAQyLu/iX+WX16ZUoH+o7tRMsChZi2 6XQH7iTfKBBK78barLJl7EV07hcmAXwt1KLH6V3KJ2cWa9gDcVjkfLj/ngkOc2PD2xuq T947jTXWdEwKfL2nqrJQKDGxBJGoDlFRaTDBzM4sWO0STTMry3fxGETArKVLAI3jgJVu DtkFVuLsb26z1XagJblwKefwmeuaMUMbXOP9IuNj+KMLR/ddQsDqmTZzRlo4TbAWX+CU 96og== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Z7JJhMqV; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Using string instead of u16 to make it more descriptive. Signed-off-by: Wayne Chang --- V1 -> V2:New change added for adding cypress,firmware-build drivers/usb/typec/ucsi/ucsi_ccg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 139707a2f3d6..e412a457bbfc 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -1343,6 +1343,7 @@ static int ucsi_ccg_probe(struct i2c_client *client, { struct device *dev = &client->dev; struct ucsi_ccg *uc; + const char *of_fw_build; int status; uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL); @@ -1363,6 +1364,17 @@ static int ucsi_ccg_probe(struct i2c_client *client, if (status) dev_err(uc->dev, "failed to get FW build information\n"); + status = device_property_read_string(dev, "cypress,firmware-build", + &of_fw_build); + if (!status) { + if (!strcmp(of_fw_build, "nvidia,jetson-agx-xavier")) + uc->fw_build = CCG_FW_BUILD_NVIDIA_TEGRA; + else if (!strcmp(of_fw_build, "nvidia,gpu")) + uc->fw_build = CCG_FW_BUILD_NVIDIA; + } else { + dev_err(uc->dev, "failed to get FW build information\n"); + } + /* reset ccg device and initialize ucsi */ status = ucsi_ccg_init(uc); if (status < 0) { From patchwork Fri Nov 11 10:15:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18650 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656475wru; Fri, 11 Nov 2022 02:19:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf7k2N/WLDeCAo97GbBvz3B3oFSQ3Vd3PxD5t7aynTB0h1Y1CejP/LHpYfumWJej7e7A4IVH X-Received: by 2002:a05:6402:651:b0:458:cc1b:a273 with SMTP id u17-20020a056402065100b00458cc1ba273mr908855edx.92.1668161966839; Fri, 11 Nov 2022 02:19:26 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161966; cv=pass; d=google.com; s=arc-20160816; b=0WCmTd3kpFUBByT8+LxRyjfz8WHfqzuEd6NZiwTzMTxxLF1cxHcR4PFfr34dUxeYha bBaNYDc43izJnn5ySitvAskYt/bgMbAi/BtDXNnQg7o74JmdGoWIN/plyOjtmXIrkhyZ g1Y+sn/Ibzk/0Zqh1UYS02FscMVS80DeJRQYUFPM64Bxu3rH2uuVlUnpJqZzKU3tow2U vJHYW/cVHBVB9Njg5aRmkM4XB9JqkQCHtc1ckSE7+NL47k+2hHwN8EZ5g/18bjOYYNTv qJSKxfLGC35TNHO5TptcdSf+L16fTodmm5BgWusuPjY9hXTVA+DFpoiJR1g7N9jlZv+5 I6QQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RoOtlFxOTztopXclAbiCCC5OWKvXUyqImo9xMJ1Tn0I=; b=JO0XqYi/iJgetoFBc6uZCyvRx164eGElKI0LlvuZ+N2vaDJW/VLC3WC28OZm5QkaT5 nS4jeicn5DJ206Ei60lkqb+Tq6JQnW6DurRHvDjsCIYHmx9agcdwedl8AZeAm10cSP6X 6dbDcifWu1MPwm8OG7GLftXyspD900VpW6n5sHvxBnDNopwaeCjDR6tJZLx8/2Fm+3tL /OUpgKNyFkPsqh3w6gi2HakOWq+mM8cLEsxv4aw+1O+nqZEKNiJjf+c/JxMtddfosnWE 43bz6xoGP5HYgDXl6qmLhnXZVIA4P6onw4Yw1fo8ZqXhf7eubkv+j7SUPPt88N1S8rKP 3RzA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=QMaXrSmZ; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:23.5678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15d6c6a5-dc93-46aa-cf65-08dac3cdc92a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7508 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749194602383099146?= X-GMAIL-MSGID: =?utf-8?q?1749194602383099146?= ccgx is refer to the cypress cypd4226 typec controller. add cypress,firmware-build as a well-known regex. 16-bit value is not sufficient for descriptiva names. Using string instead of u16 to make it more descriptive. Signed-off-by: Wayne Chang --- V1 -> V2:New change for adding cypress,firmware-build drivers/i2c/busses/i2c-nvidia-gpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 12e330cd7635..9b2e13bd44db 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -261,6 +261,7 @@ MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { /* Use FW built for NVIDIA (nv) only */ PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + PROPERTY_ENTRY_STRING("cypress,firmware-build", "nvidia,gpu"), { } }; From patchwork Fri Nov 11 10:15:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656544wru; Fri, 11 Nov 2022 02:19:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Id2+ifNmwPMWIAHTMcwM7xQ+fCPudxjnD9PqDvggAEZ9hWdKA+sB1FN96cFJR6Y4HPUSB X-Received: by 2002:a17:906:e0d4:b0:7ad:d1ab:2431 with SMTP id gl20-20020a170906e0d400b007add1ab2431mr1251921ejb.213.1668161978534; Fri, 11 Nov 2022 02:19:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161978; cv=pass; d=google.com; s=arc-20160816; b=eNOkW4si9mwzUWoDC+0R7rIXI4knKxb0Q7TRc0nCflMVBgd4toWSZIyRQdwruI+H0+ g8Xm/HYb/TWMX+CMwHZZoTDg68dw7pKR6ir3QlyROkLhT1/NtJsRFeYz0Ot/mr28/mgp taMVqjDKgSLJDYiijNEqlNwl+DRU0OP5AFDk34KB0bPtiX51uUclykvl54q4QY/vjI+w e7VwQzEim6pdWPDku1mh2pxllM9fw4oHKoaESDudgI3G8EX3w5Wn3n7qq7pSwOeKWenq e2vyM3pRQJ1yFtYkm3CkNQ/JinuGScmz08N3j5U6br8KG60SwAS3/+kWnzeFqkQTbU/P S5Kg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dyuhJf4hA5+wa/Xch0Rgl1g/1ZFnBQlyo1ICvJDb4yw=; b=umMv8tUurd/CSsWzeX+8i4au+cXnThOHqCVrIKSsLW5k5DPbP31kpEKG1asiRE6kAq vdD1n2MjTmjd60PUCUfoUFlq7O+S0h/uVjieYuII93RiS0u15PckK2Hhm3nZrl7GKdso WqMQE1xkJJGxIURaFovbWVmKYkEPm+O0TPcqASmtGDJtAlT6C+zvlywfhS/Iqp1CBnUn O0nGEoFDVoX3NqniX6wKRXOYsLOLqXCAsUtVnDYbOqzGEGk3FUxtCJ34BD08C6z6bvSE t483Seem1FTo6B3aEmE09a3ThcCrfuLVdtG/rXcVzjzRGijoqvzTaNjq77GZNjd57ti9 mkTw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=OFccsrSv; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Wayne Chang --- V1 -> V2:nothing has changed drivers/usb/typec/ucsi/ucsi_ccg.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index e412a457bbfc..eab3012e1b01 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -1359,11 +1359,6 @@ static int ucsi_ccg_probe(struct i2c_client *client, INIT_WORK(&uc->pm_work, ccg_pm_workaround_work); /* Only fail FW flashing when FW build information is not provided */ - status = device_property_read_u16(dev, "ccgx,firmware-build", - &uc->fw_build); - if (status) - dev_err(uc->dev, "failed to get FW build information\n"); - status = device_property_read_string(dev, "cypress,firmware-build", &of_fw_build); if (!status) { From patchwork Fri Nov 11 10:15:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18654 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656809wru; Fri, 11 Nov 2022 02:20:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf6VSs6//H4w3FOVrBb3oMr8AU/8/TUK3nyXFP+4ouK0KmbclL3oXNFK03msPxTkDqb1DznI X-Received: by 2002:a17:906:f196:b0:78d:6a9b:216c with SMTP id gs22-20020a170906f19600b0078d6a9b216cmr1288645ejb.602.1668162010929; Fri, 11 Nov 2022 02:20:10 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668162010; cv=pass; d=google.com; s=arc-20160816; b=HSUCHtse5RMCs8t13INjftgORJl1m+yhrwdlB4R6yCrkNpfrOQLCegyrWUcGoAfncE QWwjIMWXpi5spHJpOYDhPqnNE3ywpzwy+u6Bqv5Hg0i5TBzM6u8naISfvY1BpLa1vZvm ggsguNuviz4ikhbnviZiKG1EzDoXevkL05+Yj9+XNwaee/ZsLwvSb2YLyijm0wbyWVm5 8OTyYMYmLC0RWv8uqd5s5/SWkuwjwwSNWhp+LtOurHueOB9oWILKd89QuD6T/pdIKpKg Rwd9TFOLrcj93iM5KJC1gFkakZuy+Qe+m4xjPwXLY1ZwrLctsDgoN294IWtB5Rz0tJW7 +vpQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5Dq4DR6bfOpMwbvWEHPF6B2z8xaLv7LRMxg0PuSwa04=; b=GvWrjxxsxIppxuc3P6M0t6RtihMa40QmsxMCK/YsVXub6+D1a8A6yJIM7tRWyWdnfU 10RnmwLCaJqAWrM6V1bGggg28e4CjY3eADWYUcFtJDGe6biLyMsbE6O8QHOTHm1WAaFd D/CfWrHP1jbqQJqCjS1of4Ugh+X8JHqjYuEkaE1c1XFsHg7PtTk0ORFCYHHueH9QsZZm VFW0T2nxjaccIUPkbfUGpcWE4saO04S0SmXOLIYU27oyuTETNlCmBxT1nWDK4k72dmFy 5XgtcUZtjyI/vwLwE5yhPpZI+J/OD9/AjV1Ihhmb4NDLbJmZfzch+Vdyk+z2R4YrptFG YrqQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=gG+Ptxwr; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Wayne Chang --- V1 -> V2:New added for bisectablility drivers/i2c/busses/i2c-nvidia-gpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 9b2e13bd44db..092d4d52098c 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -259,8 +259,7 @@ static const struct pci_device_id gpu_i2c_ids[] = { MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { - /* Use FW built for NVIDIA (nv) only */ - PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + /* Use FW built for NVIDIA GPU only */ PROPERTY_ENTRY_STRING("cypress,firmware-build", "nvidia,gpu"), { } }; From patchwork Fri Nov 11 10:15:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18653 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656708wru; Fri, 11 Nov 2022 02:19:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf5zye3rOKyTr2LG4/E6ByXMicwP9/4UynPza2SjZiuDldxiUvjeG3M23lQhiDBsbE9LLwKI X-Received: by 2002:a05:6402:748:b0:461:9955:b54a with SMTP id p8-20020a056402074800b004619955b54amr864335edy.159.1668161999763; Fri, 11 Nov 2022 02:19:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668161999; cv=pass; d=google.com; s=arc-20160816; b=cOYGEj1/wtamJfcAZMgmV8c6rpLh3c8u7UV35awi7agKUCNZHiGaiHZPlTxm8sF8Oo dXHukgMZx/L1hMKfEyrgPJpCPAQn5Nagh6EiLUnZne+T2BBjuoAmiqM9AJAcYcEaPUsU TqjVxRIEz6Hl/oMpt96AGffoaobWriQEGxosTh1rDxMFxTpy+SD8eZBvsorEKqz+Sz2+ SEEXE4TXQadZzGcpqx5hNPvS+GBbk6FdwNa9iPGTQTclKsCMCIEBkX7fO198wQi6qCVh LrND7ZruK7rj7rpweKnKWoXHnQ+Q0EnwZVitYGtER6csc39Tb/XsFZ3a3opgzrK7riNm grgg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jVUquMvFCJAcgb8SUkNRtqEUj4zJ27FyVryF/sm5yPk=; b=pqsGA4+uYuzfB3tc+LnQ64aKQvzBEY7zl06ctxkgYptBXsAEIXY8smeN9S+M7JmHLS GJXNZqqOVVr/7YAWwHOdwWhQUTlb0o9k2c0s83ily4UhdYsG7R3wAbtqMZ/ZXr1pZqmO qPQnxfMe5QHZyUrafNTRZS1QHjdsbA2ajjrFu4vFV9ww3m77S1donE0/ab5+jMDz27qa gciVhQ6ydxpA7RcCkC15r2QW7dfwIdUVI5/l4GH09N7bNYm/7A7frH85jwS1pozPxnCH YnHOlW/a8JUbXYVEppIBp61grJWlCzJdmo9DtAtkBlFwxItPb++BFnXrBgoZaBh/L4Qj WJpw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="QeuHHhZ/"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Clk should be disabled after calibration. Disable clk after calibration. While at it add 100us delay for HW recording the calibration value. Signed-off-by: Wayne Chang --- V1 -> V2: update the commit message. drivers/phy/tegra/xusb-tegra186.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 0996ede63387..f121b4ffbbfd 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -609,6 +609,10 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + udelay(100); + + clk_disable_unprepare(priv->usb2_trk_clk); + mutex_unlock(&padctl->lock); } @@ -633,8 +637,6 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - clk_disable_unprepare(priv->usb2_trk_clk); - mutex_unlock(&padctl->lock); } From patchwork Fri Nov 11 10:15:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18655 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656854wru; Fri, 11 Nov 2022 02:20:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf6+6hxKsQ7kXNsomNqr5I6/9VYoh7k7jRZpWwro7NvqTBpdz0KYWjnKh8k0SwLONOG8fim1 X-Received: by 2002:a05:6402:17d0:b0:458:d064:a8c2 with SMTP id s16-20020a05640217d000b00458d064a8c2mr834506edy.346.1668162017430; Fri, 11 Nov 2022 02:20:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668162017; cv=pass; d=google.com; s=arc-20160816; b=GTlEJ+h1MwFPOdiW4FpOQY2zkltyn14KVvE2LM8vV0Fpo0HkcOP8lc++qBsjMu5fJz TCctGNaah+VHBNQ5koOSPYnEzei9Fn5n9S5OE69ylPKQlMNEfKAuBEIZzmzuNRsJmM+r CiZeTTXnh/bt84G0JJgm8ndO3p3A7YTedSp6kWwC5U0fEOVz0xLZTDXJp3rszYcYwCGF yZIcrJTWsMGxwixK3tkeqjilVcv29GOqPD8B/hYahZbOgE7Ifpng7KZ13UwejUai+rej i4D4oLQ+qOGTkujGpFWx7wtwezqFjlEd1YyB6FqrcfbFRkrcSil5kpoTOlHKgdyKbM8D oLAw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1AF7aVigZwouxWVql2MnK0MSpcIZN0ezQ3PFXN5glmg=; b=ApPUpqa8qhfdcRI7u+dJdEvXTq207WsjF5Ds1FP+CzkcPVHWKkduO5OhQOwHZb9OEV S2N8ZVh02kodjdODv1L1DhmJAbPMsIzOjAg025cUdFwxfAePgZIeDE/qaMTkwh+uM3do BpgQEIQgTuDtM1t8wa3SGW1xeAdM+iIIF6+U7vNyjLDc7bDfLDsT1bqeh9JVXD992MjW Zgt4ZTr1e30KbUhnJ9inap6Ans+vXHOaSDmQUIA+kv5FHwbLHJCqlV6ymtPMfOfpSjcz wHXYUBZle3V4e8QpzhwZ9+Y85TKriVW3EC7kCba2vzejG5H7RXLL8ODBcWkHs2QhD2X9 Gh1w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="rtb6k3/0"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:38.9114 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2913a553-fb5e-4d59-106b-08dac3cdd250 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5195 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749194655709498448?= X-GMAIL-MSGID: =?utf-8?q?1749194655709498448?= From: Sing-Han Chen Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- V1 -> V2:remove atomic and the helper in padctl_readl_poll func. drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 64 +++++++++++++++++++++++++++++-- drivers/phy/tegra/xusb.c | 6 +++ drivers/phy/tegra/xusb.h | 22 +++++++++++ 4 files changed, 90 insertions(+), 3 deletions(-) diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 89b84067cb4c..eeeea72de117 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -7,4 +7,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index f121b4ffbbfd..5ae3cea19c84 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -89,6 +89,11 @@ #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) #define USB2_PD_TRK BIT(26) +#define USB2_TRK_COMPLETED BIT(31) + +#define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c +#define USB2_TRK_HW_MODE BIT(0) +#define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31) #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) #define HSIC_PD_TX_DATA0 BIT(1) @@ -609,9 +614,31 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - udelay(100); + if (padctl->soc->poll_trk_completed) { + err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, + USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100); + if (err) { + /* The failure with polling on trk complete will not + * cause the failure of powering on the bias pad. + */ + dev_warn(dev, "failed to poll USB2 trk completed: %d\n", err); + } - clk_disable_unprepare(priv->usb2_trk_clk); + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value |= USB2_TRK_COMPLETED; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + } else { + udelay(100); + } + + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value |= USB2_TRK_HW_MODE; + value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + } else { + clk_disable_unprepare(priv->usb2_trk_clk); + } mutex_unlock(&padctl->lock); } @@ -637,6 +664,13 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value &= ~USB2_TRK_HW_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + clk_disable_unprepare(priv->usb2_trk_clk); + } + mutex_unlock(&padctl->lock); } @@ -1560,7 +1594,8 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); #endif -#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) +#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) static const char * const tegra194_xusb_padctl_supply_names[] = { "avdd-usb", "vclamp-usb", @@ -1616,8 +1651,31 @@ const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { .supply_names = tegra194_xusb_padctl_supply_names, .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), .supports_gen2 = true, + .poll_trk_completed = true, }; EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc); + +const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = { + .num_pads = ARRAY_SIZE(tegra194_pads), + .pads = tegra194_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 4, + }, + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 4, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra194_xusb_padctl_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), + .supports_gen2 = true, + .poll_trk_completed = true, + .trk_hw_mode = true, +}; +EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); #endif MODULE_AUTHOR("JC Kuo "); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 95091876c422..23d179b1a5b5 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -71,6 +71,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra194-xusb-padctl", .data = &tegra194_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + { + .compatible = "nvidia,tegra234-xusb-padctl", + .data = &tegra234_xusb_padctl_soc, + }, #endif { } }; diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 8cfbbdbd6e0c..a21826c730d7 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -8,6 +8,7 @@ #define __PHY_TEGRA_XUSB_H #include +#include #include #include @@ -433,6 +434,8 @@ struct tegra_xusb_padctl_soc { unsigned int num_supplies; bool supports_gen2; bool need_fake_usb3_port; + bool poll_trk_completed; + bool trk_hw_mode; }; struct tegra_xusb_padctl { @@ -475,6 +478,22 @@ static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, return value; } +static inline u32 padctl_readl_poll(struct tegra_xusb_padctl *padctl, + unsigned long offset, u32 val, u32 mask, int us) +{ + u32 regval; + int err; + + err = readl_poll_timeout(padctl->regs + offset, regval, + (regval & mask) == val, 1, us); + if (err) { + dev_err(padctl->dev, "%08lx poll timeout > %08x\n", offset, + regval); + } + + return err; +} + struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl, const char *name, unsigned int index); @@ -491,5 +510,8 @@ extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc; #if defined(CONFIG_ARCH_TEGRA_194_SOC) extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) +extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */ From patchwork Fri Nov 11 10:15:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 18656 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp656858wru; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:50.2977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fede80a5-347b-4f3b-03b3-08dac3cdd923 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4471 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749194655836895040?= X-GMAIL-MSGID: =?utf-8?q?1749194655836895040?= From: Sing-Han Chen This change adds Tegra234 XUSB host mode controller support. In Tegra234, some of the registers have moved to bar2 space. The new soc variable has_bar2 indicates the chip with bar2 area. This patch adds new reg helper to let the driver reuse the same code for those chips with bar2 support. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- V1 -> V2:fix some issues on coding style extract tegra_xusb_load_firmware function refine has_bar2 and remove has_ifr/firmware on Tegra234 drivers/usb/host/xhci-tegra.c | 270 +++++++++++++++++++++++++++++----- 1 file changed, 232 insertions(+), 38 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index bdb776553826..b2f07eae2c93 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -44,6 +44,9 @@ #define XUSB_CFG_4 0x010 #define XUSB_BASE_ADDR_SHIFT 15 #define XUSB_BASE_ADDR_MASK 0x1ffff +#define XUSB_CFG_7 0x01c +#define XUSB_BASE2_ADDR_SHIFT 16 +#define XUSB_BASE2_ADDR_MASK 0xffff #define XUSB_CFG_16 0x040 #define XUSB_CFG_24 0x060 #define XUSB_CFG_AXI_CFG 0x0f8 @@ -75,6 +78,20 @@ #define MBOX_SMI_INTR_FW_HANG BIT(1) #define MBOX_SMI_INTR_EN BIT(3) +/* BAR2 registers */ +#define XUSB_BAR2_ARU_MBOX_CMD 0x004 +#define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 +#define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c +#define XUSB_BAR2_ARU_MBOX_OWNER 0x010 +#define XUSB_BAR2_ARU_SMI_INTR 0x014 +#define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c +#define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 +#define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 +#define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 +#define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c +#define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 +#define XUSB_BAR2_CSB_BASE_ADDR 0x2000 + /* IPFS registers */ #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 @@ -111,6 +128,9 @@ #define IMFILLRNG1_TAG_HI_SHIFT 16 #define XUSB_FALC_IMFILLCTL 0x158 +/* CSB ARU registers */ +#define XUSB_CSB_ARU_SCRATCH0 0x100100 + /* MP CSB registers */ #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 @@ -131,6 +151,9 @@ #define IMEM_BLOCK_SIZE 256 +#define FW_IOCTL_TYPE_SHIFT 24 +#define FW_IOCTL_CFGTBL_READ 17 + struct tegra_xusb_fw_header { __le32 boot_loadaddr_in_imem; __le32 boot_codedfi_offset; @@ -175,6 +198,7 @@ struct tegra_xusb_mbox_regs { u16 data_in; u16 data_out; u16 owner; + u16 smi_intr; }; struct tegra_xusb_context_soc { @@ -189,6 +213,18 @@ struct tegra_xusb_context_soc { } fpci; }; +struct tegra_xusb; +struct tegra_xusb_soc_ops { + u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*mbox_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); + u32 (*csb_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*csb_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); +}; + struct tegra_xusb_soc { const char *firmware; const char * const *supply_names; @@ -205,11 +241,14 @@ struct tegra_xusb_soc { } ports; struct tegra_xusb_mbox_regs mbox; + const struct tegra_xusb_soc_ops *ops; bool scale_ss_clock; bool has_ipfs; bool lpm_support; bool otg_reset_sspi; + + bool has_bar2; }; struct tegra_xusb_context { @@ -230,6 +269,8 @@ struct tegra_xusb { void __iomem *ipfs_base; void __iomem *fpci_base; + void __iomem *bar2_base; + struct resource *bar2; const struct tegra_xusb_soc *soc; @@ -300,7 +341,33 @@ static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, writel(value, tegra->ipfs_base + offset); } +static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + return readl(tegra->bar2_base + offset); +} + +static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + writel(value, tegra->bar2_base + offset); +} + static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + return ops->csb_reg_readl(tegra, offset); +} + +static void csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + ops->csb_reg_writel(tegra, value, offset); +} + +static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); u32 ofs = CSB_PAGE_OFFSET(offset); @@ -310,7 +377,7 @@ static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); } -static void csb_writel(struct tegra_xusb *tegra, u32 value, +static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); @@ -320,6 +387,26 @@ static void csb_writel(struct tegra_xusb *tegra, u32 value, fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); } +static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + + return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + +static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, unsigned long rate) { @@ -451,6 +538,7 @@ static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, const struct tegra_xusb_mbox_msg *msg) { + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; bool wait_for_idle = false; u32 value; @@ -459,15 +547,15 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, * ACK/NAK messages. */ if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) { dev_err(tegra->dev, "mailbox is busy\n"); return -EBUSY; } - fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_SW) { dev_err(tegra->dev, "failed to acquire mailbox\n"); return -EBUSY; @@ -477,17 +565,17 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } value = tegra_xusb_mbox_pack(msg); - fpci_writel(tegra, value, tegra->soc->mbox.data_in); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value |= MBOX_INT_EN | MBOX_DEST_FALC; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); if (wait_for_idle) { unsigned long timeout = jiffies + msecs_to_jiffies(250); while (time_before(jiffies, timeout)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value == MBOX_OWNER_NONE) break; @@ -495,7 +583,7 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } if (time_after(jiffies, timeout)) - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) return -ETIMEDOUT; @@ -507,11 +595,12 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) { struct tegra_xusb *tegra = data; + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; u32 value; /* clear mailbox interrupts */ - value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); - fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); if (value & MBOX_SMI_INTR_FW_HANG) dev_err(tegra->dev, "controller firmware hang\n"); @@ -664,6 +753,7 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) { struct tegra_xusb *tegra = data; + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; struct tegra_xusb_mbox_msg msg; u32 value; @@ -672,16 +762,16 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) if (pm_runtime_suspended(tegra->dev) || tegra->suspended) goto out; - value = fpci_readl(tegra, tegra->soc->mbox.data_out); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); tegra_xusb_mbox_unpack(&msg, value); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value &= ~MBOX_DEST_SMI; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); /* clear mailbox owner if no ACK/NAK is required */ if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) - fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); tegra_xusb_mbox_handle(tegra, &msg); @@ -709,6 +799,15 @@ static void tegra_xusb_config(struct tegra_xusb *tegra) value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); fpci_writel(tegra, value, XUSB_CFG_4); + /* Program BAR2 space */ + if (tegra->bar2) { + value = fpci_readl(tegra, XUSB_CFG_7); + value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + value |= tegra->bar2->start & + (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + fpci_writel(tegra, value, XUSB_CFG_7); + } + usleep_range(100, 200); /* Enable bus master */ @@ -881,21 +980,36 @@ static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) return 0; } -static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) +static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) +{ + struct xhci_cap_regs __iomem *cap_regs; + struct xhci_op_regs __iomem *op_regs; + int ret; + u32 value; + + cap_regs = tegra->regs; + op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); + + ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000); + + if (ret) + dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", + csb_readl(tegra, XUSB_FALC_CPUCTL)); + + return ret; +} + +static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra) { unsigned int code_tag_blocks, code_size_blocks, code_blocks; - struct xhci_cap_regs __iomem *cap = tegra->regs; struct tegra_xusb_fw_header *header; struct device *dev = tegra->dev; - struct xhci_op_regs __iomem *op; - unsigned long timeout; time64_t timestamp; u64 address; u32 value; int err; header = (struct tegra_xusb_fw_header *)tegra->fw.virt; - op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase)); if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { dev_info(dev, "Firmware already loaded, Falcon state %#x\n", @@ -968,30 +1082,55 @@ static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); - timeout = jiffies + msecs_to_jiffies(200); + if (tegra_xusb_wait_for_falcon(tegra)) + return -EIO; + + timestamp = le32_to_cpu(header->fwimg_created_time); - do { - value = readl(&op->status); - if ((value & STS_CNR) == 0) - break; + dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + + return 0; +} + +static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset) +{ + /* + * We only accept reading the firmware config table + * The offset should not exceed the fw header structure + */ + if (offset >= sizeof(struct tegra_xusb_fw_header)) + return 0; - usleep_range(1000, 2000); - } while (time_is_after_jiffies(timeout)); + bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, + XUSB_BAR2_ARU_FW_SCRATCH); + return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); +} + +static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) +{ + time64_t timestamp; - value = readl(&op->status); - if (value & STS_CNR) { - value = csb_readl(tegra, XUSB_FALC_CPUCTL); - dev_err(dev, "XHCI controller not read: %#010x\n", value); + if (tegra_xusb_wait_for_falcon(tegra)) return -EIO; - } - timestamp = le32_to_cpu(header->fwimg_created_time); +#define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) + timestamp = tegra_xusb_read_firmware_header(tegra, + offsetof_32(struct tegra_xusb_fw_header, + fwimg_created_time) << 2); - dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); return 0; } +static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) +{ + if (!tegra->soc->firmware) + return tegra_xusb_init_ifr_firmware(tegra); + else + return tegra_xusb_load_firmware_rom(tegra); +} + static void tegra_xusb_powerdomain_remove(struct device *dev, struct tegra_xusb *tegra) { @@ -1435,6 +1574,10 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); if (IS_ERR(tegra->ipfs_base)) return PTR_ERR(tegra->ipfs_base); + } else if (tegra->soc->has_bar2) { + tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2); + if (IS_ERR(tegra->bar2_base)) + return PTR_ERR(tegra->bar2_base); } tegra->xhci_irq = platform_get_irq(pdev, 0); @@ -1651,10 +1794,13 @@ static int tegra_xusb_probe(struct platform_device *pdev) goto disable_phy; } - err = tegra_xusb_request_firmware(tegra); - if (err < 0) { - dev_err(&pdev->dev, "failed to request firmware: %d\n", err); - goto disable_phy; + if (tegra->soc->firmware) { + err = tegra_xusb_request_firmware(tegra); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request firmware: %d\n", err); + goto disable_phy; + } } err = tegra_xusb_unpowergate_partitions(tegra); @@ -2271,6 +2417,13 @@ static const struct tegra_xusb_context_soc tegra124_xusb_context = { }, }; +static const struct tegra_xusb_soc_ops tegra124_ops = { + .mbox_reg_readl = &fpci_readl, + .mbox_reg_writel = &fpci_writel, + .csb_reg_readl = &fpci_csb_readl, + .csb_reg_writel = &fpci_csb_writel, +}; + static const struct tegra_xusb_soc tegra124_soc = { .firmware = "nvidia/tegra124/xusb.bin", .supply_names = tegra124_supply_names, @@ -2286,11 +2439,13 @@ static const struct tegra_xusb_soc tegra124_soc = { .scale_ss_clock = true, .has_ipfs = true, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); @@ -2322,11 +2477,13 @@ static const struct tegra_xusb_soc tegra210_soc = { .scale_ss_clock = false, .has_ipfs = true, .otg_reset_sspi = true, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); @@ -2363,11 +2520,13 @@ static const struct tegra_xusb_soc tegra186_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; @@ -2394,21 +2553,56 @@ static const struct tegra_xusb_soc tegra194_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0x68, .data_in = 0x6c, .data_out = 0x70, .owner = 0x74, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); +static const struct tegra_xusb_soc_ops tegra234_ops = { + .mbox_reg_readl = &bar2_readl, + .mbox_reg_writel = &bar2_writel, + .csb_reg_readl = &bar2_csb_readl, + .csb_reg_writel = &bar2_csb_writel, +}; + +static const struct tegra_xusb_soc tegra234_soc = { + .supply_names = tegra194_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_supply_names), + .phy_types = tegra194_phy_types, + .num_types = ARRAY_SIZE(tegra194_phy_types), + .context = &tegra186_xusb_context, + .ports = { + .usb3 = { .offset = 0, .count = 4, }, + .usb2 = { .offset = 4, .count = 4, }, + }, + .scale_ss_clock = false, + .has_ipfs = false, + .otg_reset_sspi = false, + .ops = &tegra234_ops, + .mbox = { + .cmd = XUSB_BAR2_ARU_MBOX_CMD, + .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, + .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, + .owner = XUSB_BAR2_ARU_MBOX_OWNER, + .smi_intr = XUSB_BAR2_ARU_SMI_INTR, + }, + .lpm_support = true, + .has_bar2 = true, +}; + static const struct of_device_id tegra_xusb_of_match[] = { { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, + { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc }, { }, }; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:51.8422 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8527019-35b7-4fd4-4b2f-08dac3cdda0c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5125 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749194656765079757?= X-GMAIL-MSGID: =?utf-8?q?1749194656765079757?= From: Sing-Han Chen This commit adds support for XUSB device mode controller support on Tegra234 SoC. This is very similar to the existing Tegra194 XUDC. Signed-off-by: Sing-Han Chen Signed-off-by: Wayne Chang --- V1 -> V2:Nothing has changed drivers/usb/gadget/udc/tegra-xudc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 76919d7570d2..ff697190469b 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -3660,6 +3660,19 @@ static struct tegra_xudc_soc tegra194_xudc_soc_data = { .has_ipfs = false, }; +static struct tegra_xudc_soc tegra234_xudc_soc_data = { + .clock_names = tegra186_xudc_clock_names, + .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), + .num_phys = 4, + .u1_enable = true, + .u2_enable = true, + .lpm_enable = true, + .invalid_seq_num = false, + .pls_quirk = false, + .port_reset_quirk = false, + .has_ipfs = false, +}; + static const struct of_device_id tegra_xudc_of_match[] = { { .compatible = "nvidia,tegra210-xudc", @@ -3673,6 +3686,10 @@ static const struct of_device_id tegra_xudc_of_match[] = { .compatible = "nvidia,tegra194-xudc", .data = &tegra194_xudc_soc_data }, + { + .compatible = "nvidia,tegra234-xudc", + .data = &tegra234_xudc_soc_data + }, { } }; MODULE_DEVICE_TABLE(of, tegra_xudc_of_match);