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Thu, 14 Dec 2023 11:42:48 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3BEBghuX003051; Thu, 14 Dec 2023 11:42:43 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3uvhaktcgf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 11:42:43 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3BEBghQJ002911; Thu, 14 Dec 2023 11:42:43 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3BEBghwb002830 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 11:42:43 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 838C34127D; Thu, 14 Dec 2023 17:12:42 +0530 (+0530) From: Md Sadre Alam To: thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, quic_srichara@quicinc.com, quic_varada@quicinc.com Cc: quic_mdalam@quicinc.com Subject: [PATCH 01/11] crypto: qce - Add support for crypto address read Date: Thu, 14 Dec 2023 17:12:29 +0530 Message-Id: <20231214114239.2635325-2-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214114239.2635325-1-quic_mdalam@quicinc.com> References: <20231214114239.2635325-1-quic_mdalam@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dm_cbDhlAO8voiFCninNWp50cObObTB4 X-Proofpoint-GUID: dm_cbDhlAO8voiFCninNWp50cObObTB4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140080 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 14 Dec 2023 03:43:30 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257489800550169 X-GMAIL-MSGID: 1785257489800550169 Get crypto base address from DT. This will use for command descriptor support for crypto register r/w via BAM/DMA Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/core.c | 9 +++++++++ drivers/crypto/qce/core.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 28b5fd823827..5af0dc40738a 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -192,6 +192,7 @@ static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qce_device *qce; + struct resource *res; int ret; qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); @@ -205,6 +206,14 @@ static int qce_crypto_probe(struct platform_device *pdev) if (IS_ERR(qce->base)) return PTR_ERR(qce->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + qce->base_dma = dma_map_resource(dev, res->start, resource_size(res), + DMA_BIDIRECTIONAL, 0); + if (dma_mapping_error(dev, qce->base_dma)) + return -ENXIO; + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret < 0) return ret; diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 228fcd69ec51..25e2af45c047 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -39,6 +39,7 @@ struct qce_device { struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; + dma_addr_t base_dma; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); From patchwork Thu Dec 14 11:42:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178684 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478819dys; Thu, 14 Dec 2023 03:43:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IEgc/NIi0oNIRcHictfxi4ng/d8BQuEYYhovgzVBAho9ZRGlJMfVWhO1B9yj9WrAzSVXmBO X-Received: by 2002:a05:6870:7d19:b0:203:234e:9bb5 with SMTP id os25-20020a0568707d1900b00203234e9bb5mr3474112oab.38.1702554215139; Thu, 14 Dec 2023 03:43:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554215; cv=none; d=google.com; s=arc-20160816; b=f9B9lF+vBDU0T/wmt/YL8C3fFFjj4j99sbugz6Ldffmv6bSQTx5X/r0x3J4xt8suAQ jS1s+ItroPCAi2XIIdZfl8HhaJAfzBAB+P2dk9ICD5CY+4G/6YxJhVDtVasucekjx2u3 E6l4bn1lebq5uQsdERIlxDek5pEhyWWCyUy6uqezvsEb+H+SQnOKhbLUXza20JKd9dJK 3qWQwzWHcyUWMI3zRgWsUl30ObOL3qAwHTQKOTRneOkfoghVcSIUtpG6N0u3MBWbJsxd 5W5qOQI8Z2/+HYr0fuOwWbo/W1sDz9c2jMEEF8OzA1rQpah0lK3p9cUlX+Df7VBAd3L4 d+qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zqxmqhOkW3xBad0olqFsFOy8DGPOAi52HW52FVOr2pA=; fh=TEn06IatapHMgkFhNRCYXHrnqycBlFaJECTG22CvvEc=; b=nFExBE+0x+4fo6X1ZL8EJPiLVywH8gCC+tm3WCzP7UprUOEYbFOxhJlaWUMafqgi2Q wyjgqtZOuJrqwJuW11kdzlOy5ojuebAjAId/j956ouEB6gqcwWyxWVs8phsRgxVzefFZ 7A81/dlhIWOHhBqq6R8Gsw/bsNKlHbUXQwaH5weKCN20JBQCVIwjGPVdUDpzFZkvBAvH 9CZ7i8r09g/2fym0yv6dfmSzmkFla2fct6Q4CAZhxDFJP+b0F+StQDFcy+Ex9Ni71sP7 zgfa4sZC3/HdMHATT3bf2Ez6PwzLf+G6PGvw1gSatjSWSlzSpYkF+IdV7trcVVEhNWcV pU2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=oKaDCRHu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Thu, 14 Dec 2023 03:43:24 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257488872948556 X-GMAIL-MSGID: 1785257488872948556 Add BAM/DMA support for crypto register read/write. With this change multiple crypto register will get Written using bam in one go. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/core.h | 9 ++ drivers/crypto/qce/dma.c | 233 ++++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/dma.h | 24 +++- 3 files changed, 265 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 25e2af45c047..bf28dedd1509 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -40,6 +40,8 @@ struct qce_device { int burst_size; unsigned int pipe_pair_id; dma_addr_t base_dma; + __le32 *reg_read_buf; + dma_addr_t reg_buf_phys; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); @@ -59,4 +61,11 @@ struct qce_algo_ops { int (*async_req_handle)(struct crypto_async_request *async_req); }; +int qce_write_reg_dma(struct qce_device *qce, unsigned int offset, u32 val, + int cnt); +int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, + int cnt); +void qce_clear_bam_transaction(struct qce_device *qce); +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); +struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); #endif /* _CORE_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 46db5bf366b4..85c8d4107afa 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -4,12 +4,220 @@ */ #include +#include #include #include "dma.h" +#include "core.h" + +#define QCE_REG_BUF_DMA_ADDR(qce, vaddr) \ + ((qce)->reg_buf_phys + \ + ((uint8_t *)(vaddr) - (uint8_t *)(qce)->reg_read_buf)) + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + + qce_bam_txn->qce_bam_ce_index = 0; + qce_bam_txn->qce_write_sgl_cnt = 0; + qce_bam_txn->qce_read_sgl_cnt = 0; + qce_bam_txn->qce_bam_ce_index = 0; + qce_bam_txn->qce_pre_bam_ce_index = 0; +} + +static int qce_dma_prep_cmd_sg(struct qce_device *qce, struct dma_chan *chan, + struct scatterlist *qce_bam_sgl, + int qce_sgl_cnt, unsigned long flags, + enum dma_transfer_direction dir, + dma_async_tx_callback cb, void *cb_param) +{ + struct dma_async_tx_descriptor *dma_desc; + struct qce_desc_info *desc; + dma_cookie_t cookie; + + desc = qce->dma.qce_bam_txn->qce_desc; + + if (!qce_bam_sgl || !qce_sgl_cnt) + return -EINVAL; + + if (!dma_map_sg(qce->dev, qce_bam_sgl, + qce_sgl_cnt, dir)) { + dev_err(qce->dev, "failure in mapping sgl for cmd desc\n"); + return -ENOMEM; + } + + dma_desc = dmaengine_prep_slave_sg(chan, qce_bam_sgl, qce_sgl_cnt, + dir, flags); + if (!dma_desc) { + pr_err("%s:failure in prep cmd desc\n", __func__); + dma_unmap_sg(qce->dev, qce_bam_sgl, qce_sgl_cnt, dir); + kfree(desc); + return -EINVAL; + } + + desc->dma_desc = dma_desc; + desc->dma_desc->callback = cb; + desc->dma_desc->callback_param = cb_param; + + cookie = dmaengine_submit(desc->dma_desc); + + return dma_submit_error(cookie); +} + +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + struct dma_chan *chan = qce->dma.rxchan; + unsigned long desc_flags; + int ret = 0; + + desc_flags = DMA_PREP_CMD; + + /* For command descriptor always use consumer pipe + * it recomended as per HPG + */ + + if (qce_bam_txn->qce_read_sgl_cnt) { + ret = qce_dma_prep_cmd_sg(qce, chan, + qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + desc_flags, DMA_DEV_TO_MEM, + NULL, NULL); + if (ret) { + pr_err("error while submiting cmd desc for rx\n"); + return ret; + } + } + + if (qce_bam_txn->qce_write_sgl_cnt) { + ret = qce_dma_prep_cmd_sg(qce, chan, + qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + desc_flags, DMA_MEM_TO_DEV, + NULL, NULL); + } + + if (ret) { + pr_err("error while submiting cmd desc for tx\n"); + return ret; + } + + qce_dma_issue_pending(&qce->dma); + + return ret; +} + +static void qce_prep_dma_command_desc(struct qce_device *qce, + struct qce_dma_data *dma, bool read, unsigned int addr, + void *buff, int size) +{ + struct qce_bam_transaction *qce_bam_txn = dma->qce_bam_txn; + struct bam_cmd_element *qce_bam_ce_buffer; + int qce_bam_ce_size, cnt, index; + + index = qce_bam_txn->qce_bam_ce_index; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce[index]; + if (read) + bam_prep_ce(qce_bam_ce_buffer, addr, BAM_READ_COMMAND, + QCE_REG_BUF_DMA_ADDR(qce, + (unsigned int *)buff)); + else + bam_prep_ce_le32(qce_bam_ce_buffer, addr, BAM_WRITE_COMMAND, + *((__le32 *)buff)); + + if (read) { + cnt = qce_bam_txn->qce_read_sgl_cnt; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce + [qce_bam_txn->qce_pre_bam_ce_index]; + qce_bam_txn->qce_bam_ce_index += size; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_read_sgl[cnt], + qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_read_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = + qce_bam_txn->qce_bam_ce_index; + } else { + cnt = qce_bam_txn->qce_write_sgl_cnt; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce + [qce_bam_txn->qce_pre_bam_ce_index]; + qce_bam_txn->qce_bam_ce_index += size; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_write_sgl[cnt], + qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_write_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = + qce_bam_txn->qce_bam_ce_index; + } +} + +int qce_write_reg_dma(struct qce_device *qce, + unsigned int offset, u32 val, int cnt) +{ + void *buff; + unsigned int reg_addr; + + buff = &val; + + reg_addr = ((unsigned int)(qce->base_dma) + offset); + qce_prep_dma_command_desc(qce, &qce->dma, false, reg_addr, buff, cnt); + + return 0; +} + +int qce_read_reg_dma(struct qce_device *qce, + unsigned int offset, void *buff, int cnt) +{ + void *vaddr; + unsigned int reg_addr; + + reg_addr = ((unsigned int)(qce->base_dma) + offset); + vaddr = qce->reg_read_buf; + + qce_prep_dma_command_desc(qce, &qce->dma, true, reg_addr, vaddr, cnt); + memcpy(buff, vaddr, 4); + + return 0; +} + +struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma) +{ + struct qce_bam_transaction *qce_bam_txn; + + dma->qce_bam_txn = kmalloc(sizeof(*qce_bam_txn), GFP_KERNEL); + if (!dma->qce_bam_txn) + return NULL; + + dma->qce_bam_txn->qce_desc = kzalloc(sizeof(struct qce_desc_info), + GFP_KERNEL); + if (!dma->qce_bam_txn->qce_desc) { + kfree(dma->qce_bam_txn); + return NULL; + } + + sg_init_table(dma->qce_bam_txn->qce_reg_write_sgl, + QCE_BAM_CMD_SGL_SIZE); + + sg_init_table(dma->qce_bam_txn->qce_reg_read_sgl, + QCE_BAM_CMD_SGL_SIZE); + + qce_bam_txn = dma->qce_bam_txn; + + return qce_bam_txn; +} int qce_dma_request(struct device *dev, struct qce_dma_data *dma) { + struct qce_device *qce = container_of(dma, struct qce_device, dma); int ret; dma->txchan = dma_request_chan(dev, "tx"); @@ -31,6 +239,21 @@ int qce_dma_request(struct device *dev, struct qce_dma_data *dma) dma->ignore_buf = dma->result_buf + QCE_RESULT_BUF_SZ; + dma->qce_bam_txn = qce_alloc_bam_txn(dma); + if (!dma->qce_bam_txn) { + pr_err("Failed to allocate bam transaction\n"); + return -ENOMEM; + } + + qce->reg_read_buf = dmam_alloc_coherent(qce->dev, + QCE_MAX_REG_READ * + sizeof(*qce->reg_read_buf), + &qce->reg_buf_phys, GFP_KERNEL); + if (!qce->reg_read_buf) { + pr_err("Failed to allocate reg_read_buf\n"); + return -ENOMEM; + } + return 0; error_nomem: dma_release_channel(dma->rxchan); @@ -41,9 +264,19 @@ int qce_dma_request(struct device *dev, struct qce_dma_data *dma) void qce_dma_release(struct qce_dma_data *dma) { + struct qce_device *qce = container_of(dma, + struct qce_device, dma); + dma_release_channel(dma->txchan); dma_release_channel(dma->rxchan); kfree(dma->result_buf); + if (qce->reg_read_buf) + dmam_free_coherent(qce->dev, QCE_MAX_REG_READ * + sizeof(*qce->reg_read_buf), + qce->reg_read_buf, + qce->reg_buf_phys); + kfree(dma->qce_bam_txn->qce_desc); + kfree(dma->qce_bam_txn); } struct scatterlist * diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 786402169360..f10991590b3f 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -7,6 +7,7 @@ #define _DMA_H_ #include +#include /* maximum data transfer block size between BAM and CE */ #define QCE_BAM_BURST_SIZE 64 @@ -14,6 +15,10 @@ #define QCE_AUTHIV_REGS_CNT 16 #define QCE_AUTH_BYTECOUNT_REGS_CNT 4 #define QCE_CNTRIV_REGS_CNT 4 +#define QCE_BAM_CMD_SGL_SIZE 64 +#define QCE_BAM_CMD_ELEMENT_SIZE 64 +#define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) +#define QCE_MAX_REG_READ 8 struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; @@ -27,13 +32,30 @@ struct qce_result_dump { #define QCE_RESULT_BUF_SZ \ ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE) +struct qce_bam_transaction { + struct bam_cmd_element qce_bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist qce_reg_write_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct scatterlist qce_reg_read_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *qce_desc; + u32 qce_bam_ce_index; + u32 qce_pre_bam_ce_index; + u32 qce_write_sgl_cnt; + u32 qce_read_sgl_cnt; +}; + struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; + struct qce_bam_transaction *qce_bam_txn; void *ignore_buf; }; +struct qce_desc_info { + struct dma_async_tx_descriptor *dma_desc; + enum dma_data_direction dir; +}; + int qce_dma_request(struct device *dev, struct qce_dma_data *dma); void qce_dma_release(struct qce_dma_data *dma); int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in, @@ -44,5 +66,5 @@ int qce_dma_terminate_all(struct qce_dma_data *dma); struct scatterlist * qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, unsigned int max_len); - +void qce_dma_issue_cmd_desc_pending(struct qce_dma_data *dma, bool read); #endif /* _DMA_H_ */ From patchwork Thu Dec 14 11:42:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178679 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478609dys; Thu, 14 Dec 2023 03:43:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IGx6KhYMqh4JPNNkTqQ8euMuTAdp4XYDLouQMVDpNHyDAtg8TTIqKo/ddN6etBta+uMly0Q X-Received: by 2002:a05:6358:94a7:b0:170:cb4d:7fc2 with SMTP id i39-20020a05635894a700b00170cb4d7fc2mr5569505rwb.49.1702554188641; Thu, 14 Dec 2023 03:43:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554188; cv=none; d=google.com; s=arc-20160816; b=uUCVXsNOby3+B7zlQdn4U67SHUzzpHWPsOZgCWaQ1vtrzWw+gN9balasx/VKpw3e1b 6uIN4Aq+/A/ZISujBPUBv1pKkzlEH6KQV4uTqHwZHrqhHFfYtvp+JJc9iJjirgHtXntn 3AGQlcUHnmrFRTEqfbSp7ueSzgg/tUAG208B6lbLL+xFJsKh1snNHqtfR7G3qmaPU72l otvJoHpSvXAHThlyouM5LM1/3uPhlBQBHSx/ij5C6nV8PoJDCnb2x+yj46maj2FXSNar 9q5iaClnu4UReqj1hFjAaGpyHZcdyvfCikEFyZkpL4rd6lQie97D83YtCakpQ/KuMVRn o3QA== ARC-Message-Signature: i=1; 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Thu, 14 Dec 2023 03:43:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257460844748194 X-GMAIL-MSGID: 1785257460844748194 Convert register read/write for skcipher via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/common.c | 42 +++++++++++++++++++++-------------- drivers/crypto/qce/skcipher.c | 12 ++++++++++ 2 files changed, 37 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d3340..d1da6b1938f3 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -34,7 +34,7 @@ static inline void qce_write_array(struct qce_device *qce, u32 offset, int i; for (i = 0; i < len; i++) - qce_write(qce, offset + i * sizeof(u32), val[i]); + qce_write_reg_dma(qce, offset + i * sizeof(u32), val[i], 1); } static inline void @@ -43,7 +43,7 @@ qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) int i; for (i = 0; i < len; i++) - qce_write(qce, offset + i * sizeof(u32), 0); + qce_write_reg_dma(qce, offset + i * sizeof(u32), 0, 1); } static u32 qce_config_reg(struct qce_device *qce, int little) @@ -86,16 +86,16 @@ static void qce_setup_config(struct qce_device *qce) config = qce_config_reg(qce, 0); /* clear status */ - qce_write(qce, REG_STATUS, 0); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_STATUS, 0, 1); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); } static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) { if (result_dump) - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); + qce_write_reg_dma(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT), 1); else - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); + qce_write_reg_dma(qce, REG_GOPROC, BIT(GO_SHIFT), 1); } #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AEAD) @@ -308,7 +308,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey, /* Set data unit size to cryptlen. Anything else causes * crypto engine to return back incorrect results. */ - qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen); + qce_write_reg_dma(qce, REG_ENCR_XTS_DU_SIZE, cryptlen, 1); } static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) @@ -325,7 +325,9 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) u32 encr_cfg = 0, auth_cfg = 0, config; unsigned int ivsize = rctx->ivsize; unsigned long flags = rctx->flags; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_XTS(flags)) @@ -336,7 +338,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) qce_cpu_to_be32p_array(enckey, ctx->enc_key, keylen); enckey_words = keylen / sizeof(u32); - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); encr_cfg = qce_encr_cfg(flags, keylen); @@ -369,25 +371,31 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) if (IS_ENCRYPT(flags)) encr_cfg |= BIT(ENCODE_SHIFT); - qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); - qce_write(qce, REG_ENCR_SEG_START, 0); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_START, 0, 1); if (IS_CTR(flags)) { - qce_write(qce, REG_CNTR_MASK, ~0); - qce_write(qce, REG_CNTR_MASK0, ~0); - qce_write(qce, REG_CNTR_MASK1, ~0); - qce_write(qce, REG_CNTR_MASK2, ~0); + qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1); } - qce_write(qce, REG_SEG_SIZE, rctx->cryptlen); + qce_write_reg_dma(qce, REG_SEG_SIZE, rctx->cryptlen, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); qce_crypto_go(qce, true); + ret = qce_submit_cmd_desc(qce, 0); + if (ret) { + dev_err(qce->dev, "Error in skcipher cmd descriptor\n"); + return ret; + } + return 0; } #endif diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index 5b493fdc1e74..fa7ee5db9aa0 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -31,6 +31,7 @@ static void qce_skcipher_done(void *data) struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); struct qce_device *qce = tmpl->qce; + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; struct qce_result_dump *result_buf = qce->dma.result_buf; enum dma_data_direction dir_src, dir_dst; u32 status; @@ -52,6 +53,17 @@ static void qce_skcipher_done(void *data) sg_free_table(&rctx->dst_tbl); + if (qce_bam_txn->qce_read_sgl_cnt) + dma_unmap_sg(qce->dev, + qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + DMA_DEV_TO_MEM); + if (qce_bam_txn->qce_write_sgl_cnt) + dma_unmap_sg(qce->dev, + qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + DMA_MEM_TO_DEV); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); From patchwork Thu Dec 14 11:42:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178682 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478770dys; Thu, 14 Dec 2023 03:43:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IH76i3U+CjwfKJ2EbPF65S3XOq+ojEWH3f9Os96T93j5NCi2O9nHeTRejWrMBnfk535wbD7 X-Received: by 2002:a05:6a00:1789:b0:6ce:6cae:c262 with SMTP id s9-20020a056a00178900b006ce6caec262mr11551568pfg.11.1702554209413; Thu, 14 Dec 2023 03:43:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554209; cv=none; d=google.com; s=arc-20160816; b=JatBERFhn5+SFGKG1rsYhx+DA3LFSml68pmZZXV3yXkwT+jP4GI/aPqPLQbPVT5xej u5h3yzA5l8sruJed5nE7xsHPr0J/xeUiaInfH04PqT1fZ74w6vgwJrdYnMkUbuRg8xml zWbM4BocWXc5YjY6LM0/CSqLGsRSOZeDe439QYpx/Lr5NhwY4Lf1FZjO4bNW2PYl5xIN RwzD/BjN/vJ1sm5tp64oPdKPFa5bby8OBto9iiNV9EIr9JousSgdysvR4uRRe7//chsj YA/uFVuhVJCbg5oClAPtK3brRz1x97mmVTSmC+rT9YfMb8cxDsvzu5qmRKNTR4YQbnkE KCmQ== ARC-Message-Signature: i=1; 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Thu, 14 Dec 2023 03:43:15 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257482762752092 X-GMAIL-MSGID: 1785257482762752092 Convert register read/write for sha via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/common.c | 26 +++++++++++++++++--------- drivers/crypto/qce/sha.c | 12 ++++++++++++ 2 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index d1da6b1938f3..d485762a3fdc 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -157,17 +157,19 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0}; u32 auth_cfg = 0, config; unsigned int iv_words; + int ret; /* if not the last, the size has to be on the block boundary */ if (!rctx->last_blk && req->nbytes % blocksize) return -EINVAL; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_CMAC(rctx->flags)) { - qce_write(qce, REG_AUTH_SEG_CFG, 0); - qce_write(qce, REG_ENCR_SEG_CFG, 0); - qce_write(qce, REG_ENCR_SEG_SIZE, 0); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, 0, 1); qce_clear_array(qce, REG_AUTH_IV0, 16); qce_clear_array(qce, REG_AUTH_KEY0, 16); qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); @@ -213,18 +215,24 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) auth_cfg &= ~BIT(AUTH_FIRST_SHIFT); go_proc: - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); - qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes); - qce_write(qce, REG_AUTH_SEG_START, 0); - qce_write(qce, REG_ENCR_SEG_CFG, 0); - qce_write(qce, REG_SEG_SIZE, req->nbytes); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, req->nbytes, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_SEG_SIZE, req->nbytes, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); qce_crypto_go(qce, true); + ret = qce_submit_cmd_desc(qce, 0); + if (ret) { + dev_err(qce->dev, "Error in sha cmd descriptor\n"); + return ret; + } + return 0; } #endif diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index fc72af8aa9a7..f850c6206a31 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -41,6 +41,7 @@ static void qce_ahash_done(void *data) struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); struct qce_device *qce = tmpl->qce; + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; struct qce_result_dump *result = qce->dma.result_buf; unsigned int digestsize = crypto_ahash_digestsize(ahash); int error; @@ -60,6 +61,17 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); + if (qce_bam_txn->qce_read_sgl_cnt) + dma_unmap_sg(qce->dev, + qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + DMA_DEV_TO_MEM); + if (qce_bam_txn->qce_write_sgl_cnt) + dma_unmap_sg(qce->dev, + qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + DMA_MEM_TO_DEV); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); From patchwork Thu Dec 14 11:42:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178678 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478559dys; Thu, 14 Dec 2023 03:43:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IHXlx5zEBR5xGmDVt9vn/upPQ6gSLUk2Mozw+kqA7A5pZk1ptIOYTCQe/3NqMcNmMZIsUYa X-Received: by 2002:a05:6808:3199:b0:3ba:270:2dee with SMTP id cd25-20020a056808319900b003ba02702deemr8785503oib.91.1702554182429; Thu, 14 Dec 2023 03:43:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554182; cv=none; d=google.com; s=arc-20160816; b=DgsIs/eI1UgiUPdWFXS6KtY8aCOQ1j5e3bqgGHZNrRuLHXpvs8nweOzMXTuurSCUOQ ygfIL+Y2j69RSe/Wj67hKisiZxJUgf0LbDnul0nHW7raIQ7nU2faLvOVkM0q+qFDXbwk ovWAw5G8f7dSBlTDSCRraHSblT5kkj4pFMD/X97h7e8G0n2mS/OhBLKoNM0M/OvvwW1f eYMvmS0g2bHnAs2iW6o4/uyDGlZ6Tt5JCs6NqNcqPi5YiZFAFaQF4B/aCeQejc23nMRw NS4jHf44Ic1mJY2tGhEPKhVH/VrTyjIxLR3pyQq33dNyECwkkR4vPijqaEVRMIWLM8Os aaKg== ARC-Message-Signature: i=1; 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Thu, 14 Dec 2023 03:43:01 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257454320257395 X-GMAIL-MSGID: 1785257454320257395 Convert register read/write for skcipher via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/aead.c | 12 ++++++++++++ drivers/crypto/qce/common.c | 38 ++++++++++++++++++++++--------------- 2 files changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 7d811728f047..c03600f396be 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -29,6 +29,7 @@ static void qce_aead_done(void *data) struct qce_alg_template *tmpl = to_aead_tmpl(crypto_aead_reqtfm(req)); struct qce_device *qce = tmpl->qce; struct qce_result_dump *result_buf = qce->dma.result_buf; + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; enum dma_data_direction dir_src, dir_dst; bool diff_dst; int error; @@ -50,6 +51,17 @@ static void qce_aead_done(void *data) dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); + if (qce_bam_txn->qce_read_sgl_cnt) + dma_unmap_sg(qce->dev, + qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + DMA_DEV_TO_MEM); + if (qce_bam_txn->qce_write_sgl_cnt) + dma_unmap_sg(qce->dev, + qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + DMA_MEM_TO_DEV); + if (IS_CCM(rctx->flags)) { if (req->assoclen) { sg_free_table(&rctx->src_tbl); diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index d485762a3fdc..ff96f6ba1fc5 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -454,7 +454,9 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) unsigned long flags = rctx->flags; u32 encr_cfg, auth_cfg, config, totallen; u32 iv_last_word; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); /* Write encryption key */ @@ -467,12 +469,12 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) if (IS_CCM(rctx->flags)) { iv_last_word = enciv[enciv_words - 1]; - qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1); + qce_write_reg_dma(qce, REG_CNTR3_IV3, iv_last_word + 1, 1); qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words); - qce_write(qce, REG_CNTR_MASK, ~0); - qce_write(qce, REG_CNTR_MASK0, ~0); - qce_write(qce, REG_CNTR_MASK1, ~0); - qce_write(qce, REG_CNTR_MASK2, ~0); + qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1); } /* Clear authentication IV and KEY registers of previous values */ @@ -508,7 +510,7 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) encr_cfg = qce_encr_cfg(flags, enc_keylen); if (IS_ENCRYPT(flags)) encr_cfg |= BIT(ENCODE_SHIFT); - qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1); /* Set up AUTH_SEG_CFG */ auth_cfg = qce_auth_cfg(rctx->flags, auth_keylen, ctx->authsize); @@ -525,34 +527,40 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) else auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; } - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); totallen = rctx->cryptlen + rctx->assoclen; /* Set the encryption size and start offset */ if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize, 1); else - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); - qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff, 1); /* Set the authentication size and start offset */ - qce_write(qce, REG_AUTH_SEG_SIZE, totallen); - qce_write(qce, REG_AUTH_SEG_START, 0); + qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, totallen, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1); /* Write total length */ if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) - qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize); + qce_write_reg_dma(qce, REG_SEG_SIZE, totallen + ctx->authsize, 1); else - qce_write(qce, REG_SEG_SIZE, totallen); + qce_write_reg_dma(qce, REG_SEG_SIZE, totallen, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); /* Start the process */ qce_crypto_go(qce, !IS_CCM(flags)); + ret = qce_submit_cmd_desc(qce, 0); + if (ret) { + dev_err(qce->dev, "Error in aead cmd descriptor\n"); + return ret; + } + return 0; } #endif From patchwork Thu Dec 14 11:42:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178687 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478855dys; Thu, 14 Dec 2023 03:43:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IHGAwO75dLfo1PIkYlEksybmUbuM4fuP3UXY56G8+/WabhPaHxXqzy9ITKTK6U36Ix04pyU X-Received: by 2002:a05:6358:441e:b0:170:4836:cd44 with SMTP id z30-20020a056358441e00b001704836cd44mr12219793rwc.50.1702554218387; Thu, 14 Dec 2023 03:43:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554218; cv=none; d=google.com; s=arc-20160816; b=Xh96NXntRIrsmYYuD5E0YFjRFB6taPuWQBD8eEAheV1LqsHso4pdhDCvjtbak9eG1J arteluTVTnNDpkOhbPGSJ1n/2SekPbzCKeUtR0F00O2DMtSRg3Ko8fXpXMhDSin+K1oV HdCWHF71o2Pg2R1zuH4ZnF8KHvYx4N83h1L9GLtIOjbYdx9PDe3JlH7MdOVvdgsuOdd/ NPw9+x9oOWG/V4F6SJeZBp6yEsELDZqOLjzf6WdZsmjlA+x7WnhTouYTgyM50Pw85UZz heT//MMhFPDlHW6wZJ3PBcgIXtN+u/PeErvEC8gHHOGxWERSy8DRWm1sLGNmh7ZLv0vS XG3Q== ARC-Message-Signature: i=1; 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Thu, 14 Dec 2023 03:43:22 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257491923589223 X-GMAIL-MSGID: 1785257491923589223 Add lock and unlock flag support on command descriptor. Once lock set in requester pipe, then the bam controller will lock all others pipe and process the request only from requester pipe. Unlocking only can be performed from the same pipe. If DMA_PREP_LOCK flag passed in command descriptor then requester of this transaction wanted to lock the BAM controller for this transaction so BAM driver should set LOCK bit for the HW descriptor. If DMA_PREP_UNLOCK flag passed in command descriptor then requester of this transaction wanted to unlock the BAM controller.so BAM driver should set UNLOCK bit for the HW descriptor. Signed-off-by: Md Sadre Alam --- drivers/dma/qcom/bam_dma.c | 10 ++++++++++ include/linux/dma/qcom_bam_dma.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 5e7d332731e0..146d78af3731 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "../dmaengine.h" #include "../virt-dma.h" @@ -58,6 +59,8 @@ struct bam_desc_hw { #define DESC_FLAG_EOB BIT(13) #define DESC_FLAG_NWD BIT(12) #define DESC_FLAG_CMD BIT(11) +#define DESC_FLAG_LOCK BIT(10) +#define DESC_FLAG_UNLOCK BIT(9) struct bam_async_desc { struct virt_dma_desc vd; @@ -686,6 +689,13 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, /* fill in temporary descriptors */ desc = async_desc->desc; + if (flags & DMA_PREP_CMD) { + if (flags & DMA_PREP_LOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_LOCK); + if (flags & DMA_PREP_UNLOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_UNLOCK); + } + for_each_sg(sgl, sg, sg_len, i) { unsigned int remainder = sg_dma_len(sg); unsigned int curr_offset = 0; diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_dma.h index 68fc0e643b1b..bc619c44ce82 100644 --- a/include/linux/dma/qcom_bam_dma.h +++ b/include/linux/dma/qcom_bam_dma.h @@ -8,6 +8,8 @@ #include +#define DMA_PREP_LOCK BIT(0) +#define DMA_PREP_UNLOCK BIT(1) /* * This data type corresponds to the native Command Element * supported by BAM DMA Engine. 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Thu, 14 Dec 2023 03:43:22 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257488826994015 X-GMAIL-MSGID: 1785257488826994015 Add LOCK and UNLOCK flag support while preapring command descriptor for writing crypto register. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/dma.c | 7 ++++++- drivers/crypto/qce/dma.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 85c8d4107afa..bda60e6bc4b3 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -71,7 +71,12 @@ int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) unsigned long desc_flags; int ret = 0; - desc_flags = DMA_PREP_CMD; + if (flags & QCE_DMA_DESC_FLAG_LOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_LOCK; + else if (flags & QCE_DMA_DESC_FLAG_UNLOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_UNLOCK; + else + desc_flags = DMA_PREP_CMD; /* For command descriptor always use consumer pipe * it recomended as per HPG diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index f10991590b3f..ad8a18a720b1 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -19,6 +19,8 @@ #define QCE_BAM_CMD_ELEMENT_SIZE 64 #define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) #define QCE_MAX_REG_READ 8 +#define QCE_DMA_DESC_FLAG_LOCK (0x0002) +#define QCE_DMA_DESC_FLAG_UNLOCK (0x0001) struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; From patchwork Thu Dec 14 11:42:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178681 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478694dys; Thu, 14 Dec 2023 03:43:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IGbtIn+F3J79LwcT93B38XPUo00W/d6/pHoa4gR/OHabjByg935XTqWAi0dVx+X1R/+r/HS X-Received: by 2002:a05:6808:1294:b0:3b8:b063:5058 with SMTP id a20-20020a056808129400b003b8b0635058mr10142419oiw.89.1702554199186; Thu, 14 Dec 2023 03:43:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554199; cv=none; d=google.com; s=arc-20160816; b=qwbrO4RNDfn1WsAIAAZkAg1SAUvdw1ronW7dImjwJhTIseRFimseAnmBq06X0NTW1w thntk22atPBTiDLP3UuuAwz3mNRKU5HOS79/GQD4sM+Sr/rjqfEHMf/MqrF1yD/9pd7W 9e2KhpmOOEPInB5XnLEtg5xYArKb3ONVLIKZgdnM5nUsyZ6i8lvBHj2c9PWsbUCyrEzw 6A+fzEMluezp85rhrBK/Sstqc4Ywt+wH+7aZ8MdGOlWU5QbWr+c1DbV4ne89dU0JBuH7 zQTtwJi2iZrthhLEyFvPRyoHidpHVeS16hM5KQl+DroIkmdblkJVp1a8NX5Cq3mkABKQ cv3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wFSa4XbhxhY/eUFYQapfTu49LcidIL4qfDML5fBRy48=; fh=TEn06IatapHMgkFhNRCYXHrnqycBlFaJECTG22CvvEc=; b=mYwAK59CbcgiB51jGyRhJwX8IXgd2XPF+tsIJKKVBhRomLvwXl8105KHlCuyMBGsZy ZZj/wp9jtZtrlVr1yMiKnA7Dl7aeIdM94JZ3KjdXjTFUy2NEUKaoIt9/qEs2UhPnksRe y5KZaV6DBY+eyYUYn1o/LqrRmfjsGNR18F2x+UUW6C6CbYm3to7178D2K4loYb5kKzep H79rPXpnER+2SLjVq7Typ7Yf+HGKfagxZEQ2NiDlGRagazvS90RkON/9Tzt5NVWxwG2S 4zLB+zMi3BOChRSAQjBqeq767C3po/Gx7yUpakR69/EtA2lxoHANMkGGcRjRPXirVx/i Wdaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Rb0G1WOH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Date: Thu, 14 Dec 2023 17:12:36 +0530 Message-Id: <20231214114239.2635325-9-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214114239.2635325-1-quic_mdalam@quicinc.com> References: <20231214114239.2635325-1-quic_mdalam@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HTiBrGur5d00_fZ2R78aNte1E_sUWF1t X-Proofpoint-ORIG-GUID: HTiBrGur5d00_fZ2R78aNte1E_sUWF1t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140080 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 14 Dec 2023 03:43:18 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257471962971670 X-GMAIL-MSGID: 1785257471962971670 Add support for lock acquire and lock release api. When multiple EE's(Execution Environment) want to access CE5 then there will be race condition b/w multiple EE's. Since each EE's having their dedicated BAM pipe, BAM allows Locking and Unlocking on BAM pipe. So if one EE's requesting for CE5 access then that EE's first has to LOCK the BAM pipe while setting LOCK bit on command descriptor and then access it. After finishing the request EE's has to UNLOCK the BAM pipe so in this way we race condition will not happen. Added these two API qce_bam_acquire_lock() and qce_bam_release_lock() for the same. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/common.c | 38 +++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/core.h | 2 ++ 2 files changed, 40 insertions(+) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index ff96f6ba1fc5..d3b461331b24 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -617,3 +617,41 @@ void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; } + +int qce_bam_acquire_lock(struct qce_device *qce) +{ + u32 val = 0; + int ret; + + qce_clear_bam_transaction(qce); + + /* This is just a dummy read to acquire lock bam pipe */ + qce_read_reg_dma(qce, REG_STATUS2, &val, 1); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_LOCK); + if (ret) { + dev_err(qce->dev, "Error in LOCK cmd descriptor\n"); + return ret; + } + + return 0; +} + +int qce_bam_release_lock(struct qce_device *qce) +{ + u32 val = 0; + int ret; + + qce_clear_bam_transaction(qce); + + /* This just dummy read to release lock on bam pipe*/ + qce_read_reg_dma(qce, REG_STATUS2, &val, 1); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_UNLOCK); + if (ret) { + dev_err(qce->dev, "Error in LOCK cmd descriptor\n"); + return ret; + } + + return 0; +} diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index bf28dedd1509..d01d810b60ad 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -68,4 +68,6 @@ int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, void qce_clear_bam_transaction(struct qce_device *qce); int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); +int qce_bam_acquire_lock(struct qce_device *qce); +int qce_bam_release_lock(struct qce_device *qce); #endif /* _CORE_H_ */ From patchwork Thu Dec 14 11:42:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178688 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8479096dys; Thu, 14 Dec 2023 03:44:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IFqPvQ3AFrketl1cImtRgdJ+pNAWoqElW4aQvr9T2UcxXIYvuRZ2H4gPCZ/53OOQ9yiqBvR X-Received: by 2002:a05:6870:7247:b0:203:2ae6:206b with SMTP id y7-20020a056870724700b002032ae6206bmr2994133oaf.79.1702554243390; Thu, 14 Dec 2023 03:44:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554243; cv=none; d=google.com; s=arc-20160816; b=wOijzT1dIHLlSi4uZ8+0AsAdZraYWzoUTTwCRgyclWieQipak3A84kXCmk1rpw+Yw1 FpnBcUcEi8+pfWdMRBtbi9aEPDlvZtysvfYqQRn1u9RFpB6VfswYAEETVqeFAZoK5tiQ wdVB6oUVsSoBqm0xgTF8N7/JajUjXPm6iVFADeOHvXdDFitu4RZK131SU16QKgmVsDcv ChctBkDcUIQtjGTLR4iN6CjBNzNfseA4SpqdM9EXwF/BslbJFz27ZsK/RMI1dpHqp3zX +W/KssMFCEN0YWw23qHnd4gJAap5gD4PTKvtQ9Md125UPUR+J3Xwujj9pGFxHdZHHZT9 VHFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jeaEe5HnF2x0m61p1cqViCnzJTUQfXgbn7gCqVrYXWY=; fh=TEn06IatapHMgkFhNRCYXHrnqycBlFaJECTG22CvvEc=; b=asUqaEI8hYUwiwVmMDJfKJv0M8LnxCaIpUgRTyMZe3L7F2HRhcqsA1/nUBSEMHG4BD 6jq8cXx9uktDkEU2y0fGHl+ECa62u2jdidi6qZ7kCE3Yf0f/VbhmQ0hFjdUgI67TABiz 2EZzWm+Gszd1iLAC8kh2uQZk/fcuuO5sVczB3kqOTveII6lHdPUrPOu0amOxZE/XE/Oa 7D6acNrPga2SUzCpQuZyKEZGI1dPe5lPpDzTcLQ3SfyL5fJfmrtl4zz1yx6haYy7FRyt ce0Mvi6cDVTW/bvVVOjr0652Z5KngCwovOsgGSY0eJPDdXQx8C2m2TThxQ10DxIfw+ze CqpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Glx6lDfr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from morse.vger.email (morse.vger.email. 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Thu, 14 Dec 2023 11:42:48 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3BEBexrC001132; Thu, 14 Dec 2023 11:42:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3uvhaktcha-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 11:42:44 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3BEBex01001124; Thu, 14 Dec 2023 11:42:44 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3BEBgiLw003204 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 11:42:44 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 9F3A841674; Thu, 14 Dec 2023 17:12:42 +0530 (+0530) From: Md Sadre Alam To: thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, quic_srichara@quicinc.com, quic_varada@quicinc.com Cc: quic_mdalam@quicinc.com Subject: [PATCH 09/11] crypto: qce - Add support for lock/unlock in skcipher Date: Thu, 14 Dec 2023 17:12:37 +0530 Message-Id: <20231214114239.2635325-10-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214114239.2635325-1-quic_mdalam@quicinc.com> References: <20231214114239.2635325-1-quic_mdalam@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IQo-KjvO-Z2zSMrrTFCRlCj_MGfHwWd5 X-Proofpoint-GUID: IQo-KjvO-Z2zSMrrTFCRlCj_MGfHwWd5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140080 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Thu, 14 Dec 2023 03:43:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257518198702936 X-GMAIL-MSGID: 1785257518198702936 Add support for lock/unlock on bam pipe in skcipher. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/skcipher.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index fa7ee5db9aa0..c74df30e8e31 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -42,6 +42,8 @@ static void qce_skcipher_done(void *data) dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; + qce_bam_release_lock(qce); + error = qce_dma_terminate_all(&qce->dma); if (error) dev_dbg(qce->dev, "skcipher dma termination error (%d)\n", @@ -94,6 +96,8 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; + qce_bam_acquire_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->cryptlen); if (diff_dst) rctx->dst_nents = sg_nents_for_len(req->dst, req->cryptlen); From patchwork Thu Dec 14 11:42:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178683 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478820dys; Thu, 14 Dec 2023 03:43:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IFqWsmACedNMFrd1EIU6XefCDFg+5mUEU/oYkHlddVJot9RqXelkWsIJVgSqYpSgOowP8D8 X-Received: by 2002:a17:90a:2b08:b0:28b:105c:2ce4 with SMTP id x8-20020a17090a2b0800b0028b105c2ce4mr119277pjc.66.1702554215127; Thu, 14 Dec 2023 03:43:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554215; cv=none; d=google.com; s=arc-20160816; b=Vok/rBv1oBV6Hmi0kaZCmvsZ1/LZ9f2c4+X08sLCUjb+Yub7m+RDxF2/bP+WUKL122 5H7bQqEr4Wtx6LZoNsi9eYNW1QaODvQyPYrWFD5VntCSIpJf4NbLGdXv+teRIAbKcVh2 mrmjx9eeTpegSOQ/WHM+PViTwlpM0NzsSXysM7PEz7abuq8NtZjInmMdGewVtcdyKsSm 7x45gb7LmBPeHuh/tyHYCIh7624u2d9Zv9QpfbwCAAychnhR//ZtAOHazDJvTxSN53g3 1dpUNKE2nmmDPUuGmszVxCvKC1LJ8O+SZmNBEqwVlQ+FlgjcdsC7S4ueUYxJEbjB4E+O 4Udg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hfMKRVnpBaCu6d6aUwhdQLjOhhBXaGuNFVwN6cK+sqg=; fh=TEn06IatapHMgkFhNRCYXHrnqycBlFaJECTG22CvvEc=; b=Lip26cegDsRoIf2wIXq7SOeoG+VsN47Fv2o3Iw5wHBVjaSAO3DewcGsJ5VSYlWpiL+ akKroWZcaWxHLc8bHmOloKKDNGt/PIP2kjk51Tc67P3a42KJBUUmxX1TCHN28qWg0YVF /QRdatYR6VVDhfK7t2vLw9YOMNYhRPcuyQc/p0px0+rKooEz9QAxQn+cZCIvQcEpHR6P axB0U9BRP8tzjN/9djmJG6rUS+b/EBOQ1TFbXqF7i45kUPaEQzpOUfOji96s/SXapD2m 0RbUNYlBGhMJjAFzBHMxhUbbvPfrY+RshD4w4fPmmR3jVrodF4TCYFeVbgbcGaBxaCPF 7xLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=SbW8yd0t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from morse.vger.email (morse.vger.email. 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Thu, 14 Dec 2023 03:43:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257488691312700 X-GMAIL-MSGID: 1785257488691312700 Add support for lock/unlock on bam pipe in sha. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/sha.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index f850c6206a31..942aecbb0736 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -47,6 +47,8 @@ static void qce_ahash_done(void *data) int error; u32 status; + qce_bam_release_lock(qce); + error = qce_dma_terminate_all(&qce->dma); if (error) dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error); @@ -102,6 +104,8 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) rctx->authklen = AES_KEYSIZE_128; } + qce_bam_acquire_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); if (rctx->src_nents < 0) { dev_err(qce->dev, "Invalid numbers of src SG.\n"); From patchwork Thu Dec 14 11:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 178680 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8478634dys; Thu, 14 Dec 2023 03:43:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IEjlgEZ4txnipMBjoTKFArvvQ4XPXtGLPMFXB6d08vfLEMU0pV4vpypWlXRZMJFwvdHMJPc X-Received: by 2002:a17:90b:384e:b0:286:6cc1:3f1c with SMTP id nl14-20020a17090b384e00b002866cc13f1cmr7143584pjb.83.1702554192964; Thu, 14 Dec 2023 03:43:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702554192; cv=none; d=google.com; s=arc-20160816; b=wNZKPYspQrxvqplYH8OA4A+mvOfbRd1jo88JQ0fEhNuyLz3FXRhv6j2L/vLZfwhOM9 maNW7TcAARC9hHc0XCGmooeyW1/KJyv7cwRPGhzNzabdttaIL1DWwb+3ZL9AmO6iXhh4 sF8tNoGLq1wJgan5aD8jWrKtml0NgH0jqm7srCK+IUDq2nUkBu5dGp0ccZz+bA4ZVifr EofHrGDWk+8SrEMdydCHjvcsK4LT0Nl8AK4vdPzDLgZJtwZKOwwKrRI8+BcKRHAJdbbr ndTu4AH3EuqfvIMzXtwehaEHXPAHukUUK2C5MAIis5vfravZAilObggkqeLSr7bPf3US NUFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3BBK0cA16vlGVM1ePtMVzo9Y00CXkV7qW3NiffbeC10=; fh=TEn06IatapHMgkFhNRCYXHrnqycBlFaJECTG22CvvEc=; b=PUBcgEq1LkNwxXgLhddKdwoG+joV/as/4/C4Lfrv7uKQGWPK357YhNWDsxHjC8d+9c ey79Pmtf4kCTw3djOPprtkWxSTCXe5rdHiGIea3AsDsO9RVngJQ83xQx84z95mUvGpGA T3nVrOfpkCIycA6GogfjaUiuRSbL5jDhgfDig5QEb6yu7bXnf0bqeGZZaiYLbMW9liga azPOzc/HGGL1jqN6zjBV7dyj0l47KsU64OKj2iRM9q5Nn732IZXEFCLB7jGEgHduBQY2 Wkz/9GuABelK9u/snJrYN/ZMHPqzZKIcBWwhL7Bcl+C4chJoICzulVNrYd85M2kYkgcm YB0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=a3LN9IpL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from morse.vger.email (morse.vger.email. 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Thu, 14 Dec 2023 11:42:48 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3BEBgiA4003251; Thu, 14 Dec 2023 11:42:44 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3uvhaktchj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 11:42:44 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3BEBgiaL003237; Thu, 14 Dec 2023 11:42:44 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3BEBgiHc003207 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 11:42:44 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id A639F41682; Thu, 14 Dec 2023 17:12:42 +0530 (+0530) From: Md Sadre Alam To: thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, quic_srichara@quicinc.com, quic_varada@quicinc.com Cc: quic_mdalam@quicinc.com Subject: [PATCH 11/11] crypto: qce - Add support for lock/unlock in aead Date: Thu, 14 Dec 2023 17:12:39 +0530 Message-Id: <20231214114239.2635325-12-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214114239.2635325-1-quic_mdalam@quicinc.com> References: <20231214114239.2635325-1-quic_mdalam@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Wq7F7IUxFM9cgXcVeUgi--HxMwPjmT56 X-Proofpoint-ORIG-GUID: Wq7F7IUxFM9cgXcVeUgi--HxMwPjmT56 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140080 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Thu, 14 Dec 2023 03:43:09 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785257465791522196 X-GMAIL-MSGID: 1785257465791522196 Add support for lock/unlock on bam pipe in aead. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- drivers/crypto/qce/aead.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index c03600f396be..0948c30ea515 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -42,6 +42,8 @@ static void qce_aead_done(void *data) dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; + qce_bam_release_lock(qce); + error = qce_dma_terminate_all(&qce->dma); if (error) dev_dbg(qce->dev, "aead dma termination error (%d)\n", @@ -445,6 +447,8 @@ qce_aead_async_req_handle(struct crypto_async_request *async_req) else rctx->assoclen = req->assoclen; + qce_bam_acquire_lock(qce); + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;