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Thu, 14 Dec 2023 09:03:30 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE93Tsc005427 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:03:29 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:03:24 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v3 1/5] net: mdio: ipq4019: move eth_ldo_rdy before MDIO bus register Date: Thu, 14 Dec 2023 17:03:00 +0800 Message-ID: <20231214090304.16884-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214090304.16884-1-quic_luoj@quicinc.com> References: <20231214090304.16884-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xtu0ot2WrfsMo5KY90KYO2yt00yo2Ppp X-Proofpoint-GUID: xtu0ot2WrfsMo5KY90KYO2yt00yo2Ppp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140058 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 14 Dec 2023 01:04:00 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785247451339598124 X-GMAIL-MSGID: 1785247451339598124 The ethernet LDO provides the clock for the ethernet PHY that is connected with PCS, each LDO enables the clock output to each PCS, after the clock output enablement, the PHY GPIO reset can take effect. For the PHY taking the MDIO bus level GPIO reset, the ethernet LDO should be enabled before the MDIO bus register. For example, the qca8084 PHY takes the MDIO bus level GPIO reset for quad PHYs, there is another reason for qca8084 PHY using MDIO bus level GPIO reset instead of PHY level GPIO reset as below. The work sequence of qca8084: 1. enable ethernet LDO. 2. GPIO reset on quad PHYs. 3. register clock provider based on MDIO device of qca8084. 4. PHY probe function called for initializing common clocks. 5. PHY capabilities acquirement. If qca8084 takes PHY level GPIO reset in the step 4, the clock provider of qca8084 can't be registered correctly, since the clock parent(reading the current qca8084 hardware registers in step 3) of the registered clocks is deserted after GPIO reset. There are two PCS(UNIPHY) supported in SOC side on ipq5332, and three PCS(UNIPHY) supported on ipq9574. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 51 +++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index abd8b508ec16..5273864fabb3 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -37,9 +37,12 @@ #define IPQ_PHY_SET_DELAY_US 100000 +/* Maximum SOC PCS(uniphy) number on IPQ platform */ +#define ETH_LDO_RDY_CNT 3 + struct ipq4019_mdio_data { - void __iomem *membase; - void __iomem *eth_ldo_rdy; + void __iomem *membase; + void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *mdio_clk; }; @@ -206,19 +209,8 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; - u32 val; int ret; - /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 - * is specified in the device tree. - */ - if (priv->eth_ldo_rdy) { - val = readl(priv->eth_ldo_rdy); - val |= BIT(0); - writel(val, priv->eth_ldo_rdy); - fsleep(IPQ_PHY_SET_DELAY_US); - } - /* Configure MDIO clock source frequency if clock is specified in the device tree */ ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); if (ret) @@ -236,7 +228,7 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) struct ipq4019_mdio_data *priv; struct mii_bus *bus; struct resource *res; - int ret; + int ret, index; bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); if (!bus) @@ -252,11 +244,32 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->mdio_clk)) return PTR_ERR(priv->mdio_clk); - /* The platform resource is provided on the chipset IPQ5018 */ - /* This resource is optional */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) - priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res); + /* These platform resources are provided on the chipset IPQ5018 or + * IPQ5332. + */ + /* This resource are optional */ + for (index = 0; index < ETH_LDO_RDY_CNT; index++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, index + 1); + if (res) { + priv->eth_ldo_rdy[index] = devm_ioremap(&pdev->dev, + res->start, + resource_size(res)); + + /* The ethernet LDO enable is necessary to reset PHY + * by GPIO, some PHY(such as qca8084) GPIO reset uses + * the MDIO level reset, so this function should be + * called before the MDIO bus register. + */ + if (priv->eth_ldo_rdy[index]) { + u32 val; + + val = readl(priv->eth_ldo_rdy[index]); + val |= BIT(0); + writel(val, priv->eth_ldo_rdy[index]); + fsleep(IPQ_PHY_SET_DELAY_US); + } + } + } bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; From patchwork Thu Dec 14 09:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 178582 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8408941dys; Thu, 14 Dec 2023 01:04:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IF5DX+XBmkKuezGDD0Qy6ZeMJBEW7uKKAXzw4as2jfG20dPU4csL8lQ/AWtPGaPhgr/nvXJ X-Received: by 2002:a05:6870:3b0e:b0:203:49a:ebb1 with SMTP id gh14-20020a0568703b0e00b00203049aebb1mr4524988oab.73.1702544649880; Thu, 14 Dec 2023 01:04:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702544649; cv=none; d=google.com; s=arc-20160816; b=tTc4QF4X/s3DR5ARG7siXMHkGHw49AQp8j3Cc/EdbyJziaRblGYYOXVEuDiOf9mOwy +IRO4eGS6V+JmYhY1v7bhuclm2EMFC9Kn5GCclkpdaBiJ1El/Bpzov2elQmoPfbUVvCL pSoBYM9slXJC+LDhS0jxaoBO5rF4QWa3nvkGetRuwS0sRX9EllqgGBLEVcODlum5f/Un knjrZ2ccIdDquGtTUqGvUWtK9qPW0LSPRhCRJahPoYuP6bDspdJ//I+yssU+HLzdBqWS fi6xQB7h+4FkA0/KfYz4lH28wTPt4HAQoVez6n5+kk1M41S2JDa/DEnzESq6iPsH0oe0 27uQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mlYzy+wSb4NOhKpWT5m2fOWnkyhlsBAyvm+KXUCzv5Y=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=PYxYW7mfQueN1V5XGVo9Z0+MD6vH/SbVt94NfffqM7QzEvQmxwekiAHKGzpGX0NJO/ 9OA4C+I6/gWMQT9nQs7VdH4BG2voV/LsHzyu1ojjHYDX08686yWWQS/k2fbjZhSq0oEn a2TyI/lwojTl5vG6Xp7ljB5iTacJHuefWuQinJaQQAjE7+qwcpcKBIUzNIY4kNrvHaLI TLChhD313340urYIT6vlBV4lY02WkmbW4TPFCazPjWwT981KUU+Tqm58ZeN6I74QF6WQ s2pHSPCkB2Ta9v0a45/V0CXbtwQdbPaQiRoMgZIDEZVx7Wh/IaqcFxkn79U7oCcXw8NA DgvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=RQ0171El; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Thu, 14 Dec 2023 09:03:35 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE93YZ6011109 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:03:34 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:03:29 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v3 2/5] net: mdio: ipq4019: enable the SoC uniphy clocks for ipq5332 platform Date: Thu, 14 Dec 2023 17:03:01 +0800 Message-ID: <20231214090304.16884-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214090304.16884-1-quic_luoj@quicinc.com> References: <20231214090304.16884-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IquLOnA1wIRV3uryLSgYSzHok6ZNPaMi X-Proofpoint-ORIG-GUID: IquLOnA1wIRV3uryLSgYSzHok6ZNPaMi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140058 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 14 Dec 2023 01:04:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785247459125026100 X-GMAIL-MSGID: 1785247459125026100 On the platform ipq5332, the related SoC uniphy GCC clocks need to be enabled for making the MDIO slave devices accessible. These UNIPHY clocks are from the SoC platform GCC clock provider, which are enabled for the connected PHY devices working. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 75 ++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 5273864fabb3..e24b0e688b10 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -35,15 +35,36 @@ /* MDIO clock source frequency is fixed to 100M */ #define IPQ_MDIO_CLK_RATE 100000000 +/* SoC UNIPHY fixed clock */ +#define IPQ_UNIPHY_AHB_CLK_RATE 100000000 +#define IPQ_UNIPHY_SYS_CLK_RATE 24000000 + #define IPQ_PHY_SET_DELAY_US 100000 /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +enum mdio_clk_id { + MDIO_CLK_MDIO_AHB, + MDIO_CLK_UNIPHY0_AHB, + MDIO_CLK_UNIPHY0_SYS, + MDIO_CLK_UNIPHY1_AHB, + MDIO_CLK_UNIPHY1_SYS, + MDIO_CLK_CNT +}; + struct ipq4019_mdio_data { void __iomem *membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; - struct clk *mdio_clk; + struct clk *clk[MDIO_CLK_CNT]; +}; + +static const char *const mdio_clk_name[] = { + "gcc_mdio_ahb_clk", + "uniphy0_ahb", + "uniphy0_sys", + "uniphy1_ahb", + "uniphy1_sys" }; static int ipq4019_mdio_wait_busy(struct mii_bus *bus) @@ -209,14 +230,43 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; - int ret; + unsigned long rate; + int ret, index; - /* Configure MDIO clock source frequency if clock is specified in the device tree */ - ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); - if (ret) - return ret; + /* For the platform ipq5332, there are two SoC uniphies available + * for connecting with ethernet PHY, the SoC uniphy gcc clock + * should be enabled for resetting the connected device such + * as qca8386 switch, qca8081 PHY or other PHYs effectively. + * + * Configure MDIO/UNIPHY clock source frequency if clock instance + * is specified in the device tree. + */ + for (index = MDIO_CLK_MDIO_AHB; index < MDIO_CLK_CNT; index++) { + switch (index) { + case MDIO_CLK_MDIO_AHB: + rate = IPQ_MDIO_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_AHB: + case MDIO_CLK_UNIPHY1_AHB: + rate = IPQ_UNIPHY_AHB_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_SYS: + case MDIO_CLK_UNIPHY1_SYS: + rate = IPQ_UNIPHY_SYS_CLK_RATE; + break; + default: + break; + } + + ret = clk_set_rate(priv->clk[index], rate); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[index]); + if (ret) + return ret; + } - ret = clk_prepare_enable(priv->mdio_clk); if (ret == 0) mdelay(10); @@ -240,10 +290,6 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); - priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); - if (IS_ERR(priv->mdio_clk)) - return PTR_ERR(priv->mdio_clk); - /* These platform resources are provided on the chipset IPQ5018 or * IPQ5332. */ @@ -271,6 +317,13 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) } } + for (index = 0; index < MDIO_CLK_CNT; index++) { + priv->clk[index] = devm_clk_get_optional(&pdev->dev, + mdio_clk_name[index]); + if (IS_ERR(priv->clk[index])) + return PTR_ERR(priv->clk[index]); + } + bus->name = "ipq4019_mdio"; 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Thu, 14 Dec 2023 09:03:40 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE93dHV013269 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:03:39 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:03:34 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v3 3/5] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Date: Thu, 14 Dec 2023 17:03:02 +0800 Message-ID: <20231214090304.16884-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214090304.16884-1-quic_luoj@quicinc.com> References: <20231214090304.16884-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Lq7cqdWlLZr2VlzMzX6bfdXxaslk30Pt X-Proofpoint-GUID: Lq7cqdWlLZr2VlzMzX6bfdXxaslk30Pt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140059 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 14 Dec 2023 01:04:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785247474136608987 X-GMAIL-MSGID: 1785247474136608987 The reference clock of CMN PLL block is selectable, the internal 48MHZ is used by default. The output clock of CMN PLL block is for providing the clock source of ethernet device(such as qca8084), there are 1 * 25MHZ and 3 * 50MHZ output clocks available for the ethernet devices. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 137 +++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index e24b0e688b10..3568ce7f48c6 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -44,6 +44,25 @@ /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +#define CMN_PLL_REFERENCE_SOURCE_SEL 0x28 +#define CMN_PLL_REFCLK_SOURCE_DIV GENMASK(9, 8) + +#define CMN_PLL_REFERENCE_CLOCK 0x784 +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) +#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) + +#define CMN_PLL_POWER_ON_AND_RESET 0x780 +#define CMN_ANA_EN_SW_RSTN BIT(6) + +#define CMN_REFCLK_INTERNAL_48MHZ 0 +#define CMN_REFCLK_EXTERNAL_25MHZ 1 +#define CMN_REFCLK_EXTERNAL_31250KHZ 2 +#define CMN_REFCLK_EXTERNAL_40MHZ 3 +#define CMN_REFCLK_EXTERNAL_48MHZ 4 +#define CMN_REFCLK_EXTERNAL_50MHZ 5 +#define CMN_REFCLK_INTERNAL_96MHZ 6 + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -55,6 +74,7 @@ enum mdio_clk_id { struct ipq4019_mdio_data { void __iomem *membase; + void __iomem *cmn_membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; }; @@ -227,12 +247,116 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, return 0; } +/* For the CMN PLL block, the reference clock can be configured according to + * the device tree property "cmn-reference-clock", the internal 48MHZ is used + * by default on the ipq533 platform. + * + * The output clock of CMN PLL block is provided to the ethernet devices, + * threre are 4 CMN PLL output clocks (1*25MHZ + 3*50MHZ) enabled by default. + * + * Such as the output 50M clock for the qca8084 ethernet PHY. + */ +static int ipq_cmn_clock_config(struct mii_bus *bus) +{ + struct ipq4019_mdio_data *priv; + u32 reg_val, src_sel, ref_clk; + int ret; + + priv = bus->priv; + if (priv->cmn_membase) { + reg_val = readl(priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK); + + /* Select reference clock source */ + ret = of_property_read_u32(bus->parent->of_node, + "cmn-reference-clock", + &ref_clk); + if (!ret) { + switch (ref_clk) { + case CMN_REFCLK_INTERNAL_48MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + break; + case CMN_REFCLK_EXTERNAL_25MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3)); + break; + case CMN_REFCLK_EXTERNAL_31250KHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4)); + break; + case CMN_REFCLK_EXTERNAL_40MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6)); + break; + case CMN_REFCLK_EXTERNAL_48MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7)); + break; + case CMN_REFCLK_EXTERNAL_50MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8)); + break; + case CMN_REFCLK_INTERNAL_96MHZ: + src_sel = readl(priv->cmn_membase + + CMN_PLL_REFERENCE_SOURCE_SEL); + src_sel &= ~CMN_PLL_REFCLK_SOURCE_DIV; + src_sel |= FIELD_PREP(CMN_PLL_REFCLK_SOURCE_DIV, 0); + writel(src_sel, priv->cmn_membase + + CMN_PLL_REFERENCE_SOURCE_SEL); + + reg_val &= ~CMN_PLL_REFCLK_DIV; + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2); + break; + default: + return -EINVAL; + } + } else if (ret == -EINVAL) { + /* If the cmn-reference-clock is not specified, + * the internal 48MHZ is selected by default. + */ + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + } else { + return ret; + } + + writel(reg_val, priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK); + + /* assert CMN PLL */ + reg_val = readl(priv->cmn_membase + CMN_PLL_POWER_ON_AND_RESET); + reg_val &= ~CMN_ANA_EN_SW_RSTN; + writel(reg_val, priv->cmn_membase); + fsleep(IPQ_PHY_SET_DELAY_US); + + /* deassert CMN PLL */ + reg_val |= CMN_ANA_EN_SW_RSTN; + writel(reg_val, priv->cmn_membase + CMN_PLL_POWER_ON_AND_RESET); + fsleep(IPQ_PHY_SET_DELAY_US); + } + + return 0; +} + static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; unsigned long rate; int ret, index; + ret = ipq_cmn_clock_config(bus); + if (ret) + return ret; + /* For the platform ipq5332, there are two SoC uniphies available * for connecting with ethernet PHY, the SoC uniphy gcc clock * should be enabled for resetting the connected device such @@ -296,7 +420,7 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) /* This resource are optional */ for (index = 0; index < ETH_LDO_RDY_CNT; index++) { res = platform_get_resource(pdev, IORESOURCE_MEM, index + 1); - if (res) { + if (res && strcmp(res->name, "cmn_blk")) { priv->eth_ldo_rdy[index] = devm_ioremap(&pdev->dev, res->start, resource_size(res)); @@ -317,6 +441,17 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) } } + /* The CMN block resource is for providing clock source to ethernet, + * which can be optionally configured on the platform ipq9574 and + * ipq5332. + */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cmn_blk"); + if (res) { + priv->cmn_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->cmn_membase)) + return PTR_ERR(priv->cmn_membase); + } + for (index = 0; index < MDIO_CLK_CNT; index++) { priv->clk[index] = devm_clk_get_optional(&pdev->dev, mdio_clk_name[index]); From patchwork Thu Dec 14 09:03:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 178584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8409080dys; Thu, 14 Dec 2023 01:04:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQhfOPuzDr5LminBE96XW3PdnHzyxC4jyegq1MCHnKsCXIiKMVZJGXy94aOs5av2JO1QXR X-Received: by 2002:a05:6e02:17ca:b0:35d:5dc3:f7f4 with SMTP id z10-20020a056e0217ca00b0035d5dc3f7f4mr15830361ilu.58.1702544668122; Thu, 14 Dec 2023 01:04:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702544668; cv=none; d=google.com; s=arc-20160816; b=lwDxFfaD0ed77EjJX1dwO8VcPGAo1aUrZnqWIndqe7OjMagsordODVlJSBqZUrs5P8 i+N6K2Ikai4P6CA+vf1y9z9SeuwLZWPMQ6l4Vel+d4K+UKtbphmx4IuKzjCRmWmnbTue Ge9nAdxQXTZYgBqzuXHYsEhplzbdQaPCN7BRAvY9Kctf4Zb1Z7pEuWhBud146+hmT5+i lrD0zCzTDbUrD/DSXfkSuz47kKqSIyRLC729En17eADSNMugtKSeYf6+J04y+YEX/02D BaxotTAzCnygk6rVwsBVG8ch30fjhtEfrR4SYmPKDI9kFD2d78Jxw/+r/jWbmltmNco1 7hyQ== ARC-Message-Signature: i=1; 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Thu, 14 Dec 2023 01:04:25 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785247477587049377 X-GMAIL-MSGID: 1785247477587049377 The MDIO clock frequency can be divided according to the MDIO control register value. The MDIO system clock is fixed to 100MHZ, the working frequency is 100MHZ/(divider + 1), the divider value is from the bit[7:0] of control register 0x40. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 45 +++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 3568ce7f48c6..330963026475 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -29,6 +29,9 @@ /* 0 = Clause 22, 1 = Clause 45 */ #define MDIO_MODE_C45 BIT(8) +/* MDC frequency is SYS_CLK/(MDIO_CLK_DIV + 1), SYS_CLK is 100MHz */ +#define MDIO_CLK_DIV_MASK GENMASK(7, 0) + #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -77,6 +80,7 @@ struct ipq4019_mdio_data { void __iomem *cmn_membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; + int clk_div; }; static const char *const mdio_clk_name[] = { @@ -110,6 +114,7 @@ static int ipq4019_mdio_read_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -151,6 +156,7 @@ static int ipq4019_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -183,6 +189,7 @@ static int ipq4019_mdio_write_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -226,6 +233,7 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -397,6 +405,39 @@ static int ipq_mdio_reset(struct mii_bus *bus) return ret; } +static int ipq_mdio_clk_set(struct platform_device *pdev, int *clk_div) +{ + int freq; + + /* Keep the MDIO clock divider as the hardware default value 0xff if + * the MDIO property "clock-frequency" is not specified. + */ + if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", &freq)) { + *clk_div = 0xff; + return 0; + } + + /* MDC frequency is SYS_CLK/(MDIO_CLK_DIV + 1), SYS_CLK is fixed + * to 100MHz, the MDIO_CLK_DIV can be only configured the valid + * values, other values cause malfunction. + */ + switch (freq) { + case 12500000: + case 6250000: + case 3125000: + case 1562500: + case 781250: + case 390625: + *clk_div = DIV_ROUND_UP(IPQ_MDIO_CLK_RATE, freq) - 1; + break; + default: + dev_err(&pdev->dev, "Invalid clock frequency %dHZ\n", freq); + return -EINVAL; + } + + return 0; +} + static int ipq4019_mdio_probe(struct platform_device *pdev) { struct ipq4019_mdio_data *priv; @@ -459,6 +500,10 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) return PTR_ERR(priv->clk[index]); } + ret = ipq_mdio_clk_set(pdev, &priv->clk_div); + if (ret) + return ret; + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22; From patchwork Thu Dec 14 09:03:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 178585 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8409157dys; Thu, 14 Dec 2023 01:04:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IG6ax/MZw82+ktkOVjYuhh/EDZt/dbteLiPiNiNs2O36sMimDIxePvpVM4fLTTTUHz3J+Ih X-Received: by 2002:a17:902:f68c:b0:1d3:62a6:98da with SMTP id l12-20020a170902f68c00b001d362a698damr1622108plg.25.1702544677952; Thu, 14 Dec 2023 01:04:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702544677; cv=none; d=google.com; s=arc-20160816; b=RxUgiYHZuWUWbrP7WViZpii8zZ8ljJdewcZwWaeEoZG56lss2gYnhr1mh/Tg3fnFEl 2kNmg0YfwTCXvIeyZcQz1A7EOlTM/HixGLGQCOGOYkl9qSjBKT3KyeCFWHZYunn3Uu8z 5Jmanb7ID4qHbW2XLLd63dLHzmk6ATEnGAxEx1T57gm3AuRxI6OjQGeY0B4/pAk76ZvW tE9Pm/4ccT+Kd6juTOMRx/tYZJIVZaIMdS0HvFAEmjxpGCSEt1EQm11xqrR7wCcpBYxo dI6gC5b3T/DfJwpn9zrcib38zrq5elWXXwfrqp+dtI4Vd9H8z4PsZU/U/oXs+fZv5S9Y N31w== ARC-Message-Signature: i=1; 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Thu, 14 Dec 2023 01:04:35 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785247488350515623 X-GMAIL-MSGID: 1785247488350515623 Update the yaml file for the new DTS properties. 1. cmn-reference-clock for the CMN PLL source clock select. 2. clock-frequency for MDIO clock frequency config. 3. add uniphy AHB & SYS GCC clocks. 4. add reset-gpios for MDIO bus level reset. Signed-off-by: Luo Jie --- .../bindings/net/qcom,ipq4019-mdio.yaml | 143 +++++++++++++++++- 1 file changed, 139 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8a7..79f8513739e7 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml @@ -20,6 +20,8 @@ properties: - enum: - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq9574-mdio + - qcom,ipq5332-mdio - const: qcom,ipq4019-mdio "#address-cells": @@ -30,19 +32,77 @@ properties: reg: minItems: 1 - maxItems: 2 + maxItems: 5 description: - the first Address and length of the register set for the MDIO controller. - the second Address and length of the register for ethernet LDO, this second - address range is only required by the platform IPQ50xx. + the first Address and length of the register set for the MDIO controller, + the optional second, third and fourth address and length of the register + for ethernet LDO, these three address range are required by the platform + IPQ50xx/IPQ5332, the last address and length is for the CMN clock to + select the reference clock. + + reg-names: + minItems: 1 + maxItems: 5 clocks: + minItems: 1 items: - description: MDIO clock source frequency fixed to 100MHZ + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ clock-names: + minItems: 1 items: - const: gcc_mdio_ahb_clk + - const: uniphy0_ahb + - const: uniphy1_ahb + - const: uniphy0_sys + - const: uniphy1_sys + + cmn-reference-clock: + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - items: + - enum: + - 0 # CMN PLL reference internal 48MHZ + - 1 # CMN PLL reference external 25MHZ + - 2 # CMN PLL reference external 31250KHZ + - 3 # CMN PLL reference external 40MHZ + - 4 # CMN PLL reference external 48MHZ + - 5 # CMN PLL reference external 50MHZ + - 6 # CMN PLL reference internal 96MHZ + + clock-frequency: + oneOf: + - items: + - enum: + - 12500000 + - 6250000 + - 3125000 + - 1562500 + - 781250 + - 390625 + description: + The MDIO bus clock that must be output by the MDIO bus hardware, + only the listed frequencies above can be supported, other frequency + will cause malfunction. If absent, the default hardware value 0xff + is used, which means the default MDIO clock frequency 390625HZ, The + MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC + MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control + register, there is higher clock frequency requirement on the normal + working case where the MDIO slave devices support high clock frequency. + + reset-gpios: + maxItems: 1 + + reset-assert-us: + maxItems: 1 + + reset-deassert-us: + maxItems: 1 required: - compatible @@ -61,6 +121,8 @@ allOf: - qcom,ipq5018-mdio - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq5332-mdio + - qcom,ipq9574-mdio then: required: - clocks @@ -70,6 +132,20 @@ allOf: clocks: false clock-names: false + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-mdio + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + reg-names: + minItems: 4 + unevaluatedProperties: false examples: @@ -100,3 +176,62 @@ examples: reg = <4>; }; }; + + - | + #include + #include + + mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5332-mdio", + "qcom,ipq4019-mdio"; + cmn-reference-clock = <0>; + clock-frequency = <6250000>; + + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + + reg = <0x90000 0x64>, + <0x9B000 0x800>, + <0x7A00610 0x4>, + <0x7A10610 0x4>; + + reg-names = "mdio", + "cmn_blk", + "eth_ldo1", + "eth_ldo2"; + + clocks = <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>; + + clock-names = "gcc_mdio_ahb_clk", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy0_sys", + "uniphy1_sys"; + + qca8kphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id004d.d180"; + reg = <1>; + }; + + qca8kphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id004d.d180"; + reg = <2>; + }; + + qca8kphy2: ethernet-phy@3 { + compatible = "ethernet-phy-id004d.d180"; + reg = <3>; + }; + + qca8kphy3: ethernet-phy@4 { + compatible = "ethernet-phy-id004d.d180"; + reg = <4>; + }; + };