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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a1cbe52300csm9026226ejc.56.2023.12.14.00.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 00:25:12 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Andrzej Hajda , Daniel Vetter , David Airlie , Inki Dae , Jagan Teki , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Marek Szyprowski , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v8 1/3] drm: bridge: samsung-dsim: enter display mode in the enable() callback Date: Thu, 14 Dec 2023 09:24:04 +0100 Message-ID: <20231214082457.18737-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> References: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 14 Dec 2023 00:25:31 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785245082758794200 X-GMAIL-MSGID: 1785245082758794200 The synaptics-r63353 (panel-bridge) can only be configured in command mode. So, samsung-dsim (bridge) must not be in display mode during the prepare()/unprepare() of the panel-bridge. Setting the "pre_enable_prev_first" flag to true allows the prepare() of the panel-bridge to be called between the pre_enabled() and enabled() of the bridge. So, the bridge can enter display mode only in the enabled(). The unprepare() of the panel-bridge is instead called between the disable() and post_disable() of the bridge. So, the disable() must exit the display mode (i .e. enter command mode) to allow the panel-bridge to receive DSI commands. samsung_dsim_atomic_pre_enable -> command mode r63353_panel_prepare -> send DSI commands samsung_dsim_atomic_enable -> enter display mode samsung_dsim_atomic_disable -> exit display mode (command mode) r63353_panel_unprepare -> send DSI commands samsung_dsim_atomic_post_disable Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/gpu/drm/bridge/samsung-dsim.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index be5914caa17d..15bf05b2bbe4 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1494,7 +1494,6 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, return; samsung_dsim_set_display_mode(dsi); - samsung_dsim_set_display_enable(dsi, true); } } @@ -1507,6 +1506,7 @@ static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, samsung_dsim_set_display_mode(dsi); samsung_dsim_set_display_enable(dsi, true); } else { + samsung_dsim_set_display_enable(dsi, true); samsung_dsim_set_stop_state(dsi, false); } @@ -1524,6 +1524,8 @@ static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) samsung_dsim_set_stop_state(dsi, true); + samsung_dsim_set_display_enable(dsi, false); + dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; } @@ -1532,7 +1534,8 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, { struct samsung_dsim *dsi = bridge_to_dsi(bridge); - samsung_dsim_set_display_enable(dsi, false); + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + samsung_dsim_set_stop_state(dsi, true); dsi->state &= ~DSIM_STATE_ENABLED; pm_runtime_put_sync(dsi->dev); From patchwork Thu Dec 14 08:24:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 178562 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8394527dys; Thu, 14 Dec 2023 00:25:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IGQ7td08RUouf82t1Syc7N8NSqaOxMZiA7r1hnIAoOzw498OaUCIMGDmj2vBO1LcMz46X1n X-Received: by 2002:a17:90a:f16:b0:28b:6ac:2e77 with SMTP id 22-20020a17090a0f1600b0028b06ac2e77mr512481pjy.97.1702542330000; Thu, 14 Dec 2023 00:25:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702542329; cv=none; d=google.com; s=arc-20160816; b=KqbX3vBs9zxAb3Ai+wnLEOaOAIOlBN3eFv7GvUkxE2+fLVnqffNUkhX7IVnDloSF9x zUGCYVzn+xNvijL1HNRbloKfO+4kCVU92LOZxrPCSymPsUJJSQGydpo86+rHIjbZFwMd l/oOh2PVI6rX8kN+l4mFdNA9zLCZR20q7NPeqwZDPae1N8II2SWt3smjUfLpEIvvZbll SDBThUH+JGzidLOamhufUwC/xk7NMzevrM2U5QjkI7S7/Wz1QHkS2y+TFWkXtg4PsbAq dX7GByCZciarj9UoXy1XhsqwfiHR0b7Um79Nyho1PcYBX0OOGqg25r6aZK4KNOV+uPZj Sycg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LRuU/Yf3+WOs2/s3BqHchrpBnPmBNhkaR5Vfu/UBGmU=; fh=UPLugLp3TGz/UFnnpIyweeCZZjgZZPvHfi+TCy9TH+Y=; b=Wz2vQ9deXCU9lKbL27XKp6myOHtC344QCakwafGFN7v7Su5n8Xq6Gwh4DFUauJgWPr TvhNLyRj/DF14dA/rO2sSkQVBFrW5noyKc5VFlETA4O34gwh+cAIiNsBduvEfhsdFdUm IckQi7X8xkxEMLKOI3fuJjedcyiEXoNAM60eFDr9iLFFmdqbxPWeOXPsQj+65WCSD2+n FagsQwqPDvhD4dcTcqsdDNPpUrLuEwLh73vo2qi3V0lARrJTOF2aiNkxmQ3n1BmksPt0 EUcOyKzGE7NEFgfqxRa2w2e5pk9//L1XD7448uzK2AHpKC5/41TfUgDVrJM4fIBcID+C M8mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Vxnoh+LR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from pete.vger.email (pete.vger.email. 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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a1cbe52300csm9026226ejc.56.2023.12.14.00.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 00:25:14 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Andrzej Hajda , Daniel Vetter , David Airlie , Inki Dae , Jagan Teki , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Marek Szyprowski , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v8 2/3] drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting Date: Thu, 14 Dec 2023 09:24:05 +0100 Message-ID: <20231214082457.18737-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> References: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 14 Dec 2023 00:25:26 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785245026596171127 X-GMAIL-MSGID: 1785245026596171127 The patch completes the setting of CLKLANE_STOP for the imx8mn and imx8mp platforms (i. e. not exynos). Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/gpu/drm/bridge/samsung-dsim.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 15bf05b2bbe4..13f181c99d7e 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -96,6 +96,7 @@ #define DSIM_MFLUSH_VS BIT(29) /* This flag is valid only for exynos3250/3472/5260/5430 */ #define DSIM_CLKLANE_STOP BIT(30) +#define DSIM_NON_CONTINUOUS_CLKLANE BIT(31) /* DSIM_ESCMODE */ #define DSIM_TX_TRIGGER_RST BIT(4) @@ -945,8 +946,12 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi) * power consumption. */ if (driver_data->has_clklane_stop && - dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + reg |= DSIM_NON_CONTINUOUS_CLKLANE; + reg |= DSIM_CLKLANE_STOP; + } samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); lanes_mask = BIT(dsi->lanes) - 1; From patchwork Thu Dec 14 08:24:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 178563 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8394687dys; Thu, 14 Dec 2023 00:25:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IFCC5cO7Eq/LIa+qf/VWxalIA8D/v7/3VXhLyiUSzA7bH+6p5neBMUdeGe/S3dFoKGYxsoC X-Received: by 2002:a05:6808:1a1c:b0:3b9:eec3:925b with SMTP id bk28-20020a0568081a1c00b003b9eec3925bmr11741635oib.77.1702542357759; Thu, 14 Dec 2023 00:25:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702542357; cv=none; d=google.com; s=arc-20160816; b=j3frLjx5L4Xf11gkRc8uOh8Zx2niGGepn+7BjY/dkob5wTtYpM67TA7cpHNZ4VDevp 9ReSYv3ShKNSyhExG0Ry5/wCYU8q+tvKbJgxQwLIO7fVOa+cjBYALiFsrsaoyL7n9v1i XvZHE/j7xI/6nvu3ZWrOLzaaS+U7xWegayicWLP+oZJtYi7lZv/HGZZIppg0KSajYBlR Sr/HvFALRUNZrBgs+ro1MrPzMpuuvROjpHDPCuknf5DrXkDTQ+xsv5KepI/ArAjOuask SeifcOVLlA5igVtAVH4J4YYTjUklZaHUe9I4XYB5duzz27aE/ziRjHQFT9UFMDVJt8P5 EKjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P9aQAquZ5xS5RyqBzg0IY2qUUlWniNS/41pwDJpEejQ=; fh=7gcOMIGX5RJawHCpqVktl/feo/YxGsC5w2AVovKlYnc=; b=Lrndq+tcjOVKiJyhGyC/ycwZYzXn7NJ2djupYdUlujF4iR6Ss5wbTJquoSr+7jjsgj vImGhThJzc/cgoIvSQcsEGZdlCZmKFqiaA4Z7xqC6VTvYOwjRSSY0QG5ojW5wqtffbwK qpeWY7hLYdT4cTW5OQmqzO6X6lkuqUMbrcLxl8ZrpVSHGg2i4Ay+QG2dUAYranpMaWxc EX/lnky/iVEibj+XSTWGqh6Z2eFHNAMcKFgh72Yuw9v9uc4a0zxRip/jOzX6AI2OSy9A i6X7YhA9EbFmtLR1psyu1tvWOxJGfv42VLqrNeF5V0zP1jyTsFrRf9aYbz8eE+LthXMN ii0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NFqUpxjK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from pete.vger.email (pete.vger.email. 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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a1cbe52300csm9026226ejc.56.2023.12.14.00.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 00:25:15 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 3/3] arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup Date: Thu, 14 Dec 2023 09:24:06 +0100 Message-ID: <20231214082457.18737-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> References: <20231214082457.18737-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 14 Dec 2023 00:25:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785245055090839272 X-GMAIL-MSGID: 1785245055090839272 From: Michael Trimarchi Add the display and nodes required for its operation. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- Changes in v8: - Move the 'status' property to the end of the list of nodes: - pwm1 - lcdif - mipi_dsi - Add a newline between properties and child node (mipi_dsi_out). - Sort the iomuxc node alphabetically - Rename pwm1grp to blgrp Changes in v7: - Drop [3/4] dt-bindings: display: panel: Add synaptics r63353 panel controller because applied. Changes in v6: - Drop patches: - [06/10] drm/panel: Add Synaptics R63353 panel driver - [07/10] dt-bindings: display: panel: Add Ilitek ili9805 panel controller - [08/10] drm/panel: Add Ilitek ILI9805 panel driver - [09/10] drm/panel: ilitek-ili9805: add support for Tianma TM041XDHG01 panel Because applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-next) Drop patches: - [01/10] drm/bridge: Fix bridge disable logic - [02/10] drm/bridge: Fix a use case in the bridge disable logic Because they are wrong Changes in v3: - Replace "synaptics,r63353" compatible with "syna,r63353", as required by vendor-prefixes.yaml. - Squash patch [09/11] dt-bindings: ili9805: add compatible string for Tianma TM041XDHG01 into [07/11] dt-bindings: display: panel: Add Ilitek ili9805 panel controller. Changes in v2: - Adjust the mipi_dsi node based on the latest patches merged into the mainline in the dtsi files it includes. - Added to the series the following patches: - 0001 drm/bridge: Fix bridge disable logic - 0002 drm/bridge: Fix a use case in the bridge disable logic - 0003 samsung-dsim: enter display mode in the enable() callback - 0004 drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting .../freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 + .../freescale/imx8mn-bsh-smm-s2-display.dtsi | 121 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index 22a754d438f1..bbb07c650da9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mn.dtsi" +#include "imx8mn-bsh-smm-s2-display.dtsi" / { chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi new file mode 100644 index 000000000000..7675583a6b67 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 BSH + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */ + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <50>; + status = "okay"; + }; + + reg_3v3_dvdd: regulator-3v3-O3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvdd>; + regulator-name = "3v3-dvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_v3v3_avdd: regulator-3v3-O2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_avdd>; + regulator-name = "3v3-avdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl>; + status = "okay"; +}; + +&lcdif { + assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; + assigned-clock-rates = <594000000>; + status = "okay"; +}; + +&pgc_dispmix { + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <12000000>; + status = "okay"; + + panel@0 { + compatible = "sharp,ls068b3sx02", "syna,r63353"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + reg = <0>; + + backlight = <&backlight>; + dvdd-supply = <®_3v3_dvdd>; + avdd-supply = <®_v3v3_avdd>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&iomuxc { + pinctrl_avdd: avddgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */ + >; + }; + + /* This is for both PWM and voltage regulators for display */ + pinctrl_bl: blgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16 + >; + }; + + pinctrl_dvdd: dvddgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */ + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */ + >; + }; +};