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Wed, 13 Dec 2023 22:29:33 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237735162985529 X-GMAIL-MSGID: 1785237735162985529 Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the interface (PCIe/USB) can use this combo PHY and the PHY drivers are different for PCIe and USB. Hence separate the PCIe and USB pipe clock source from DT, and individual driver node can be used as a clock source separately in the gcc. Change the dt-bindings accordingly. Signed-off-by: Praveenkumar I --- .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 718fe0625424..b22643037119 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -28,7 +28,8 @@ properties: - description: Sleep clock source - description: PCIE 2lane PHY pipe clock source - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - - description: USB PCIE wrapper pipe clock source + - description: PCIE wrapper pipe clock source + - description: USB wrapper pipe clock source required: - compatible @@ -45,7 +46,8 @@ examples: <&sleep_clk>, <&pcie_2lane_phy_pipe_clk>, <&pcie_2lane_phy_pipe_clk_x1>, - <&usb_pcie_wrapper_pipe_clk>; + <&pcie_wrapper_pipe_clk>, + <&usb_wrapper_pipe_clk>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; From patchwork Thu Dec 14 06:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178493 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352262dys; Wed, 13 Dec 2023 22:29:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IE2GOPcrjGhc/+qlU5Cxwm6U2YQteOVpqP0/NgJQOI757VBqCzeaDgQCB1xIPbA6z8QOxxP X-Received: by 2002:a05:6808:120c:b0:3b9:dda8:1956 with SMTP id a12-20020a056808120c00b003b9dda81956mr9395236oil.64.1702535394194; Wed, 13 Dec 2023 22:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535394; cv=none; d=google.com; s=arc-20160816; b=woaooGo9I7q4c/XXAf70ACgE4Hpee3/LOM1QUOz1nr18rVqlbJycskrOp2be7SkTAQ C9GWAH3IzRVb27on5UrZ/p/gA6qXW6eVuaqaPEgZwt0AxZr0bFvY7qdFTpFkrqf9dnT2 klXPhdF924/Fx2avAInrTXvymrarU1wgfTFyrPagHLD+rWgPAOWT9ghAjxm1lNMf3xMH xfVBlQFhw5sV/vpOmsdA6FaKvuDhplTADFZj82iBXrvvBHrGyERflFg7BDv7AGRaEhP6 0iizjbD14fe6pymSb4wJJ9Hcgx03zMS4mszdxNpKV8mq4TslPf61tJHsMnXPCK1J+75k 0h/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rl4RrSic2RPILQgcuXsxGN828QIT4dj5tIrRbc9tKS0=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=kZU6hzIc9noXAjpvRS6IfJeoQrrGkcztjuCrgUmnxUrrWYPLgdkskPuRZ3Fic+w6Ze k/jnr9sQvQgf/rwyCEzZ+a2KHlfDsq/cJVd8/IePYRW0DOj1qJsL/8/NoP3dyc8/xfIB y2tSNIfx639GA90EuXclMEBXbTk+eKRW0XSyFQUA9miyK5BGL0FqRtno9vKt0/1cIZf1 0mQVXB/kxkHczUxS9uueYC3OPdI0o4bxMkHcZ7YjJlpwnrGGqmqDHoPGLGPKCkpdoAfI 42/y5YmoQM0kC0Pu9p1X5JM3Zz/TnxbwIwMi9cEo+Y8Pkt5Ge/4ONqv7PZetx6VBF/6O YY3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WFEH4GWX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from fry.vger.email (fry.vger.email. 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Wed, 13 Dec 2023 22:29:48 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237753421868036 X-GMAIL-MSGID: 1785237753421868036 Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the interface (PCIe/USB) can use this combo PHY and the PHY drivers are different for PCIe and USB. Hence separate the PCIe and USB pipe clock source from DT, and individual driver node can be used as a clock source separately in the gcc. Add separate enum for PCIe and USB pipe clock and change the parent in corresponding structures. Signed-off-by: Praveenkumar I Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-ipq5332.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index f98591148a97..aa0f616c3b1b 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -25,7 +25,8 @@ enum { DT_SLEEP_CLK, DT_PCIE_2LANE_PHY_PIPE_CLK, DT_PCIE_2LANE_PHY_PIPE_CLK_X1, - DT_USB_PCIE_WRAPPER_PIPE_CLK, + DT_PCIE_WRAPPER_PIPE_CLK, + DT_USB_WRAPPER_PIPE_CLK, }; enum { @@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { .hw.init = &(struct clk_init_data) { .name = "gcc_pcie3x1_0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, + .index = DT_PCIE_WRAPPER_PIPE_CLK, }, .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, @@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { .hw.init = &(struct clk_init_data) { .name = "gcc_usb0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, + .index = DT_USB_WRAPPER_PIPE_CLK, }, .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, From patchwork Thu Dec 14 06:28:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352270dys; Wed, 13 Dec 2023 22:29:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IHV4tQR9chZ+KQFoqBUtDwBywvL7TaPUM1dLw8Gm7pr6x6LB9lhjL/bX41i9+Ez0cp2U0re X-Received: by 2002:a05:687c:2246:b0:203:27d1:e164 with SMTP id yu6-20020a05687c224600b0020327d1e164mr2346180oab.12.1702535394882; Wed, 13 Dec 2023 22:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535394; cv=none; d=google.com; s=arc-20160816; b=BYl/Nl+LwFIiShXMxdnHLz8eyOovhwH9FIPHrm/sKpmGJPGmVu8Se/NYHZvw0FTJt+ UYHAMTcctRwOOwkSWRerBt5+YG6KI4At6HXkAwSgyO3ptPgdGvnWRUvpKM7eQXWdkLMf OPqaVF5eU1TMmoOfGt1z2FfybG6pNAfqXyKpJjzYlgYjZ9AH+CCyctemo6dz5nBIzwSj aS4GknMLe4M2br30a0+DRaGOsbdfFfent/WEaTWa72iAJn49OCdlq7LzbQMlXapvUwWC r+GLek0DbE+X3VLPY/1m1J7Bur9gsLzhVz12RSsPNpj4+mCVD0t6uCf0i02viT/F+2T+ obUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JQ0nr4FK7OYqVW9xeD0Cq7RjmHvl/L55eTXozHo9UHA=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=fKL5Tsusljf3zdke8qgjVA5XwCuD1YrsTG+Q6O/BJki22ZKrv6a28s5FUHhwOruSo8 DkojI557TG2KoYEmrot+EiwWYgdTR0tIyQZO+dABpkUx3l5apv17/+0wyBnvoxISXpKT R8OrPr1VYD9UXAVL0OuBKQT0DVIjfT3AnXTi2JQcv+mjwUZohpsXQT3rfBnQvt3Hd48C cw+0FHgjhe0+5FGJJgN5KZoygA9CcJNmpxR4VL89QxhJInrzZU5xUCFKjyh8j09jIWkH 8CZVYnXmIr72NorsbZp1DebNEFph/ED6JM888C8/ILEoPDHA7/VelUDQEYddr4yTGLha /Apg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QMeRnq5l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. 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Wed, 13 Dec 2023 22:29:52 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237754253370906 X-GMAIL-MSGID: 1785237754253370906 Add separate entry in clock-controller for USB pipe clock. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 42e2e48b2bc3..f0d92effb783 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -213,6 +213,7 @@ gcc: clock-controller@1800000 { <&sleep_clk>, <0>, <0>, + <0>, <0>; }; From patchwork Thu Dec 14 06:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178496 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352699dys; Wed, 13 Dec 2023 22:31:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IENZLNxOUjekta0Ghz0SnzlXwZ/T52bsgOT6xUusJnEfsDOtYqvv1flgsnF2ewVrRfvXJax X-Received: by 2002:a05:6871:4398:b0:1fb:49c:309 with SMTP id lv24-20020a056871439800b001fb049c0309mr6916006oab.2.1702535461963; Wed, 13 Dec 2023 22:31:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535461; cv=none; d=google.com; s=arc-20160816; b=I4uhQeYpW6U1o27ALqDk0s7WMTV83c66QgumlDdsBQFL8tM6XxShthxbH4vy48G/2+ U76K8vllfHmZxkuSMiCw2tPJtrWpqYr23AQQZCEaEozrAOCPvY4KgwL8lnygY4BOVGPY Zj9pJA84C5sYcW2EQsYqCA3QNcvv9exjfnwiqBWxBhY7VwiSgAHQimMMcPynZc4CIdLc bT0OrWxs8ry4K4Oc2K4RalnMftGYlBwxfH6d06xHcKJC8SCF7yc+yIrY7NXdiveBT3se Jca7ZmV8w/HbVGsN6QeZRuKOnqmRlwui2tcTnWNDvqcZqG0nkFUUbT0+z3qW4W0q12/h KnCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+bJsIiFNHY5aU+4zRAegfGTvThqxKaxMtSO0RkFserM=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=lPq13pAQpV2ZC1k1IVk3ynt39KtRil+sooA7fZR0EsXXjmZlPGu5yz10RB5wd35pyv hM1q9XSmXNZBbVf35Z1Fk/pmklw3Q1j8Z7Q6V08MTrB6JvZ941eCOvI4elVgtuGwV//1 eWaPPpfX23ogyzUuo8Njf+mKOWUuBLej/Hv6kGgwVuaoxhAox21IE7xL50LO95osBhWc nm9Fc3jUz9L7CzCKleAK7SPKax9IPgv9TQXF3zYqI1b0YDJSVWph+or8cpggsfJU4K90 bFG1dmwnOo7ofdpfkMN432nc/fOvZoohpxn1D8Rzo6QOnbErmJtwmtec/xFNt0nYNhDm gXzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Og9FCSyt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. 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Wed, 13 Dec 2023 22:30:09 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237824551443362 X-GMAIL-MSGID: 1785237824551443362 Qualcomm IPQ5332 has the same PCIe UNIPHY PHY with different pipe clock rate. Add support to define the pipe clock rate in device data. Signed-off-by: Praveenkumar I Reviewed-by: Dmitry Baryshkov --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ5018 https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index 5ef6ae7276cf..9f9a03faf6fa 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -54,6 +54,7 @@ struct uniphy_pcie_data { unsigned int phy_type; const struct uniphy_regs *init_seq; unsigned int init_seq_num; + unsigned int pipe_clk_rate; }; struct qcom_uniphy_pcie { @@ -117,6 +118,7 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { .phy_type = PHY_TYPE_PCIE_GEN2, .init_seq = ipq5018_regs, .init_seq_num = ARRAY_SIZE(ipq5018_regs), + .pipe_clk_rate = 125000000, }; static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) @@ -232,6 +234,7 @@ static int qcom_uniphy_pcie_get_resources(struct platform_device *pdev, static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, struct device_node *np) { + const struct uniphy_pcie_data *data = phy->data; struct clk_fixed_rate *fixed; struct clk_init_data init = { }; int ret; @@ -247,7 +250,7 @@ static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, return -ENOMEM; init.ops = &clk_fixed_rate_ops; - fixed->fixed_rate = 125000000; + fixed->fixed_rate = data->pipe_clk_rate; fixed->hw.init = &init; ret = devm_clk_hw_register(phy->dev, &fixed->hw); From patchwork Thu Dec 14 06:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352600dys; Wed, 13 Dec 2023 22:30:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IH320neRxdHzOh6gvHIZrSWmYJjupLHusWqofwsKv6hFcitm50uBRWk+88bZYkOf2scAwb8 X-Received: by 2002:a05:6870:7020:b0:203:27fe:2808 with SMTP id u32-20020a056870702000b0020327fe2808mr2225082oae.65.1702535448113; Wed, 13 Dec 2023 22:30:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535448; cv=none; d=google.com; s=arc-20160816; b=QOAQekOeYn8yB0msb6ILyhC/pJ2+1CuCC0BH4sVWd21D0ISvW30NCfo0hxNim/Ih2Q AeWuDC8svDO5mt1krT5hPbjPtoC/WinUULuDBgskyRnuVL0DJqLBnOZcHYfKLGW8TOCK vA17nPKbrIX+ooSw3cIkfnf0v/y0hNA2eDbTjxf+bihub+IW0BK2SVdIc+4Ssk/+aCqc Cxx0wectB/hm5sLBlYnnj9eJftXAX9A8++YG4eRuHxy9JZTDNgk2bP3L0jg3R3hMy5Bd HlMPC76DUr0u/pw+wbPBw7KYRXVzRohjX2HoB5BGm3XGLZ1aI/pulcCuuOt4OF5j4qsq mfOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=A6PPmlLB6gn91AEx4ASsMIEO3od95Y+EsLFhvi3krTo=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=o3Y5cCsxJCBgb1QAtwCemZKOiiSIN8ioHe+OhvH5uHAinFY/nMf65//2EgRq6Zcdeh 2MwzOPAcwJl8tVh5ATzMxi53tMorAceMP5Tl5rWKyGiDWMXijMWApICbUylN4xD3AjAI yLpPhkTLbRk+A5xO5X0+uiIpEz4JbRfvP/ogd52osgzLwQV7Vjfr/6x7qTYlGGLyXTo4 0kWck1wo0AsZVSgZhcwQyivWJYZjGlIxoxanPZXxcQ1pTVk7HsXOpjf4kl+haCh1wL+S jrFQ/Ao7OP1S7SHPlJHN0KkdO47ISFHhP69/IZ0T0RdpaJ0vjQ81iyxhUSnRKk7Fh2XK hDwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WMvSVRkh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from howler.vger.email (howler.vger.email. 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Wed, 13 Dec 2023 22:30:23 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237810184030453 X-GMAIL-MSGID: 1785237810184030453 Qualcomm IPQ5332 has single-lane and dual-lane PCIe UNIPHY with Gen 3 support. This UNIPHY is similar to the one found on Qualcomm IPQ5018. Hence add the bindings in qcom,uniphy-pcie. Clocks and resets are different for IPQ5332. Update the bindings to support both IPQ5018 and IPQ5332. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ5018 https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++++++++++++++-- 1 file changed, 58 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml index 6b2574f9532e..205eaec2291e 100644 --- a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml @@ -20,19 +20,20 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 clock-names: - items: - - const: pipe_clk + minItems: 1 + maxItems: 4 resets: - maxItems: 2 + minItems: 2 + maxItems: 3 reset-names: - items: - - const: phy - - const: phy_phy + minItems: 2 + maxItems: 3 "#phy-cells": const: 0 @@ -54,6 +55,56 @@ required: - "#clock-cells" - clock-output-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-pcie-gen2x1 + - qcom,ipq5018-uniphy-pcie-gen2x2 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: pipe_clk + resets: + minItems: 2 + maxItems: 2 + reset-name: + items: + - const: phy + - const: phy_phy + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-uniphy-pcie-gen3x1 + - qcom,ipq5332-uniphy-pcie-gen3x2 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: pipe + - const: lane_m + - const: lane_s + - const: phy_ahb + resets: + minItems: 2 + maxItems: 2 + reset-name: + items: + - const: phy + - const: phy_ahb + additionalProperties: false examples: From patchwork Thu Dec 14 06:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352714dys; Wed, 13 Dec 2023 22:31:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IG3JS33zMcZ6MmDnuITsujRgbhoz5qIxFFlhiQs9XZMn45rkwqQy8JgobZGQ4RtcHFlIPzC X-Received: by 2002:a05:6808:3998:b0:3b9:bd7a:3fb with SMTP id gq24-20020a056808399800b003b9bd7a03fbmr14489560oib.53.1702535463813; Wed, 13 Dec 2023 22:31:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535463; cv=none; d=google.com; s=arc-20160816; b=She0ddhrieYDymieotlav/J4smBsaLgEu3xH3QWpFKgMAyFOpIqBz3hs4AgQK3HhFq xGReF6dlAeCqDBTxfvvws8+EJsU85JjpNg8+5O5FBfJ0EB6pw5AQtxdk60lDPC72frBH Z6dYVc+iMwKB2JpPsqPEw0oV9GWfJqFQhA11ofbOtNGh6w4k8zzcRXx5wOxF4bTPuxTQ R5y4WRXm7NYX80poGeI7zINBkJuaB+Md9mYx9F72jBC4deNhBQxgVZC2IFFy4MziBPVb nVNFQLcXzg0oKP28k6smlZNQXuGeSdKfqnh1SkysgVWbGLLayxeh9jM8v/msdZI36SXA u0uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=O/y9Wtug2ck8Z5eDt9Qo1Eos0dLEvEuPtPA3MKLz4ts=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=oM9wHDDFJU2WEUMY06oOqaTXFyyzgq3WYWEduZEZhWedf1rdOXByQvsoJXR3dowTwz 73jjQtFF2tfZj/pakieyJ55w6pt9k0WlT626lpnsK8kBRVpU7ep8M+VQo4lUM20IGIcg N4B4SE0hafd/O+aEQZUNxCVSFMTA288PlUkv2D3Ys5EPTtqU16sKwBU6CHQLlnBMf75R WFXAYjXXiA3vpMxJOxvdwh6+jvgI4qDcu3hEm+A/5lZSRg26VSApBS9zdmWCT0HiUNFN FGZPXJKLhaNuu3CcWZ5Ygp4xE7xfshf44YHCD9u1lOSyN3C6+vOWpnkG0kZb+U7VcKhn uFqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="ZE/b4bc7"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. 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Wed, 13 Dec 2023 22:31:00 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237826607645254 X-GMAIL-MSGID: 1785237826607645254 Add support for single-lane and dual-lane PCIe UNIPHY found on Qualcomm IPQ5332 platform. This UNIPHY is similar to the one present in Qualcomm IPQ5018. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ5018 https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index 9f9a03faf6fa..aa71b85eb50e 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -34,6 +34,10 @@ #define SSCG_CTRL_REG_6 0xb0 #define PCS_INTERNAL_CONTROL_2 0x2d8 +#define PHY_CFG_PLLCFG 0x220 +#define PHY_CFG_EIOS_DTCT_REG 0x3e4 +#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 + #define PHY_MODE_FIXED 0x1 enum qcom_uniphy_pcie_type { @@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = { }, }; +static const struct uniphy_regs ipq5332_regs[] = { + { + .offset = PHY_CFG_PLLCFG, + .val = 0x30, + }, + { + .offset = PHY_CFG_EIOS_DTCT_REG, + .val = 0x53ef, + }, + { + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, + .val = 0xCf, + }, +}; + static const struct uniphy_pcie_data ipq5018_2x2_data = { .lanes = 2, .lane_offset = 0x800, @@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { .pipe_clk_rate = 125000000, }; +static const struct uniphy_pcie_data ipq5332_x2_data = { + .lanes = 2, + .lane_offset = 0x800, + .phy_type = PHY_TYPE_PCIE_GEN3, + .init_seq = ipq5332_regs, + .init_seq_num = ARRAY_SIZE(ipq5332_regs), + .pipe_clk_rate = 250000000, +}; + +static const struct uniphy_pcie_data ipq5332_x1_data = { + .lanes = 1, + .phy_type = PHY_TYPE_PCIE_GEN3, + .init_seq = ipq5332_regs, + .init_seq_num = ARRAY_SIZE(ipq5332_regs), + .pipe_clk_rate = 250000000, +}; + static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) { const struct uniphy_pcie_data *data = phy->data; @@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = { .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2", .data = &ipq5018_2x2_data, }, + { + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2", + .data = &ipq5332_x2_data, + }, + { + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1", + .data = &ipq5332_x1_data, + }, { /* Sentinel */ }, }; MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); From patchwork Thu Dec 14 06:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178497 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352700dys; Wed, 13 Dec 2023 22:31:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IE9kHrKcqaH9z7RpEly7NOk55CUvVgtq+840FAhHlwkjrdZVkbOoKc7elFaF7wjZxFKzpOQ X-Received: by 2002:a05:6a00:398c:b0:6cd:df27:9519 with SMTP id fi12-20020a056a00398c00b006cddf279519mr11031943pfb.34.1702535461942; Wed, 13 Dec 2023 22:31:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535461; cv=none; d=google.com; s=arc-20160816; b=VkoC59j032k5Leuyn+csVSt6/LjxkU+ZzHOh96XPuy4EmeiTb882IBSkZ2EDBbzf9U v1K9ouQapVvCvdTm2IIxDG6tZYmnycjL8yMa+e/vFfGZVzYBMUoqcwkiIspo7qmH3PyZ MmW1tMJTkb+ENMpxOcN+MXpWvf1UYJyz9dqgnSWou+6/ewl4ZG51oaBGhQjvPAQoDM9n jSMywucYYmlywc6SR2jnYEQzwUM76nz8ZgMeX2OkzmHTXNtX+i63BpkrXS1cUNSOY690 On9F8WzMXSBD4QYBTv3ISUd7B6PdKidAHC4zzd5yg2B6+qm/cBNkIYvkWWvT2paVcAbY rByg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RIzgw5CtNpODSCQg6WtMkxWQgree7bxQt0OylqoVt58=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=EsMKrujyPQYhB3PrCvIouyVh1Mp5Y+fsEkOtX+Gpi82Cyh9zWHkDh4lB+xYRQOqoKU BKplMXGLokYLE6djgg8OlOmKrxEx7KO7uuiNPHWNleIRmD3itKw0Fhu5gAJOffTyxre9 02qZmPWixN9uDQyLhwSFU3he0/PP/zRIrgrAXxffjWmmi73wC/X3YVzLhZJnjpcE5y2A GBWIq+RespfOKh4TsbbB9P22i7b1Di08ggs0xsuuy/Cg5yRWWQBpmuvet1DkCB3TGSEd 96ruBimdugxHws3YBLwZd4lzoxzEKrd87ncZBoPjHkcUfyA0KjojdkswkvkbU4cCvmBn /7Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=NHgT5H80; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. 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Thu, 14 Dec 2023 06:30:01 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6U0aU005544 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:00 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:53 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 07/10] dt-bindings: PCI: qcom: Add IPQ5332 SoC Date: Thu, 14 Dec 2023 11:58:44 +0530 Message-ID: <20231214062847.2215542-8-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -Aa4TgoKNCEn7SIisZ3c2z9pAp_XeBZl X-Proofpoint-ORIG-GUID: -Aa4TgoKNCEn7SIisZ3c2z9pAp_XeBZl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 13 Dec 2023 22:30:55 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237824498520382 X-GMAIL-MSGID: 1785237824498520382 Add support for the PCIe controller on the Qualcomm IPQ5332 SoC to the bindings. Signed-off-by: Praveenkumar I --- .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index eadba38171e1..af5e67d2a984 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -170,6 +171,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 then: @@ -332,6 +334,39 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5332 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sticky # Core sticky reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_m # AXI master reset + - const: axi_s_sticky # AXI slave sticky reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: aux # AUX reset + - if: properties: compatible: @@ -790,6 +825,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 From patchwork Thu Dec 14 06:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352796dys; Wed, 13 Dec 2023 22:31:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IEcJz8ayzAJdLt2s+Ehn3I0Z3MjfGRRD5vPYDVU1pD5ExqrGmY5RYKWeLzubGKYGFvv1JA4 X-Received: by 2002:a05:6a20:748e:b0:190:e07d:99f7 with SMTP id p14-20020a056a20748e00b00190e07d99f7mr7981061pzd.15.1702535475089; Wed, 13 Dec 2023 22:31:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535475; cv=none; d=google.com; s=arc-20160816; b=vm5yskcCNXTeSitxy8svmmHXQRTtJ/gTLKrjvs/51Iwl3FMXALPgtT/jODNtO3zECQ y5QBFD1XC/BFAVDMzpXVmF1CqgvwTd4I2Y2AwkPOmuzI/U13lCUkkGMJ4jJQZ+mtGCUI 8bwPmOWViiYyTqeQ6zHWCISOGi5a0lkVTRCBVG0h1r4utuLRVAESynk6CL2sYvglEp5X N2zZnHUUtmcZFmk7T3Tqnja4xYkfrOYwrmW8dl4EyTEOa6BuBiblUtz74TYzXLGATYDF dq7oZSvPBas6H3v5vVaTvKTpiRuSQu/+lavUbr1TbHJOjRtZC82TD6vfNFUKnvfLO1bC S5/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WJr3Nkmd/Qw0LXUgVh1auTrBFZKq1cTU8dUnkpzDrVU=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=dJVKNvFQzdVFB0LsVGUta3eL6O7S4IcmH4YMNhy5L3btcLaLeoAGwwbt34hRw1siPk 00qwHlTrKhEznp2JKiD15Kfps6BJAko6NIix1/yeotJo9n0SuqnHNz2gPFUDTeVTi0Qq TgvmfdJm8ABTEOcyJ5uJtHXfLwxG1+W69LXTDYYeDMIV6MWndxsdSVZy4z+61lCCf5bB 8Te/7wji21d1j9BtOHiW3m1XnZpebZDovqdkz4EwShMuuWYsyS8zWoFO621FgrMIIhiW ZouBqesWJqdrinjwXK8LGZubv6+Ai8VEZMN/zn/u16qRG+RgZNXC5c48pnNRO9m3BdFg ZZTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=c1U2Xg+1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from howler.vger.email (howler.vger.email. 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Thu, 14 Dec 2023 06:30:09 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6U8pt006229 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:08 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:30:00 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 08/10] pci: qcom: Add support for IPQ5332 Date: Thu, 14 Dec 2023 11:58:45 +0530 Message-ID: <20231214062847.2215542-9-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GUaimBjfFoMiK3fyMTlOIKmwFZNFsqnm X-Proofpoint-GUID: GUaimBjfFoMiK3fyMTlOIKmwFZNFsqnm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=958 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 13 Dec 2023 22:31:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237838404124825 X-GMAIL-MSGID: 1785237838404124825 The Qualcomm IPQ5332 PCIe controller instances are based on SNPS core 5.90a with Gen3 Single-lane and Dual-lane support. The Qualcomm IP rev is 1.27.0 and hence using the 1_27_0 ops. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ9574 https://lore.kernel.org/all/20230519090219.15925-1-quic_devipriy@quicinc.com/ drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 109df587234e..3d54de1a71df 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, + { .compatible = "qcom,pcie-ipq5332", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, From patchwork Thu Dec 14 06:28:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 178500 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp8352795dys; Wed, 13 Dec 2023 22:31:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IFfS8Di6XIgdfuwXmT4Mz3iYoxECpRX8/Dxhj0BRlJoEBbWx4btpTS68aBBnbqjhRT0CkLx X-Received: by 2002:a17:902:e5cd:b0:1cc:3544:ea41 with SMTP id u13-20020a170902e5cd00b001cc3544ea41mr10181566plf.46.1702535475096; Wed, 13 Dec 2023 22:31:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702535475; cv=none; d=google.com; s=arc-20160816; b=rWZ0DQO85cIJgihqE8io49OMBwOSyg+vN58X4bROS6j/x9SJm70PzAA+aM29EwoApI 1vXLFb0GRuTNxQVVjvcTCVVBavh1E66qtkf4KkGX9sicrApfdktR3+5n6Mr3zXFZttjA /PabEqHG7+4xR/r6X0cJ5hbhMHth7JcoXySOg6XQSViWz6IQorRi1m0RG+RIG/Cp9h/l DM22eIyYeRTKLmOrIaqiWwzsz174PHNFTw+5fV+G1NSzeVXaxRJhJg1/VfGlsOgkQH1f MOhC8D+TGjyhRS1Pv1711MgG/naEwVM8/MV/Xd9OREGjZP3OXUDBEQb3T+tSUi7fh40R Ym7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TqsYi/GLvr1dtXxkw/HLOJUf5YR9fORp7rKJGaPNwT0=; fh=Rt0kLJa5uw2v8+a6QLzz/XrrVhh9NAe/gnPEpTFc420=; b=Ebh5lr25JtoNF0S9bqsuE+b6hvGexT38DSG4GVtc8NzWJlK81TWxf64q0icUbud0V1 Brl7Va7ToJG9u0bx6Sk281lv5/VdrLQIkaDLaVvyTSbyXSsMA/g1lxmHCgGeBSu0hH+f txtDsePOEr2K1qm8lW0FETLFb6MvPmEZuAE/0dJSB8NgtuxJOnNy+4Ag6QGTWEANKQJQ TQtQ9TGkzApBpJcSoAt6J5IxtO/n9WAaxHuyRPeS90L2CnWeeMU6ww1QcUV9XapTgqYr 9O/VloqOMj6XCQmj9m95K/8bUTSHxPimU39MzRl+8OF+3ZYOvwSFjhLUXoXdSVAKfG3p aozw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=oxHT3je5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. 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Wed, 13 Dec 2023 22:31:07 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237837919800834 X-GMAIL-MSGID: 1785237837919800834 Add phy and controller nodes for pcie0_x1 and pcie1_x2. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 189 +++++++++++++++++++++++++- 1 file changed, 187 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index f0d92effb783..367641ab4938 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -166,6 +166,58 @@ usbphy0: phy@7b000 { status = "disabled"; }; + pcie0_phy: phy@4b0000{ + compatible = "qcom,ipq5332-uniphy-pcie-gen3x1"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_SNOC_PCIE3_1LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE3_1LANE_S_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + clock-names = "pipe", + "lane_m", + "lane_s", + "phy_ahb"; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_cfg", + "phy_ahb"; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: phy@4b1000 { + compatible = "qcom,ipq5332-uniphy-pcie-gen3x2"; + reg = <0x004b1000 0x1000>; + + clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + clock-names = "pipe", + "lane_m", + "lane_s", + "phy_ahb"; + + resets = <&gcc GCC_PCIE3X2_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_ahb"; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x721>; @@ -211,9 +263,9 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, + <&pcie1_phy>, <0>, - <0>, - <0>, + <&pcie0_phy>, <0>; }; @@ -359,6 +411,139 @@ usb_dwc: usb@8a00000 { }; }; + pcie0: pcie@20000000 { + compatible = "qcom,pcie-ipq5332"; + reg = <0x20000000 0xf1d>, + <0x20000F20 0xa8>, + <0x20001000 0x1000>, + <0x00080000 0x3000>, + <0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, /* I/O */ + <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* MEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + clocks = <&gcc GCC_PCIE3X1_0_AHB_CLK>, + <&gcc GCC_PCIE3X1_0_AUX_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X1_0_RCHG_CLK>; + + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, + <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_m_sticky", + "axi_m", + "axi_s_sticky", + "axi_s", + "ahb", + "aux"; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + msi-map = <0x0 &v2m0 0x0 0xffd>; + status = "disabled"; + }; + + pcie1: pcie@18000000 { + compatible = "qcom,pcie-ipq5332"; + reg = <0x18000000 0xf1d>, + <0x18000F20 0xa8>, + <0x18001000 0x1000>, + <0x00088000 0x3000>, + <0x18100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x18200000 0x18200000 0 0x00100000>, /* I/O */ + <0x02000000 0 0x18300000 0x18300000 0 0x07d00000>; /* MEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 412 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 413 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 414 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + clocks = <&gcc GCC_PCIE3X2_AHB_CLK>, + <&gcc GCC_PCIE3X2_AUX_CLK>, + <&gcc GCC_PCIE3X2_AXI_M_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X2_RCHG_CLK>; + + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE3X2_PIPE_ARES>, + <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X2_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X2_AUX_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_m_sticky", + "axi_m", + "axi_s_sticky", + "axi_s", + "ahb", + "aux"; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + msi-map = <0x0 &v2m0 0x0 0xffd>; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ From patchwork Thu Dec 14 06:28:47 2023 Content-Type: text/plain; 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Wed, 13 Dec 2023 22:31:05 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785237838096352761 X-GMAIL-MSGID: 1785237838096352761 Enable the PCIe controller and PHY nodes for RDP 441. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..83eca8435cff 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -62,4 +62,78 @@ data-pins { bias-pull-up; }; }; + + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default>; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default>; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + status = "okay"; };