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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id sf22-20020a1709078a9600b00a1ca020cdfasm7797635ejc.161.2023.12.13.06.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:04:47 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Andrzej Hajda , Daniel Vetter , David Airlie , Inki Dae , Jagan Teki , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Marek Szyprowski , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v6 1/4] drm: bridge: samsung-dsim: enter display mode in the enable() callback Date: Wed, 13 Dec 2023 15:03:42 +0100 Message-ID: <20231213140437.2769508-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> References: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Dec 2023 06:05:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785175850572478297 X-GMAIL-MSGID: 1785175850572478297 The synaptics-r63353 (panel-bridge) can only be configured in command mode. So, samsung-dsim (bridge) must not be in display mode during the prepare()/unprepare() of the panel-bridge. Setting the "pre_enable_prev_first" flag to true allows the prepare() of the panel-bridge to be called between the pre_enabled() and enabled() of the bridge. So, the bridge can enter display mode only in the enabled(). The unprepare() of the panel-bridge is instead called between the disable() and post_disable() of the bridge. So, the disable() must exit the display mode (i .e. enter command mode) to allow the panel-bridge to receive DSI commands. samsung_dsim_atomic_pre_enable -> command mode r63353_panel_prepare -> send DSI commands samsung_dsim_atomic_enable -> enter display mode samsung_dsim_atomic_disable -> exit display mode (command mode) r63353_panel_unprepare -> send DSI commands samsung_dsim_atomic_post_disable Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/gpu/drm/bridge/samsung-dsim.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index be5914caa17d..15bf05b2bbe4 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1494,7 +1494,6 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, return; samsung_dsim_set_display_mode(dsi); - samsung_dsim_set_display_enable(dsi, true); } } @@ -1507,6 +1506,7 @@ static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, samsung_dsim_set_display_mode(dsi); samsung_dsim_set_display_enable(dsi, true); } else { + samsung_dsim_set_display_enable(dsi, true); samsung_dsim_set_stop_state(dsi, false); } @@ -1524,6 +1524,8 @@ static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) samsung_dsim_set_stop_state(dsi, true); + samsung_dsim_set_display_enable(dsi, false); + dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; } @@ -1532,7 +1534,8 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, { struct samsung_dsim *dsi = bridge_to_dsi(bridge); - samsung_dsim_set_display_enable(dsi, false); + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + samsung_dsim_set_stop_state(dsi, true); dsi->state &= ~DSIM_STATE_ENABLED; pm_runtime_put_sync(dsi->dev); From patchwork Wed Dec 13 14:03:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 178040 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7797880dys; Wed, 13 Dec 2023 06:06:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IFDhycINCtlh5JbjJA2TH5bDO25WT/ExNF4wnwX8KDdLPeHTOGB6lZ8Lm8Zcc+tVb8r/rqE X-Received: by 2002:a05:6a00:14d5:b0:6cb:d24c:4a9f with SMTP id w21-20020a056a0014d500b006cbd24c4a9fmr9216697pfu.29.1702476364261; Wed, 13 Dec 2023 06:06:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702476364; cv=none; d=google.com; s=arc-20160816; b=IIqy2cniLRdDbqVuU9/SK/Fwv3q0R8PQWDKQeJmpvT4/ZuU3Lm5wneRNY2xqOjPi2I NYJX1gReeQRFUoNlCoKSPmyBA+FSANmP3tDbYCYFP9BCP7PFJKJr4w4HZmMTIxbSAbUN hfHYYBsgeSVVXXWk7NcqlC+JzKWclrUn70zURpYzGrPnb+Wh2frj9eN90LChqZyrnXVo knLrGoccFWtWX5DJkKsuugFloHkgE34EIvg6sytck01r3/55MkXK0WGysRIKc74YqH2K DnsPxGsxSAfaZrfMZfZ5mJmNK16RNVyRl9GBox0YbwALJ0cABQoQ5/3pIaSVgZYXl6GW pNLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LRuU/Yf3+WOs2/s3BqHchrpBnPmBNhkaR5Vfu/UBGmU=; fh=UPLugLp3TGz/UFnnpIyweeCZZjgZZPvHfi+TCy9TH+Y=; b=nM8CVeDmijakJL6pwWAH1doKEP9NF2QyETdXQ6TGfBwhcITRugFBjcihCdtDTnifvT oj1ps3ynQqNCgHTHWXOPQsM9n8aYVXccpU49TdzlDchPYvNN/tunjav69a3vnzDBvPw+ X5fiigO3/L/JEvT6alsuDNtLm9mJYUF0/8X6OZN7fETOrr07Itlmf6WAVmK04mNjQxhA dKNGh/5SIUUC1PRRcjsyE8sjmLx01MwcNI4LMdtbh90vb3JQsoplVifhyWV2p/M4bzGT nefzv8kRHqVLYuaCa5wLSGAIoHDsJ2+rbdV25G5YzOysUWVqFYGQpsSQSIJ42Y2hB+zd iiWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=FNNo03N4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from agentk.vger.email (agentk.vger.email. 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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id sf22-20020a1709078a9600b00a1ca020cdfasm7797635ejc.161.2023.12.13.06.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:04:49 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Andrzej Hajda , Daniel Vetter , David Airlie , Inki Dae , Jagan Teki , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Marek Szyprowski , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v6 2/4] drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting Date: Wed, 13 Dec 2023 15:03:43 +0100 Message-ID: <20231213140437.2769508-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> References: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Dec 2023 06:05:35 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785175855680273890 X-GMAIL-MSGID: 1785175855680273890 The patch completes the setting of CLKLANE_STOP for the imx8mn and imx8mp platforms (i. e. not exynos). Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/gpu/drm/bridge/samsung-dsim.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 15bf05b2bbe4..13f181c99d7e 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -96,6 +96,7 @@ #define DSIM_MFLUSH_VS BIT(29) /* This flag is valid only for exynos3250/3472/5260/5430 */ #define DSIM_CLKLANE_STOP BIT(30) +#define DSIM_NON_CONTINUOUS_CLKLANE BIT(31) /* DSIM_ESCMODE */ #define DSIM_TX_TRIGGER_RST BIT(4) @@ -945,8 +946,12 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi) * power consumption. */ if (driver_data->has_clklane_stop && - dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + reg |= DSIM_NON_CONTINUOUS_CLKLANE; + reg |= DSIM_CLKLANE_STOP; + } samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); lanes_mask = BIT(dsi->lanes) - 1; From patchwork Wed Dec 13 14:03:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 178042 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7798106dys; Wed, 13 Dec 2023 06:06:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8/hqE86ahgz7OebQaqgfxmL3TNyPW0RQcBHs+ewJ+lRpqjFPv0B4KtbxbfAhfoPDK7fif X-Received: by 2002:aa7:88c8:0:b0:6ce:7e2e:2170 with SMTP id k8-20020aa788c8000000b006ce7e2e2170mr4038621pff.36.1702476379558; Wed, 13 Dec 2023 06:06:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702476379; cv=none; d=google.com; s=arc-20160816; b=znOd2QIVUDtOEGQ4AFyKtWQ4M5NxjUMazA6j2l42oiTCgws2WDA86JzKy0yPgMF+T/ c/N3hrYOVuQP+9xgMBOuZnJrdw/JbQnbvhBXJJ9ndgBfQkF6uAQQTYAluS+B8wd8q94w EhPM4rlWkrGNSk8q2/IlA0KTD719+V37fD+wTXaHbt9U1R8IyxwbecRLxJPemaJdyTaA 314z/+qvPK1yHukwD6KPjoUDHibzUbI8rXTQHGvfzipSJrrHB9/ErDryiufJJE9gphsr UMQM56JKtxlQqIxeMNyvoA0TwNFRG/jbXzFkbj6nLUd46gHDiKFaLAIMbSf6sklgXWJv h41g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9dqXlBbcQt0R29oSjxr4jyi0yptqDX27ArBU37Ndav8=; fh=lgOgPSzyjowhGzwYowBR9Ne0BQfivme3yzjOKE5KM0w=; b=BbavhN3Q1BA40IViCrW1PkDQKnZ2osaLJjRkooft90jZp6xuIQEmZCBZFqm1y1J8qT WPK/VBYWLi+V/UIPo645o2IcyRQAcg+mQ5KRXZ8Dn4NR98jLZ5A5IVE4pNTtwNvaBGrW c501JjQnSLpXjYERwSmALKhliKCr44Wg1X8NxEhYcLjbzwV4Me7uVRJVJXLxaleuKBL0 v0e5LpTW6+Ls0sWSbY7iOZbppJ7ySPO4l3Ow+iyN5LIXXSXinR4kOS73wbu6rZiZ7Lxy DL+KxZ5SBPg/GiJjQRyvelh/UIUaeOD3CkCkYAkp++nLPCa9JEdM4nh7AfPKIPV3QGwJ 3pcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kxbvaXSF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from snail.vger.email (snail.vger.email. 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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id sf22-20020a1709078a9600b00a1ca020cdfasm7797635ejc.161.2023.12.13.06.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:04:51 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Krzysztof Kozlowski , Conor Dooley , Daniel Vetter , David Airlie , Jessica Zhang , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Rob Herring , Sam Ravnborg , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v6 3/4] dt-bindings: display: panel: Add synaptics r63353 panel controller Date: Wed, 13 Dec 2023 15:03:44 +0100 Message-ID: <20231213140437.2769508-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> References: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 13 Dec 2023 06:05:37 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785175871756273325 X-GMAIL-MSGID: 1785175871756273325 From: Michael Trimarchi Add documentation for "synaptics,r63353" panel. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- (no changes since v3) Changes in v3: - Add 'Reviewed-by' tag of Krzysztof Kozlowski. - Replace "synaptics,r63353" compatible with "syna,r63353", as required by vendor-prefixes.yaml. Changes in v2: - Add $ref to panel-common.yaml - Drop port, reset-gpios, and backlight - Set port and backlight ad required - Replace additionalProperties with unevaluatedProperties .../display/panel/synaptics,r63353.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml diff --git a/Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml b/Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml new file mode 100644 index 000000000000..e5617d125567 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/synaptics,r63353.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synaptics R63353 based MIPI-DSI panels + +maintainers: + - Michael Trimarchi + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - sharp,ls068b3sx02 + - const: syna,r63353 + + avdd-supply: true + dvdd-supply: true + reg: true + +required: + - compatible + - avdd-supply + - dvdd-supply + - reg + - reset-gpios + - port + - backlight + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sharp,ls068b3sx02", "syna,r63353"; + reg = <0>; + avdd-supply = <&avdd_display>; + dvdd-supply = <&dvdd_display>; + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + }; + +... 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[80.182.13.188]) by smtp.gmail.com with ESMTPSA id sf22-20020a1709078a9600b00a1ca020cdfasm7797635ejc.161.2023.12.13.06.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:04:52 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 4/4] arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup Date: Wed, 13 Dec 2023 15:03:45 +0100 Message-ID: <20231213140437.2769508-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> References: <20231213140437.2769508-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 13 Dec 2023 06:05:39 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785175863927165472 X-GMAIL-MSGID: 1785175863927165472 From: Michael Trimarchi Add the display and nodes required for its operation. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- Changes in v6: - Drop patches: - [06/10] drm/panel: Add Synaptics R63353 panel driver - [07/10] dt-bindings: display: panel: Add Ilitek ili9805 panel controller - [08/10] drm/panel: Add Ilitek ILI9805 panel driver - [09/10] drm/panel: ilitek-ili9805: add support for Tianma TM041XDHG01 panel Because applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-next) Drop patches: - [01/10] drm/bridge: Fix bridge disable logic - [02/10] drm/bridge: Fix a use case in the bridge disable logic Because they are wrong Changes in v3: - Replace "synaptics,r63353" compatible with "syna,r63353", as required by vendor-prefixes.yaml. - Squash patch [09/11] dt-bindings: ili9805: add compatible string for Tianma TM041XDHG01 into [07/11] dt-bindings: display: panel: Add Ilitek ili9805 panel controller. Changes in v2: - Adjust the mipi_dsi node based on the latest patches merged into the mainline in the dtsi files it includes. - Added to the series the following patches: - 0001 drm/bridge: Fix bridge disable logic - 0002 drm/bridge: Fix a use case in the bridge disable logic - 0003 samsung-dsim: enter display mode in the enable() callback - 0004 drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting .../freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 + .../freescale/imx8mn-bsh-smm-s2-display.dtsi | 121 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index 22a754d438f1..bbb07c650da9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mn.dtsi" +#include "imx8mn-bsh-smm-s2-display.dtsi" / { chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi new file mode 100644 index 000000000000..f0a924cbe548 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 BSH + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */ + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <50>; + status = "okay"; + }; + + reg_3v3_dvdd: regulator-3v3-O3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvdd>; + regulator-name = "3v3-dvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_v3v3_avdd: regulator-3v3-O2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_avdd>; + regulator-name = "3v3-avdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl>; +}; + +&lcdif { + status = "okay"; + assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; + assigned-clock-rates = <594000000>; +}; + +&pgc_dispmix { + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <12000000>; + + panel@0 { + compatible = "sharp,ls068b3sx02", "syna,r63353"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + reg = <0>; + + backlight = <&backlight>; + dvdd-supply = <®_3v3_dvdd>; + avdd-supply = <®_v3v3_avdd>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + }; + + ports { + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&iomuxc { + + /* This is for both PWM and voltage regulators for display */ + pinctrl_bl: pwm1grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */ + >; + }; + + pinctrl_dvdd: dvddgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */ + >; + }; + + pinctrl_avdd: avddgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */ + >; + }; +};