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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:12 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 1/9] riscv: add ISA extension parsing for Ztso Date: Wed, 13 Dec 2023 12:32:57 +0100 Message-ID: <20231213113308.133176-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:33:57 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166295528819325 X-GMAIL-MSGID: 1785166295528819325 Add support to parse the Ztso string in the riscv,isa string. The bindings already supports it but not the ISA parsing code. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2438d4685da6..3b31efe2f716 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -84,6 +84,7 @@ #define RISCV_ISA_EXT_ZVFH 69 #define RISCV_ISA_EXT_ZVFHMIN 70 #define RISCV_ISA_EXT_ZFA 71 +#define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dc0ab3e97cd2..3eb48a0eecb3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -279,6 +279,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), From patchwork Wed Dec 13 11:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177924 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7707189dys; Wed, 13 Dec 2023 03:34:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IHvhiZ9BGsg/oGY4CCJI1irStxmvfRwSZYOYQ3xFX4rY8RvZJTck6K6mO3th03L5d64GKX/ X-Received: by 2002:a05:6870:7b4f:b0:203:2e29:1ee6 with SMTP id ji15-20020a0568707b4f00b002032e291ee6mr368418oab.31.1702467280082; Wed, 13 Dec 2023 03:34:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467280; cv=none; d=google.com; s=arc-20160816; b=eep8dziNA8/u8FepCyDIw30gp3WJ11bWZuL50R3rbvlAxiBekQ0r/LHE6GeeouBjdl 8MqckHhfg7KJEF7XNY++MPa3zA0Gxo/DgtdFSBDKnQ9Ys/eqzPGc9O47InFye9tzVTGg 7pmO2RCT2sakFSv2028drIFeCWEhucsqgkD4y8UgQpc1lYoDennMyte2qp2alwyBep6s nEOKMulhZ32oc5zDXzRotm36zSWBUQhGNLWLnumAvGpunXr1LuGhOheO1rtZ67jBE/yW wSta63F+uSLdIu3xNqDItuX/aT9Vzbqb/jPZkdDJiZv5kd8iP/IWeAic5uy/9Y/9RMOy BBBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fxiI83AWHviDA1K2goPpANE3T3h3Nt6zkBhZOZxUOr0=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=xKsWdHo8e3cuVYlbbqmMtP1IjrXnl4qV18cs3Oilif2YlP7W1Yux6Zi3VNuNkJ0IEW w+s712adQOefVx8r/TOEPuIyTNps9tdmFtl2v2YyIsQoS+DWCqmdOEYDwikQFwvnCI+n e//eeJuDrywYTNo9URSrC5BuqyHuP3nontnOiAw2DQu/qF4MkRQucuBosbDsdEr8vO1b x1EexE8N2ORz8mP02fg2IZfh9kkcaVy1nh8wlZfhaOeNmudF0lPiUPbQhA2Z0RMKcspW dsxl2B7dSBupJKQM0PGmijGg2ZEkvqS2iooXxsH00TzE5AOubSFlJZUXMkfpQeK4XTzK 3MCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=wRW7vS6m; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from pete.vger.email (pete.vger.email. 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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:13 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 2/9] riscv: hwprobe: export Ztso ISA extension Date: Wed, 13 Dec 2023 12:32:58 +0100 Message-ID: <20231213113308.133176-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:34:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166330749860771 X-GMAIL-MSGID: 1785166330749860771 Export the Ztso extension to userspace. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 41463b932268..10bd7b170118 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -161,6 +161,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as + defined in the RISC-V ISA manual starting from commit 5618fb5a216b + ("Ztso is now ratified.") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 91fbe1a7f2e2..01ac3dc196e5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -56,6 +56,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f0bd7b480b7f..6564fa9e7a7f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -174,6 +174,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSH); EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); + EXT_KEY(ZTSO); if (has_vector()) { EXT_KEY(ZVBB); From patchwork Wed Dec 13 11:32:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177917 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7706904dys; Wed, 13 Dec 2023 03:34:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8O5wAkT9S7XCY8WA97C0LcgDgVr+16IPzxFBJY5GfKLz05Wqid70HtSZR418DtY/4+Rzc X-Received: by 2002:a05:6830:18f0:b0:6d9:a1c5:7d7 with SMTP id d16-20020a05683018f000b006d9a1c507d7mr7487538otf.57.1702467245447; Wed, 13 Dec 2023 03:34:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467245; cv=none; d=google.com; s=arc-20160816; b=MwNc2+mjGJ/NdmyleE+Och5F8/Y2vJ+qbQwq+KcbfNUXHBT9FMYM1mXs4RewC6VnMa y7X5ZxM2zCKZRvEPp05UCcuUAs/sYY/JpW268Jlky7sMUuLtUZjx4pcrcPP8dLrM37N7 9oiGrA8EfRtN6z9gePFhLGIn7GdXRRoz+KA8Kv2ozdo8/254TrKJSLcxUwduy+j1bKOt BE5GwrMeijWLhW7s2LqS9R4G6b2976LIm14SsxPB0f2mgOHccR6slpDrODObtJNEDyWX vlc/3XvqIjd80ngzTk7Prmq1UZDM3l6UvIZPq/6MD/iudLvLbmR6aDC4CgXkIROGsyMk DYgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bstEpC4Wn7eojNR4ey8qLYKe/MWWQca3CdSgitFw4Fg=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=XgkAR+fNlyEElETcvnXJZJGav7ruEqULNeWX2nsem1dfCYjDyKYCnmrWtEr5rcaVsc luQ71hEefh3FtKljUd6N+LkAEmkiYT9UHVQ5GQ02p/bDhkl305QTvOZM9Qn5+A0RKG9g 7sNoSFBE/C/ZOQ1Gc//6mCMZ+jjmQLPVO5R48JdyYxPg/DPjX2uPhXJQINdiOS/g1xQK 2mAy9tBX4/xjl4KdC5bnTQnz3wT2JMeCUxXMXq9U177OSfkP1lQbKKCtaXc9v7NMBx0B ZqIEoopXFjRjNSrDzyKQ/QXOBwa/O8+9oA2JylnMrDGxZW7bh2g5nVqn94x0guJKb1eA HfJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=RC0pQrg+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:14 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 3/9] dt-bindings: riscv: add Zam ISA extension description Date: Wed, 13 Dec 2023 12:32:59 +0100 Message-ID: <20231213113308.133176-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:34:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166294078169490 X-GMAIL-MSGID: 1785166294078169490 Add description for the Zam ISA extension. Signed-off-by: Clément Léger --- Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 3574a0b70be4..912cc6a42eb4 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,11 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: zam + description: | + The standard Zam extension for misaligned atomics is supported as + ratified in version 20191213 of the riscv-isa-manual. + - const: zba description: | The standard Zba bit-manipulation extension for address generation From patchwork Wed Dec 13 11:33:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177920 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7706988dys; Wed, 13 Dec 2023 03:34:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IH4LDpfcHVvf8zTCV9BcOs8Gviyh3rd/OnzX5ovhrmmeZPONoGQJfK2w9mK7N5WRWhCBsca X-Received: by 2002:a05:6e02:1587:b0:35d:59a2:a336 with SMTP id m7-20020a056e02158700b0035d59a2a336mr10858120ilu.56.1702467255794; Wed, 13 Dec 2023 03:34:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467255; cv=none; d=google.com; s=arc-20160816; b=mT3puID6k1/SpKm0Qw+Ztzb1quBkJ2ao1A1G9r/p3X614wdhmja3lFQHcY7lpBaru4 R4/qiPVwjNdCsEAlNldOIsD53OMC/rG8hFe5VW7SMMNFDSq25muF12F9PmqdcXr0RlmE hnbdCtjZBnbUTUZwpB+I3+U3VjOu0KjgCrSkNWjYLrEQpNVtf5dTOJQbAJta7Qo5ma8s UmvlT5ZoIRQJAOGgkOE0cw94CwgSoC+ah74Iv1+A1GHOuUcBwz72GOlDTbDckc5FkrQy ReA1uCkysW0ztyVdf/wefy9+g7VM0DRBJiAfPmXBilPrgn+ealrNv7HGI+O1PsEWIAS7 cD4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zJ7qFvLPI16XitLVU7jac70czdbEyCJmCnGlh/kcFn4=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=kEcfgMAs5pJdj5JCpnAS8tUniDQC+whlDS6pSjGr01PtzvF/IPowVEdEYIxp5BobwI EROF09vtF3sN5TVqDF0vNMGBOI5jy5uw1+sMBat8x0Eg7V/8jODgeKFy93xLi9fuuf9r KzTfQPk7yLfhYmCpn5hMMnRaeSwn1hWtfyruHajO55gE3DVIc+6uvZgcAEftLTCRpqEZ U5hV74sujdjHg44d5dSdS4VNevLD2GLHQXgEn4vQSmvROqypKFIqPOSNajK2c2LiDDr5 jjWWlXJhBcvCzyEMb4Ul4aSnByDQOa6pOdyWpOfsYVRZCJLZlEwnPaijUl2+THvHBvuX 3VKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=ldWMEEcs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:16 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 4/9] riscv: add ISA extension parsing for Zam Date: Wed, 13 Dec 2023 12:33:00 +0100 Message-ID: <20231213113308.133176-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:34:12 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166304692462477 X-GMAIL-MSGID: 1785166304692462477 Add parsing for Zam ISA extension which is part of the riscv-isa manual but was not added to ISA parsing up to now. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 3b31efe2f716..016faa08c8ba 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -85,6 +85,7 @@ #define RISCV_ISA_EXT_ZVFHMIN 70 #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 +#define RISCV_ISA_EXT_ZAM 73 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3eb48a0eecb3..e999320398b7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zam, RISCV_ISA_EXT_ZAM), __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), From patchwork Wed Dec 13 11:33:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177919 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7706983dys; Wed, 13 Dec 2023 03:34:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IGFLxAMtR6ClCYKQiZFq6in5zPtW2oqRQvbArOXFHgwONRoqztWjx14qI26jrX90Lpw9Akw X-Received: by 2002:a17:903:1206:b0:1cf:d07c:2806 with SMTP id l6-20020a170903120600b001cfd07c2806mr4489960plh.25.1702467254671; Wed, 13 Dec 2023 03:34:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467254; cv=none; d=google.com; s=arc-20160816; b=Kl3/4T/SIgIIsS9kMpU3dTIinVXAnvRnsMpZd3llvusYTnp41q50AyCVnA9vaEiBcs uMRaj7x7egYXHfWzKeUEevhtvG+E3wevKHuaUxt4x/v+lZw+bp+Zw5gSoPdqEzL0sivu NcTFvrkX62viDnzbAXvfrZiYpu28+/fK0J5Nekp9axiJTdFNZkvA3L5xPbgygxThz+Xk 6I2xjvqh5fHqnC1Py68/1lAqODwBWTBKSTDCXjgyIFCm2BrqutY8heMpWNXITQBviLXb ZgtiMDdMaPNaUMeVmN8/bekc4UJQdDTjQhsdpNHiWgMY6y6lVJ9Ye31ACr6z4shy/7+e C5Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N3Huv5MEBJaGZczqd/5TE8MmVw2Iifvm3SE9MHyvArM=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=RNYVitIxXZOt5q3MASCfWFGxVyhbBg5dSGGfY78A+lQphZsCZxADbZG4LpyU5tDlBb WvXVfTTk2e/NKd3/LeKDBtqKDDn/Vk9LYsQzuhKd5qK/XQKDEGo42ArI1ulHNKTi8pmW Y6hscufwRNBynB2y4uwnb9kEg1GC+8BkhgKZpR0Z1b0aFXKiHSKNX4/E5g7JoJb1FAgS s0U0z2x/+hJkccJlXKhNl9juAEF2n+SkSlMcqmFAP4jT5O3hZhX9rUb+iY8fCuTh1NdC loZ5dWHq+scsfh4olzZjhWTkfKIwyvD65EdlmVKdSnL2PEdWS/dZlaUXeddNsysRn2Kn ehMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=Oly2hJhI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. 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Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 10bd7b170118..9b19ca3433de 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -165,6 +165,9 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") + * :c:macro:`RISCV_HWPROBE_EXT_ZAM`: The Zam extension v0.1 is supported as + defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 01ac3dc196e5..2350c45741a6 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -57,6 +57,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) +#define RISCV_HWPROBE_EXT_ZAM (1ULL << 34) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 6564fa9e7a7f..a8473d7f9d1e 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -175,6 +175,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); EXT_KEY(ZTSO); + EXT_KEY(ZAM); if (has_vector()) { EXT_KEY(ZVBB); From patchwork Wed Dec 13 11:33:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177925 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7707365dys; Wed, 13 Dec 2023 03:35:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IGrVP4I0tvyfLm0oiqFDi0W3UQ6Ec4PqetJbx8S5h7Tx/JE8X2QZyhGpLMfTNS5+eP5uEW8 X-Received: by 2002:a05:6830:6e18:b0:6d9:cfd6:61bf with SMTP id ec24-20020a0568306e1800b006d9cfd661bfmr12476428otb.18.1702467300130; Wed, 13 Dec 2023 03:35:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467300; cv=none; d=google.com; s=arc-20160816; b=NLPXXmU4B3L9EIx6cSPb1Ef1FP/1acaAM0nmueO1G1wehjbCQCxJA+fsXY43HMtBrf 69yJWzQIzF4WXRQEo2PnFCiCzV34VNUJzJnUr5jLWmeD45Y9D36+OT3XRx1vUQ4yXmZq TwF7ZYYzy4WEsspR46JmO2JrbctQ/HKreJCZ8ceVI5gGnDe+Qs5YLRhb4Vd8SZReCdle TQYpMTa3+8+xpGOPNynJx1bGXOWpDx1NEveJUWDq6FKHzlWkl61b3iuUWbn6LErSBEgh dboul1VSxjhpeSSwxwJaVtcE0WF7yncNZuAroebqyry2NqxObEEfqNNUnW/0e3A6dVUN d8/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nWX/zjp+iAoc0sTO0EE360u/fHh1vFE2puPVRvnlJSg=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=QO4q91fLSrk0mOpsGG/q/f4mtgCcYD/BDDVcmFVsVbBjAvuyMjt/1XxM4s7jt2oQ0r rVsOEtT9XtedcNNbfNs7xPzCQb/E7KDuyG1OL4dcXDdLidL3skL9sGzcrL+o3TZULUIF x+oREKzM4QODncAXddnUzOhD3gBVq0/GkA0PXazHcPFJEMWN8SlCDfR0vz7j2u8b8EwP U5OHYhtpXKpr6Zozp3SaM0djDPfMXlvfQa0uP4rehwNnuSjkli8mHFh7RVTcbq3REh2i 03Gpse5M3aUCwRFeukN9LUKue5RJ78Xwve67sVOksn7UEQISAgNeGYPU7hNDKO+qzqbD Jvzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=QqJV3DhQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from pete.vger.email (pete.vger.email. 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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:18 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 6/9] dt-bindings: riscv: add Zacas ISA extension description Date: Wed, 13 Dec 2023 12:33:02 +0100 Message-ID: <20231213113308.133176-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:34:52 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166351635140582 X-GMAIL-MSGID: 1785166351635140582 Add description for the Zacas ISA extension which was ratified recently. Signed-off-by: Clément Léger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 912cc6a42eb4..264114fa943e 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,12 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: zacas + description: | + The Zacas extension for Atomic Compare-and-Swap (CAS) instructions + is supported as ratified at commit 5059e0ca641c ("update to + ratified") of the riscv-zacas. + - const: zam description: | The standard Zam extension for misaligned atomics is supported as From patchwork Wed Dec 13 11:33:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177921 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7707003dys; Wed, 13 Dec 2023 03:34:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IHhlJ4Puh1o592l8k1dULqzKRZqaIJJkP8Txe7ptj3Gexm1vIUYfwG/dCV5Cx+VtJjiS48U X-Received: by 2002:a17:903:234c:b0:1d0:c418:1758 with SMTP id c12-20020a170903234c00b001d0c4181758mr9425616plh.66.1702467256621; Wed, 13 Dec 2023 03:34:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467256; cv=none; d=google.com; s=arc-20160816; b=g6P+jBf/G5p3KbllhzKEwbO1z+nf+1nTrrVWZqY0ELX4MGaRngBgQsLY7lQX0CkWyP tFh2yA/T1yJOFLV339gZaiZlEPV4UvI/1LI2vZ66ntnsNmgDbcoZXef2UMla4JDghWEH Xa+385EVN3Pon5gfHZteXOFrK+TPL4Zqm53h0yptNEl1UV/rQQpI5ohCi+G5Cixgn5im mJ19JcxmQ6h/j1SfBwipxKcBSYuThrHhuce/tGOBAjTSQzzUWwLH5PL4AAmmoOMVdZZE gaItdCcLhFkmJBGUSNSKmm9SSIrkyjS2nKvMDtv7S/AnmLah7P6YLT/m4bmjOmr0dEIM fz6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NSyk12PGgNh6ZiEbOULW7RPQKbPPPMGsxhdUj3Rl3fw=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=FGd6d/Q5AxgtbyXm9gtJT8NBBPUVxh64pEKeWHRdG6Y6ZK9+ohQbcDLf7D8fCB5cAY AtQUyv0IHBfiqCQUUUsAeqOlMzO+uFy099udOYxSO7XI87HTvHqYI01Ts7We41W1xtu6 zDQ3E5GZtY3WOLxUBV90lKt9/M/p/R2t2v3T+sIQMxt3N7VpY2qSKyTFfvQ3k/+10/EQ ekznmdT5BayTGlbnKeXtJKDoD5k+5Xvv2dV5v/nnmRgZxqUVowtniwj+QFEh7F8+weu4 GqhlLhgB6jbsBNi/mDlcT/Fc/JQqftNgKQ3aGPekzqs+nJfxIxsSyb+Ty4sSdHp3Hn20 2S7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=dbtjg5ig; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 016faa08c8ba..8aee032f092f 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,7 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZAM 73 +#define RISCV_ISA_EXT_ZACAS 74 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e999320398b7..62443cd632b8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), __RISCV_ISA_EXT_DATA(zam, RISCV_ISA_EXT_ZAM), __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), From patchwork Wed Dec 13 11:33:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177922 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7707043dys; Wed, 13 Dec 2023 03:34:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IF8q5Q+N5pwst2GtjAlkrDVKwgMcsL60emImRgRN5fBrrdarqr01uhV2Zx6Gp0G0/J8qzYp X-Received: by 2002:a05:6e02:2142:b0:35d:7b57:2294 with SMTP id d2-20020a056e02214200b0035d7b572294mr12828522ilv.32.1702467261753; Wed, 13 Dec 2023 03:34:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467261; cv=none; d=google.com; s=arc-20160816; b=rK8gp1bCWBtAvjaB8qCqSOyXPSguG8FSSKM9W9NLVqEiqYgJxV4V0HZhhtWMfufD6l 6rzrA/55Eh7knXDEM03YuRHjSLJbPBGlN2IAZh+PX4bRaWC2Ud9SS04H2SmnIpahAsT6 KSu8+gfPzpdPmVxzrtN5q9L+aZw9JlE8WwCW6mW73QnG+yyosq58o0LL1REhpMtegDzW e2frGPMSoMoVPvZQaJaLPMz50QAw+nDCk7Ile1Ga7musHfKa9zi0dLiY2HbE6ad8o3VD DDA0mzRsREHRZJ7ah/HgmJLHk0YJctfAlN1ogPTFZApeidq3CT6QrtRtmuazWbqnCSQ7 ZzOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OT3PabJ+SN8OyyxUlhRHLBK2j0fBOpZosf39djft3/Y=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=lb1JLyQL/c988OQITkuKEbqEGLgBISQLxoVlE+vog6enGarygUIzKM2DEPT61eVaUA c7ITAImUNFL/BLHVLFXa+cHAxYdLZeWrSvvNiizcwj1C03dTQOMpAsncA58WF0yVM+LF EVcl3j/0gUT4+8wneH80NKc3txajSrtncOJjOVYgcw8ndnGzp47AE6a1ATXZ3LRGi3e/ eeDe/tHurjesbsrIk7TcVYo8w0Brif5GjTl+5Np243bzzAgeqbD7vF/XeB1wcOKWGaTn WO1p7rq7TUdOM1LkNgX+Qx3/bDKkuHo1Ny/uEFwcmjFnj1eWhxwUFl08pne5GBF17d3e XrVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b="IUo7/JGk"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:20 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 8/9] riscv: hwprobe: export Zacas ISA extension Date: Wed, 13 Dec 2023 12:33:04 +0100 Message-ID: <20231213113308.133176-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:34:18 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166311643776813 X-GMAIL-MSGID: 1785166311643776813 Export Zacas ISA extension through hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 9b19ca3433de..510e49878834 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -168,6 +168,10 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZAM`: The Zam extension v0.1 is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as + defined in the Atomic Compare-and-Swap (CAS) instructions manual starting + from commit 5059e0ca641c ("update to ratified"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 2350c45741a6..7ec4331122e7 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -58,6 +58,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZAM (1ULL << 34) +#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 35) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index a8473d7f9d1e..abb0eea3ee08 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -176,6 +176,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIHINTNTL); EXT_KEY(ZTSO); EXT_KEY(ZAM); + EXT_KEY(ZACAS); if (has_vector()) { EXT_KEY(ZVBB); From patchwork Wed Dec 13 11:33:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 177923 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:3b04:b0:fb:cd0c:d3e with SMTP id c4csp7707051dys; Wed, 13 Dec 2023 03:34:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IEhCIMVT9RJhawmKa2CtS826m6xGqkVR2Mfge5tOz6DD+FYU7CyXOtdcKXxYkL7c2Xr9Vpa X-Received: by 2002:a17:902:d4cb:b0:1cf:c329:6204 with SMTP id o11-20020a170902d4cb00b001cfc3296204mr4115571plg.14.1702467263029; Wed, 13 Dec 2023 03:34:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702467263; cv=none; d=google.com; s=arc-20160816; b=D727kfbsHOuToDAzFa2bIx6KSG3+ZbX8ndhCAzu0Xzdw4BOe5HffXDklMGkUNs48Jb gop8tTxSJDXflkGG03uD6dOYGwiPOnssU9LzDAX9GwBmL6zBKHSUcMlrfMRKmQrjXyth KN3EmiukXshjhA+nhyOiOPV5NAKxnryCmXyXjaPanYAR/25vOMqMXaIt7eUbTIOIXyrB oThONMXOJ1VP5NAR2cekdjW0JdL2Y0sZEvOCW0iiMlnZmm3+VoGRpDpGvcWAW3/fg2qT gp3Kqk2eLFRsRA1LU2yymHLXO+gVX4Hbrq2yxHBqDdTVp9qV8VcVhLV29GZJZ5fAN8bI JPLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KKPObWVuIFXSRwOfIm7U25jwf++f1sQGlTYA9JTEt2I=; fh=xetE2tvUj4KVv4Y1ULtLdPNUjx3CE50rVjiyrCzTN7A=; b=OSYKo5aLrxeoQ9Lia3fJw7Su69sd4wmZAvvVXOImBY7Tp32GYpfoZxf5QLX0osl2LB zDO/1mWunkxz+JC9CcEeeSPjfvKY0wp8yCm0PKTeqdImh+CmiWddoBb/PHukScqMvNH1 IGI1vUaerwfGKuVX/ZdqZLQ3+bmiSIfcstdTPw+nhFdUf+x8qeU4BKlUXw7bEpnfANxm ecn3IR24qONsCcHITBxm28X6yePiLLJLIr0b1vGXny7xkls7/CczFgO54tRiy06r3273 DLmrYdWnCg6F6DTlZvnL4GHWhPUBjh1HVMpFJhZ79mb9SDTR/c6eHF93SRySUVhh2oe3 iecw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=RfzSBK9S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:21 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 9/9] riscv: hwprobe: export Zicond extension Date: Wed, 13 Dec 2023 12:33:05 +0100 Message-ID: <20231213113308.133176-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 13 Dec 2023 03:34:22 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785166313030539208 X-GMAIL-MSGID: 1785166313030539208 Export the zicond extension to userspace using hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 5 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 7 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 510e49878834..a42c3b5d6bc3 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -172,6 +172,11 @@ The following keys are defined: defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as + defined in the RISC-V Integer Conditional (Zicond) operations extension + manual starting from commit 95cf1f9 ("Add changes requested by Ved + during signoff") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 7ec4331122e7..4287aa391cf5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -59,6 +59,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZAM (1ULL << 34) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 35) +#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 36) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index abb0eea3ee08..d94f11534efa 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -177,6 +177,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZTSO); EXT_KEY(ZAM); EXT_KEY(ZACAS); + EXT_KEY(ZICOND); if (has_vector()) { EXT_KEY(ZVBB);