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[23.128.96.36]) by mx.google.com with ESMTPS id s16-20020a056a00195000b006cdfca5f4dbsi8741806pfk.106.2023.12.12.15.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 15:51:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=fail header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=S7CJJiQe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 23313801BB76; Tue, 12 Dec 2023 15:51:19 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377498AbjLLXvI (ORCPT + 99 others); Tue, 12 Dec 2023 18:51:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377507AbjLLXvC (ORCPT ); Tue, 12 Dec 2023 18:51:02 -0500 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28946BE for ; Tue, 12 Dec 2023 15:50:55 -0800 (PST) Received: by mail-ot1-x331.google.com with SMTP id 46e09a7af769-6d7fa93afe9so4607796a34.2 for ; Tue, 12 Dec 2023 15:50:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1702425054; x=1703029854; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bp9tJj1SA2bMEiEs1rPeqlO2QZ9OUerkC/ZIE58TG2c=; b=S7CJJiQecN5gJhEqxLA/wZb/buP73t1Q5veqBJUD38KyH2gGXp32vGBlNdvkFbAXgl /IlGziOZmxD/hpbLCx3YYmNRleGZolg1C1/Yy5EOtxq5VkuYi7kXuvqMkdAC8D1td9vL F6OCl+zYDml/lTwBx2p7MvEY6RgJBlOl/pjITbPdRvPWWiyAAlYOZwgvNBMkaorS0zlp PItGV5x8emhMmQa44Bbq5DVq9rLs5awroxUG97IpUnDvhN8rVk7rwNS2UC9UfZ0fZiRR 1ENpeu2c9UlQK1F31T+qSbYpi48s/trLsE8FHpl9B82ikFZDNMSouEG1fAFFY6lCtaPB FvTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702425054; x=1703029854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bp9tJj1SA2bMEiEs1rPeqlO2QZ9OUerkC/ZIE58TG2c=; b=ZYy7U/FsU37qIAo03woVKpVOvEx2pJUpufU73dUcHstry+uA/Y6PVOImSwefLbYgJY xBGrXJ1bDH2EpPM37E9FFFF4Lllz7XxPgocztwRNNPViMnHhElZiYjb5ZVyvtfAE7ATn pmHHBKl8x6IClSA2NGwieAqobooqVKshSEhks2dEePAK6Q0MTie5T8+Vy8ANZozK9K8H 5yFbto13aJESfod4XSmvQihXwAEbOr6+ng5Qrtnq2CUJqXrq1LDfJfLKrP5nXOki+hNM TGf0R/WoSexIDnk5VsYsGHqYq72ULW2D5oNowBkAmoed8An4SJu9kICyQqsQGekrwmkQ 7dpg== X-Gm-Message-State: AOJu0YwA0sYD7QCyx3O2LD9EhZVtblF0kaeeVZZ8caE1qZOkPVgDlcgZ h1+l6Gel8+Ba/QlLE2SRvduAYA== X-Received: by 2002:a05:6830:1e04:b0:6d9:a337:b639 with SMTP id s4-20020a0568301e0400b006d9a337b639mr5749974otr.60.1702425054446; Tue, 12 Dec 2023 15:50:54 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m19-20020a0568301e7300b006b9cc67386fsm2487295otr.66.2023.12.12.15.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 15:50:54 -0800 (PST) From: Deepak Gupta Cc: Deepak Gupta , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Andrew Jones , Guo Ren , Mayuresh Chitale , Greentime Hu , Conor Dooley , Heiko Stuebner , Evan Green , Jisheng Zhang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] riscv: abstract envcfg CSR Date: Tue, 12 Dec 2023 15:49:26 -0800 Message-ID: <20231212235003.2036221-2-debug@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231212235003.2036221-1-debug@rivosinc.com> References: <20231212235003.2036221-1-debug@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 12 Dec 2023 15:51:19 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785122087141881648 X-GMAIL-MSGID: 1785122087141881648 This patch abstracts envcfg CSR in kernel (as is done for other homonyn CSRs). CSR_ENVCFG is used as alias for CSR_SENVCFG or CSR_MENVCFG depending on how kernel is compiled. Additionally it changes CBZE enabling to start using CSR_ENVCFG instead of CSR_SENVCFG. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 306a19a5509c..b3400517b0a9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -415,6 +415,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -439,6 +440,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b3785ffc1570..98623393fd1f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -725,7 +725,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE From patchwork Tue Dec 12 23:49:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 177675 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp8074130vqy; Tue, 12 Dec 2023 15:51:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IEtMYmcVeG2+3updjKF1hPPUn+3W+7Gfp+gZL0rrSImep6WZFxMjrviH2c2wMwB/85bl+5C X-Received: by 2002:a17:90b:23c4:b0:286:6cc0:62b2 with SMTP id md4-20020a17090b23c400b002866cc062b2mr7486048pjb.49.1702425090316; Tue, 12 Dec 2023 15:51:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702425090; cv=none; d=google.com; s=arc-20160816; b=e5jt5CdZ9iqdVQqKGJYEEqKZVbuuhSLwEW+DnA1lL0XfDOWzlJMaTQUdYh1eakaDq4 LeplEp3KykxpWOhZ48CREK+cajgry4UHSuGvHepibM0ALhho1KZ6glkZs8MQ0+5MI8C9 xxBgw7cXNZXhXAZUwSuW/CS5lNhnkZyp61lY65wbjGlM0KcuM8WqVhS4/NCwhJ0GNJVV t7BJdNzkvTncjzievzc+kUbPffkob4YME+J7aU0HFTgaV8AJyKZBDRGiuLfkWLrROcVY +BG669H6nKqONGqIK+lJ0/yy4fTc9K7Z00B2ruwXnVcZMDutB4uZw2LK7kcrBHTtD1q5 7e/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :message-id:date:subject:cc:from:dkim-signature; bh=SDRVUnCHqVBNMGZhqCPohfXcgegTHPBlvp76ltshrAo=; fh=lWWlujeSB2THWvfgaTkUGk8ba8+Clrjjecwa7Dr7zH0=; b=hpyKLfy6Iihs94UpANcIYbRhAzu0KL6ama/QrEzmEJaFHk9j9QRhKa2AuGuXr+tdxv INA/ZsXSy2R5FotRI2rnEpEHVPKx9XQBKgqGgEpZEYw2EE7ISnAR2GGh9E08MgSUTIcZ 4O+Q9Wp64+MgehS4hNXl+rLPUTZeol5YRwvh6zGaRN1kMzMcsb6/7AUU7BAm5P7wGi59 DPoZz3JaD6ED/1pyhcpopXfydIRwj1M5UfTleLzAuWSDWT8grgNbwajbyseGW8zdtibC pHurMJsRBzvBoMRU4k9CQ4XXOSr2xZeH/i2nBIc+9giQ8pkj8PdgFUzqsm2VwI6yzjZ1 LY6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=K4RE5qal; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Control flow integrity and pointer masking features need to be enabled on per thread basis. Additionally, I believe cache management instructions need to be enabled on per thread basis. As an example a seccomped task on riscv may be restricted to not use cache management instructions This patch creates a place holder for envcfg CSR in `thread_info` and adds logic to save and restore on trap entry and exits. This allows such isa feature to be enabled on per thread basis. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/thread_info.h | 1 + arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/entry.S | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index 574779900bfb..320bc899a63b 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -57,6 +57,7 @@ struct thread_info { long user_sp; /* User stack pointer */ int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ + unsigned long envcfg; #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index a03129f40c46..cdd8f095c30c 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -39,6 +39,7 @@ void asm_offsets(void) OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); + OFFSET(TASK_TI_ENVCFG, task_struct, thread_info.envcfg); #ifdef CONFIG_SHADOW_CALL_STACK OFFSET(TASK_TI_SCS_SP, task_struct, thread_info.scs_sp); #endif diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 54ca4564a926..a1d87013f15a 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -64,12 +64,14 @@ SYM_CODE_START(handle_exception) csrr s3, CSR_TVAL csrr s4, CSR_CAUSE csrr s5, CSR_SCRATCH + csrr s6, CSR_ENVCFG REG_S s0, PT_SP(sp) REG_S s1, PT_STATUS(sp) REG_S s2, PT_EPC(sp) REG_S s3, PT_BADADDR(sp) REG_S s4, PT_CAUSE(sp) REG_S s5, PT_TP(sp) + REG_S s6, TASK_TI_ENVCFG(tp) /* * Set the scratch register to 0, so that if a recursive exception @@ -129,6 +131,10 @@ SYM_CODE_START_NOALIGN(ret_from_exception) addi s0, sp, PT_SIZE_ON_STACK REG_S s0, TASK_TI_KERNEL_SP(tp) + /* restore envcfg bits for current thread */ + REG_L s0, TASK_TI_ENVCFG(tp) + csrw CSR_ENVCFG, s0 + /* Save the kernel shadow call stack pointer */ scs_save_current