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Tue, 12 Dec 2023 10:02:03 -0600 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [RFC PATCH 1/6] iommu/amd: Update PASID, GATS, and GLX feature related macros Date: Tue, 12 Dec 2023 10:01:34 -0600 Message-ID: <20231212160139.174229-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212160139.174229-1-suravee.suthikulpanit@amd.com> References: <20231212160139.174229-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECDB:EE_|LV8PR12MB9359:EE_ X-MS-Office365-Filtering-Correlation-Id: 96aeb359-6461-49b3-147d-08dbfb2bafe0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WHdhS27qTeKzis+U2tbplak2RUP2gAoNS3YLWomaFdYHWpzbitJJkWK602YniFfna/D0nYt0g7LKWpy59MnAN8bfRDtXnThw13K9tCNH+uiIcGKnB4gNyYpKGOwuXawmSVY33UdCnS9RClKsN+z9o/TZ5bx9lKkIvQHin9Gk8c8xrrgJp6Keab0WFaFcfyFDrgNCSIBtCP3D2kdspdxsrJ9hS+GRUSVT4RhNUT+xqPULwSUB+4kkUEMl8vC8atMvcqiJDknbhaBIWjxhIboNeUQmti6I1HezkEJL2CiBKIQEk/bWfwAH5LqdMCRzQ2e7CEUoLnN3iwitjRMUyDQ7Q/EW9LFTagb8TEpSbL4+Hc1aRiyXs/XadHxLSJMZgVNNwHj8kGCvyehOq6TVwytuaDiTajX454783sWHPGsmSadtw+mDay2nPnGBLkdhQ88712zBOplaZBWuwrO+F2xs94JY7gummRNAqkB/Si5YhBbAnYLHb1y1wQREx8U31C7J0bD16keJ/ElqLFRULmcAVC0OKehBymfB6x1fP7QUhIqu/SmZNLyn+xtBQQAzVqHXcvHzOmrwvQXan5RxbRXTXnqD619jeogs8JIqIs311MBDwJUoAf7fTRuKY64kfb5STzGCOemwdXZHyuDeUKdAjR4oCoSx3qH4Zjl5tTGFCIusAN03kCG3QKtOxpJZW6rbSFteCEbJljjlfdhUvsNeNUYurqy3SG+7ZMM6h9DBRjX46DiY5BC3Z69G4H8+qvTc6q2+xGv1kyGsuMu1fJf312i6lps0Krj25rLJWz3eOBE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(396003)(39860400002)(230922051799003)(82310400011)(186009)(1800799012)(64100799003)(451199024)(40470700004)(36840700001)(46966006)(8676002)(8936002)(4326008)(2906002)(44832011)(40480700001)(316002)(40460700003)(7416002)(5660300002)(110136005)(70206006)(70586007)(54906003)(478600001)(36860700001)(26005)(336012)(426003)(36756003)(1076003)(7696005)(6666004)(41300700001)(2616005)(16526019)(81166007)(82740400003)(356005)(83380400001)(47076005)(86362001)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Tue, 12 Dec 2023 08:02:20 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785092579152552117 X-GMAIL-MSGID: 1785092579152552117 Clean up and reorder them according to the bit index. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 +- drivers/iommu/amd/amd_iommu_types.h | 13 +++++++------ drivers/iommu/amd/init.c | 8 ++++---- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index bbed268e8abc..108253edbeb0 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -106,7 +106,7 @@ static inline bool check_feature2(u64 mask) static inline int check_feature_gpt_level(void) { - return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK); + return ((amd_iommu_efr & FEATURE_GATS_MASK) >> FEATURE_GATS_SHIFT); } static inline bool amd_iommu_gt_ppr_supported(void) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 3dc39bbc05fc..14f67a8cf755 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -93,8 +93,6 @@ #define FEATURE_GA BIT_ULL(7) #define FEATURE_HE BIT_ULL(8) #define FEATURE_PC BIT_ULL(9) -#define FEATURE_GATS_SHIFT (12) -#define FEATURE_GATS_MASK (3ULL) #define FEATURE_GAM_VAPIC BIT_ULL(21) #define FEATURE_GIOSUP BIT_ULL(48) #define FEATURE_HASUP BIT_ULL(49) @@ -102,11 +100,14 @@ #define FEATURE_HDSUP BIT_ULL(52) #define FEATURE_SNP BIT_ULL(63) -#define FEATURE_PASID_SHIFT 32 -#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) +#define FEATURE_GATS_SHIFT 12 +#define FEATURE_GATS_MASK (0x03ULL << FEATURE_GATS_SHIFT) -#define FEATURE_GLXVAL_SHIFT 14 -#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) +#define FEATURE_GLX_SHIFT 14 +#define FEATURE_GLX_MASK (0x03ULL << FEATURE_GLX_SHIFT) + +#define FEATURE_PASMAX_SHIFT 32 +#define FEATURE_PASMAX_MASK (0x1FULL << FEATURE_PASMAX_SHIFT) /* Extended Feature 2 Bits */ #define FEATURE_SNPAVICSUP_SHIFT 5 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 959820ccfbcc..e84c69fe13d4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2080,14 +2080,14 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) int glxval; u64 pasmax; - pasmax = amd_iommu_efr & FEATURE_PASID_MASK; - pasmax >>= FEATURE_PASID_SHIFT; + pasmax = amd_iommu_efr & FEATURE_PASMAX_MASK; + pasmax >>= FEATURE_PASMAX_SHIFT; iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); - glxval = amd_iommu_efr & FEATURE_GLXVAL_MASK; - glxval >>= FEATURE_GLXVAL_SHIFT; + glxval = amd_iommu_efr & FEATURE_GLX_MASK; + glxval >>= FEATURE_GLX_SHIFT; if (amd_iommu_max_glx_val == -1) amd_iommu_max_glx_val = glxval; From patchwork Tue Dec 12 16:01:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 177427 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7821578vqy; Tue, 12 Dec 2023 08:02:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IFUqTtpjorodknkUzXM4P2ULA4XHwU2ZSCu5PSnCj81pZ/54JowwJTRJ87HymcVgA47qftu X-Received: by 2002:a05:6e02:b44:b0:35d:66a0:5420 with SMTP id f4-20020a056e020b4400b0035d66a05420mr10454944ilu.31.1702396956055; Tue, 12 Dec 2023 08:02:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1702396956; cv=pass; d=google.com; s=arc-20160816; b=hypED0fPEoReer/yfAP4oh/Qg4suLZVJy8X7tyCzOQbNFD/J2V9NS2M1W70vfW1Yj1 xticBxxHWhQuYVBmLGNMFu1MDSrZeYoKV6xPV6JIiUY9KD+wAX21Kq3YUSqqIWHXSz9A D3nnIyJlQUn+0V0Xd+8riUL6eox/MCsa4mufu62QPHdJrFyb23e9bZN5BQw39tJVszPO rXT16+AzcYJCsL7EKNqHx2Yti6WGTKrZ5R2Qx87vrMbv5yZNyAvYTOwpsUfnbV3qqcQc QecHn0rjrdyqwIReXuCH/OKgTpE3XkILBZ1Eh2MkmeUi3VueYKjfztiGDkafT/imzVhe W1Cw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gvVFgIcnPdCeXk70+pGgRUBYR91xAlnGJLYJHydkBZY=; fh=e9PdO+rcGhV+cnwOMjmt98TGV0HSDydHzrUHrldjlVY=; b=tGPDKctazebcVRbLqKSsgQiarQ4Gh3Vt120TuYp2MQSZjd3CqkiX9bsQ1TTQbVo/KC RZAcKX338WlNdzh6z4p/TmnD3j04nrEHsDNuHdv/wOG4I8kihHScS1o4Xk3BYYF2IYV/ KJuVWoS3SVcKnGlvu/ALCoQ2hDomT5czHT47TR8AeNoQgA5HPhD4kI4z0DRq4oLRkpiK GSH02g0H1MY2uS3uZAkNAy9hfDnRkINap8Bqm/xR+teHYkVe9TUdheWw5w6HZWIXiE6O 7zuCEO+9eDFsIxkXc9MwA6i24GhBU7yXtDUBfdFuaOjYUIp/poB4M/aq5mFji2IUsMac vUNw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=OZqKLKYs; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from lipwig.vger.email (lipwig.vger.email. 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Tue, 12 Dec 2023 08:02:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785092590465330452 X-GMAIL-MSGID: 1785092590465330452 AMD IOMMU Extended Feature (EFR) and Extended Feature 2 (EFR2) registers specify features supported by each IOMMU hardware instance. The IOMMU driver checks each feature-specific bits before enabling each feature at run time. For IOMMUFD, the hypervisor determines which IOMMU features to support in the guest, and communicates this information to user-space (e.g. QEMU) via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/amd_iommu_types.h | 3 +++ drivers/iommu/amd/iommu.c | 38 +++++++++++++++++++++++++++++ include/uapi/linux/iommufd.h | 13 ++++++++++ 4 files changed, 56 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 108253edbeb0..4118129f4a24 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -72,6 +72,8 @@ void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data, void amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data, ioasid_t pasid); +void amd_iommu_build_efr(u64 *efr, u64 *efr2); + #ifdef CONFIG_IRQ_REMAP int amd_iommu_create_irq_domain(struct amd_iommu *iommu); #else diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 14f67a8cf755..956fd4658a4a 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -100,12 +100,15 @@ #define FEATURE_HDSUP BIT_ULL(52) #define FEATURE_SNP BIT_ULL(63) +#define FEATURE_GATS_5LEVEL 1ULL #define FEATURE_GATS_SHIFT 12 #define FEATURE_GATS_MASK (0x03ULL << FEATURE_GATS_SHIFT) +#define FEATURE_GLX_3LEVEL 0ULL #define FEATURE_GLX_SHIFT 14 #define FEATURE_GLX_MASK (0x03ULL << FEATURE_GLX_SHIFT) +#define FEATURE_PASMAX_16 0xFULL #define FEATURE_PASMAX_SHIFT 32 #define FEATURE_PASMAX_MASK (0x1FULL << FEATURE_PASMAX_SHIFT) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4e4ff1550cf3..c41932e9f16a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2822,8 +2822,46 @@ static const struct iommu_dirty_ops amd_dirty_ops = { .read_and_clear_dirty = amd_iommu_read_and_clear_dirty, }; +void amd_iommu_build_efr(u64 *efr, u64 *efr2) +{ + if (efr) { + *efr = (FEATURE_GT | FEATURE_GIOSUP | FEATURE_PPR); + + /* 5-level v2 page table support */ + *efr |= ((FEATURE_GATS_5LEVEL << FEATURE_GATS_SHIFT) & + FEATURE_GATS_MASK); + + /* 3-level GCR3 table support */ + *efr |= ((FEATURE_GLX_3LEVEL << FEATURE_GLX_SHIFT) & + FEATURE_GLX_MASK); + + /* 16-bit PASMAX support */ + *efr |= ((FEATURE_PASMAX_16 << FEATURE_PASMAX_SHIFT) & + FEATURE_PASMAX_MASK); + } + + if (efr2) + *efr2 = 0; +} + +static void *amd_iommu_hw_info(struct device *dev, u32 *length, u32 *type) +{ + struct iommu_hw_info_amd *hwinfo; + + hwinfo = kzalloc(sizeof(*hwinfo), GFP_KERNEL); + if (!hwinfo) + return ERR_PTR(-ENOMEM); + + *length = sizeof(*hwinfo); + *type = IOMMU_HW_INFO_TYPE_AMD; + + amd_iommu_build_efr(&hwinfo->efr, &hwinfo->efr2); + return hwinfo; +} + const struct iommu_ops amd_iommu_ops = { .capable = amd_iommu_capable, + .hw_info = amd_iommu_hw_info, .domain_alloc = amd_iommu_domain_alloc, .domain_alloc_user = amd_iommu_domain_alloc_user, .probe_device = amd_iommu_probe_device, diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 0b2bc6252e2c..bf4a1f8ab748 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -474,15 +474,28 @@ struct iommu_hw_info_vtd { __aligned_u64 ecap_reg; }; +/** + * struct iommu_hw_info_amd - AMD IOMMU device info + * + * @efr : Value of AMD IOMMU Extended Feature Register (EFR) + * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) + */ +struct iommu_hw_info_amd { + __u64 efr; + __u64 efr2; +}; + /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_NONE: Used by the drivers that do not report hardware * info * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type + * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE, IOMMU_HW_INFO_TYPE_INTEL_VTD, + IOMMU_HW_INFO_TYPE_AMD, }; /** From patchwork Tue Dec 12 16:01:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 177426 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7821563vqy; Tue, 12 Dec 2023 08:02:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IFzvNcF8I168Zi3xL426BukHCDPyIOo2FkIODz/mYJnLbmWxYJcsfi4IIR0CshzeO7lpw7N X-Received: by 2002:a17:902:8bc8:b0:1d0:a0f2:afac with SMTP id r8-20020a1709028bc800b001d0a0f2afacmr2782808plo.131.1702396955351; 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Tue, 12 Dec 2023 08:02:31 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785092589704679800 X-GMAIL-MSGID: 1785092589704679800 AMD HW-vIOMMU feature requires IOMMU driver to specify a unique 16-bit Guest ID (GID) for each VM. This ID is used to index into various data structures for configuring the hardware. Introduce amd_iommu_vminfo_hash hashtable to store per-vm configuration, which uses 16-bit GID as a hash key along with helper functions. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 6 +++ drivers/iommu/amd/amd_iommu_types.h | 6 +++ drivers/iommu/amd/iommu.c | 66 +++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 4118129f4a24..7783a933ad14 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -182,4 +182,10 @@ void amd_iommu_domain_set_pgtable(struct protection_domain *domain, struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); extern bool amd_iommu_snp_en; + +/* AMD IOMMU GID */ +int amd_iommu_vminfo_alloc(struct amd_iommu *iommu, struct amd_iommu_vminfo *vminfo); +void amd_iommu_vminfo_free(struct amd_iommu *iommu, struct amd_iommu_vminfo *vminfo); +struct amd_iommu_vminfo *amd_iommu_get_vminfo(int gid); + #endif diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 956fd4658a4a..a00731673c50 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -16,6 +16,7 @@ #include #include #include +#include /* * Maximum number of IOMMUs supported @@ -1053,6 +1054,11 @@ struct amd_irte_ops { void (*clear_allocated)(struct irq_remap_table *, int); }; +struct amd_iommu_vminfo { + u16 gid; + struct hlist_node hnode; +}; + #ifdef CONFIG_IRQ_REMAP extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c41932e9f16a..d18b23ac6357 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,16 @@ LIST_HEAD(acpihid_map); const struct iommu_ops amd_iommu_ops; static const struct iommu_dirty_ops amd_dirty_ops; +/* VMInfo Hashtable */ +#define AMD_IOMMU_VMINFO_HASH_BITS 16 +DEFINE_HASHTABLE(amd_iommu_vminfo_hash, AMD_IOMMU_VMINFO_HASH_BITS); +DEFINE_SPINLOCK(amd_iommu_vminfo_hash_lock); + +/* Global VMID */ +#define AMD_IOMMU_VMID_INVALID (-1U) +static DEFINE_IDA(amd_iommu_global_vmid_ida); +static u32 amd_iommu_latest_gid; + int amd_iommu_max_glx_val = -1; /* @@ -101,6 +112,61 @@ static inline bool domain_id_is_per_dev(struct protection_domain *pdom) return (pdom && pdom->pd_mode != PD_MODE_V1); } +int get_vmid(void) +{ + int ret; + + ret = ida_alloc_range(&amd_iommu_global_vmid_ida, 1, 0xFFFF, GFP_KERNEL); + return ret < 0 ? AMD_IOMMU_VMID_INVALID : ret; +} + +int amd_iommu_vminfo_alloc(struct amd_iommu *iommu, struct amd_iommu_vminfo *vminfo) +{ + u32 gid; + unsigned long flags; + + spin_lock_irqsave(&amd_iommu_vminfo_hash_lock, flags); + gid = amd_iommu_latest_gid = get_vmid(); + if (gid == AMD_IOMMU_VMID_INVALID) + return -EINVAL; + + pr_debug("%s: gid=%u\n", __func__, gid); + vminfo->gid = gid; + hash_add(amd_iommu_vminfo_hash, &vminfo->hnode, vminfo->gid); + spin_unlock_irqrestore(&amd_iommu_vminfo_hash_lock, flags); + return 0; +} + +void amd_iommu_vminfo_free(struct amd_iommu *iommu, + struct amd_iommu_vminfo *vminfo) +{ + unsigned long flags; + + pr_debug("%s: gid=%u\n", __func__, vminfo->gid); + spin_lock_irqsave(&amd_iommu_vminfo_hash_lock, flags); + hash_del(&vminfo->hnode); + ida_free(&amd_iommu_global_vmid_ida, vminfo->gid); + spin_unlock_irqrestore(&amd_iommu_vminfo_hash_lock, flags); +} + +struct amd_iommu_vminfo *amd_iommu_get_vminfo(int gid) +{ + unsigned long flags; + struct amd_iommu_vminfo *tmp, *ptr = NULL; + + spin_lock_irqsave(&amd_iommu_vminfo_hash_lock, flags); + hash_for_each_possible(amd_iommu_vminfo_hash, tmp, hnode, gid) { + if (tmp->gid == gid) { + ptr = tmp; + break; + } + } + if (!ptr) + pr_debug("%s : gid=%u not found\n", __func__, gid); + spin_unlock_irqrestore(&amd_iommu_vminfo_hash_lock, flags); + return ptr; +} + static inline int get_acpihid_device_id(struct device *dev, struct acpihid_map_entry **entry) { From patchwork Tue Dec 12 16:01:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 177424 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7821393vqy; Tue, 12 Dec 2023 08:02:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IEaLxjvUtWcNzVf3D9u6H/tL25S9mg4ml5Yx/Czf8o80huFPgxcAqiNTIZXnTsbNPcEH3Tw X-Received: by 2002:a17:902:8696:b0:1d0:6ffe:9f0 with SMTP id g22-20020a170902869600b001d06ffe09f0mr6181991plo.78.1702396945176; Tue, 12 Dec 2023 08:02:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1702396945; cv=pass; d=google.com; s=arc-20160816; b=hQyGSB2nQvsq1EzqOKCayw4nz6cua7kW1Ni9KuhkZsJBAE4QVtoxeEf+dDVHW+MtsY duBegfsf9eYcTxRzDAQhynKk6ojaVmRklDKgB8SVNjklE4ENu8ph1Bfrwf67trZqU3NQ NXTLXjKHsh/Z86ADmN0zQoZ0sRMg9h84GPx7BB4hDT4SmKc1bTiReL0oONYaX15x4MQR ISh1TTK4HW/vUjskXW9mABnBEDlsuf6iepV22VOdSfies60grv4K4+jOesd3U8Pxu480 9c/wG8LC3Q7f8qe2eUo937Z+ffb5mwFnLNb0IyvAFiTpbu6D1qlUbsplJClIGNStRTfV Wr7w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MUFLSNQg7aQQMVuKUbAGPiamZbXRs4qJEBIyaa8j4mw=; fh=e9PdO+rcGhV+cnwOMjmt98TGV0HSDydHzrUHrldjlVY=; b=WQUUHWr9VBXHL54+urOZYDxqRTmZNEh2qdx9AMygGbMusLfDxT+LpacpY9xiLftOgM Ic88pAK4UpjzeBLW/OhVxTfjrGzmaQRHKaLPMYxKriLDQzKy8wuZxknzJRqKiQyHcwmb GfL7hX5gfrZjbbaNJel4P1897ELKxTYL0nw4P7nlAbRO0DgqDXTwUPNaTocPHjPyth82 RMxTXBX/7AFKR+RyXoaBZTdXKemSj3uuG5qS2p9m3CKi30y/Odd+VO1NbqrL6T4B5PB4 mWEWFkdpLeKhgk9E5xatK1Aj8G8KWsTdJonrJH5AHQ80CSUi8g2f6VCYiRZ1fsyY14Lb X4hQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=KQU2+yPJ; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Tue, 12 Dec 2023 08:02:23 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785092579102474164 X-GMAIL-MSGID: 1785092579102474164 Introduce IOMMU_HWPT_DATA_AMD_V2 data type for AMD IOMMU v2 page table, which is used for stage-1 in nested translation. The data structure contains information necessary for setting up the AMD HW-vIOMMU support. Signed-off-by: Suravee Suthikulpanit --- include/uapi/linux/iommufd.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index bf4a1f8ab748..e2240d430dd1 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -389,14 +389,37 @@ struct iommu_hwpt_vtd_s1 { __u32 __reserved; }; +/** + * struct iommu_hwpt_amd_v2 - AMD IOMMU specific user-managed + * v2 I/O page table data + * @gcr3: GCR3 guest physical ddress + * @gid: Guest ID + * @iommu_id: IOMMU host device ID + * @gdev_id: Guest device ID + * @gdom_id: Guest domain ID + * @glx: GCR3 table levels + * @guest_paging_mode: Guest v2 page table paging mode + */ +struct iommu_hwpt_amd_v2 { + __aligned_u64 gcr3; + __u32 gid; + __u32 iommu_id; + __u16 gdev_id; + __u16 gdom_id; + __u16 glx; + __u16 guest_paging_mode; +}; + /** * enum iommu_hwpt_data_type - IOMMU HWPT Data Type * @IOMMU_HWPT_DATA_NONE: no data * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_DATA_AMD_V2: AMD IOMMUv2 page table */ enum iommu_hwpt_data_type { IOMMU_HWPT_DATA_NONE, IOMMU_HWPT_DATA_VTD_S1, + IOMMU_HWPT_DATA_AMD_V2, }; /** From patchwork Tue Dec 12 16:01:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 177425 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7821480vqy; Tue, 12 Dec 2023 08:02:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IFhfERPrERYh+6MUyi4RMUzm8S8TDtFsanBVFZ8qOeXog0qZNJY4heueC8oFUp4NClZtXl0 X-Received: by 2002:a05:6870:4723:b0:1fa:477:8a93 with SMTP id b35-20020a056870472300b001fa04778a93mr3361189oaq.24.1702396950566; Tue, 12 Dec 2023 08:02:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1702396950; cv=pass; d=google.com; s=arc-20160816; b=nECir/D5UnY5J/f+7WSDgxFwt0KAX1UG8wLUcWCor8nqgxZ9qn4gtTRMkoZAFpij5C BzI5NWqQmyFIh3ODvSJ88Xzbsnde16rw7G5KnFVse5SSvOF5VLgImGavBLPOfCGcLIqy tlpktzVZmQWW9KPw1oCFmg2I0HV4sLW7pm+gzEAWMHx/qhe/JDLHGAiR+XqlPNMTmWrQ tA3Z7Cn3NCRqj/bG82VByoicVEnWMBxlBg0BdOKCU4zGGr1siSya3VuZRD5CxkxLd1Dh sBPe8lj+5lEvfMuwU7Lzbx4QraAbWwsYAhVa0bvSFCb4CmxdlNGjnv1zJGNmRBoukOdR zWCw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=k0t1O6PS4HQZxDRacCxVotWwYGVY0VRDxpdj2PXvXsI=; fh=e9PdO+rcGhV+cnwOMjmt98TGV0HSDydHzrUHrldjlVY=; b=xemuachoRmRCbvOXy3KpI8By3m0Acet5EboE+q6ffa9owZkXneqT2CS5o4ajphCnkr /j2pLhBJAbM1iiTRAkpTet/+u5Q5fljSemgZKgvCcaQhAFIGF3KdgsVM7bsecEKCVbBi 0yb1UxBRQYPsGNbabWDtjFWaKhrMt/A237I1GCRXdi/Gd1KT1ZOJFW6u20yYXidZV6h+ 6f78W4aM/xQxQgp1Mcog2/Lg/9r07JlS54IJ3/rCzOoiMiqLY1v731AAcuopaBJIWwTZ r/SK0iIKuDC0QfuFX39QkXlWD5LjwdyFHI6ocJYh/8eey7EAr7o/aphMcKpsFZCO/3Kl PXrg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="B/ts5wjy"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Tue, 12 Dec 2023 08:02:28 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785092585185622446 X-GMAIL-MSGID: 1785092585185622446 The GCR3TRPMode allows IOMMU hardware to use GPA when programming the GCR3 table root pointer (GCR3TRP) in the DTE. The GPA will be translated by the IOMMU using the v1 page table referenced by the DTE[Host Page Table Root Pointer]. Please see the AMD IOMMU Specification for more detail. (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf) Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 + drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/iommu.c | 132 +++++++++++++++++++++++++++- 3 files changed, 131 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 7783a933ad14..55479a6efaae 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -56,6 +56,8 @@ void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev); int amd_iommu_set_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid, unsigned long gcr3); int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid); +int amd_iommu_set_gcr3tbl_trp(struct amd_iommu *iommu, struct pci_dev *pdev, + u64 gcr3_tbl, u16 glx, u16 guest_paging_mode); /* * This function flushes all internal caches of diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index a00731673c50..1b150e0cb689 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -541,6 +541,7 @@ struct gcr3_tbl_info { u64 *gcr3_tbl; /* Guest CR3 table */ int glx; /* Number of levels for GCR3 table */ u32 pasid_cnt; /* Track attached PASIDs */ + bool trp; /* TRP support */ }; struct amd_io_pgtable { diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index d18b23ac6357..8bf12674dc84 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -93,6 +93,9 @@ static void detach_device(struct device *dev); static void set_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data *dev_data); +static void amd_iommu_clear_gcr3tbl_trp(struct amd_iommu *iommu, + struct iommu_dev_data *dev_data); + /**************************************************************************** * * Helper functions @@ -2146,15 +2149,25 @@ static int do_attach(struct iommu_dev_data *dev_data, static void do_detach(struct iommu_dev_data *dev_data) { + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; struct protection_domain *domain = dev_data->domain; struct amd_iommu *iommu; iommu = get_amd_iommu_from_dev(dev_data->dev); - /* Clear GCR3 table */ - if (domain->pd_mode == PD_MODE_V2) { - __clear_gcr3(dev_data, 0); - free_gcr3_table(dev_data); + if (gcr3_info->gcr3_tbl) { + if (gcr3_info->trp) { + /* + * In GCR3TRPMode, the GCR3 table contains GPA, + * which is setup by guest kernel. Therefore, we just + * need to clean up the DTE settings for guest translation. + */ + amd_iommu_clear_gcr3tbl_trp(iommu, dev_data); + } else { + /* Clear GCR3 table */ + __clear_gcr3(dev_data, 0); + free_gcr3_table(dev_data); + } } /* Update data structures */ @@ -2951,6 +2964,117 @@ const struct iommu_ops amd_iommu_ops = { } }; +/* + * For GCR3TRPMode, user-space provides GPA for the GCR3 Root Pointer Table. + */ +int amd_iommu_set_gcr3tbl_trp(struct amd_iommu *iommu, struct pci_dev *pdev, + u64 gcr3_tbl, u16 glx, u16 guest_paging_mode) +{ + struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev); + struct dev_table_entry *dev_table = get_dev_table(iommu); + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + int devid = pci_dev_id(pdev); + u64 data0 = dev_table[devid].data[0]; + u64 data1 = dev_table[devid].data[1]; + u64 data2 = dev_table[devid].data[2]; + u64 tmp; + + pr_debug("%s: devid=%d, glx=%#x, gcr3_tbl=%#llx\n", + __func__, devid, glx, gcr3_tbl); + + WARN_ON(gcr3_info->trp); + + gcr3_info->trp = true; + gcr3_info->gcr3_tbl = (u64 *)gcr3_tbl; + + data0 |= DTE_FLAG_GV | DTE_FLAG_GIOV; + tmp = glx; + data0 |= (tmp & DTE_GLX_MASK) << DTE_GLX_SHIFT; + + /* First mask out possible old values for GCR3 table */ + tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; + data0 &= ~tmp; + + tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; + data1 &= ~tmp; + + tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; + data1 &= ~tmp; + + /* Encode GCR3 table into DTE */ + tmp = DTE_GCR3_VAL_A(gcr3_tbl) << DTE_GCR3_SHIFT_A; + data0 |= tmp; + + tmp = DTE_GCR3_VAL_B(gcr3_tbl) << DTE_GCR3_SHIFT_B; + data1 |= tmp; + + tmp = DTE_GCR3_VAL_C(gcr3_tbl) << DTE_GCR3_SHIFT_C; + data1 |= tmp; + + /* Mask out old values for GuestPagingMode */ + data2 &= ~(0x3ULL << DTE_GPT_LEVEL_SHIFT); + + /* Check 5-level support for the host before enabling on behalf of the guest */ + tmp = (u64)guest_paging_mode; + if ((tmp == GUEST_PGTABLE_5_LEVEL) && + (check_feature_gpt_level() < GUEST_PGTABLE_5_LEVEL)) { + pr_err("Cannot support 5-level v2 page table.\n"); + return -EINVAL; + } + data2 |= (tmp << DTE_GPT_LEVEL_SHIFT); + + dev_table[devid].data[2] = data2; + dev_table[devid].data[1] = data1; + dev_table[devid].data[0] = data0; + + device_flush_dte(dev_data); + iommu_completion_wait(iommu); + + return 0; +} + +void amd_iommu_clear_gcr3tbl_trp(struct amd_iommu *iommu, + struct iommu_dev_data *dev_data) +{ + int devid = dev_data->devid; + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + struct dev_table_entry *dev_table = get_dev_table(iommu); + u64 data0 = dev_table[devid].data[0]; + u64 data1 = dev_table[devid].data[1]; + u64 data2 = dev_table[devid].data[2]; + u64 tmp; + + if (!gcr3_info->trp) + return; + + pr_debug("%s: devid=%#x, gcr3_tbl=%#llx\n", __func__, devid, + (unsigned long long)gcr3_info->gcr3_tbl); + + tmp = DTE_GLX_MASK; + data0 &= ~(tmp << DTE_GLX_SHIFT); + data0 &= ~(DTE_FLAG_GV | DTE_FLAG_GIOV); + + /* Mask out possible old values for GCR3 table */ + tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; + data0 &= ~tmp; + + tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; + data1 &= ~tmp; + + tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; + data1 &= ~tmp; + + /* Mask out old values for GuestPagingMode */ + data2 &= ~(0x3ULL << DTE_GPT_LEVEL_SHIFT); + + dev_table[devid].data[2] = data2; + dev_table[devid].data[1] = data1; + dev_table[devid].data[0] = data0; + + gcr3_info->trp = false; + gcr3_info->gcr3_tbl = NULL; +} + #ifdef CONFIG_IRQ_REMAP /***************************************************************************** From patchwork Tue Dec 12 16:01:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 177428 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7821837vqy; Tue, 12 Dec 2023 08:02:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IF541q5D3uZlB64rsRjtmodMSbCkAaUtAZNct3OHyAfGFM5pSTPRJOLfAaoSlkuJ6i0ZbQm X-Received: by 2002:a17:902:bc4c:b0:1d0:91a0:a29 with SMTP id t12-20020a170902bc4c00b001d091a00a29mr3008529plz.6.1702396971993; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECD6.mail.protection.outlook.com (10.167.242.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.18 via Frontend Transport; Tue, 12 Dec 2023 16:02:10 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 12 Dec 2023 10:02:08 -0600 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [RFC PATCH 6/6] iommu/amd: Introduce nested translation support Date: Tue, 12 Dec 2023 10:01:39 -0600 Message-ID: <20231212160139.174229-7-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212160139.174229-1-suravee.suthikulpanit@amd.com> References: <20231212160139.174229-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD6:EE_|BY5PR12MB5512:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f8c8c74-9d1e-40b6-db34-08dbfb2bb2cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Tue, 12 Dec 2023 08:02:47 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785092606954562434 X-GMAIL-MSGID: 1785092606954562434 To support nested translation on AMD IOMMU, the driver needs to program DTE[GCR3 Table Root Pointer] with the address provided by the guest via struct iommu_hwpt_amd_v2, which is passed as a parameter of the struct iommu_ops.domain_alloc_user() with the flag IOMMU_HWPT_ALLOC_NEST_PARENT. Note that current implementation only support GCR3TRPMode for nested translation, which uses GPA to program GCR3 Table Root Pointer. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 8 +++ drivers/iommu/amd/amd_iommu_types.h | 3 + drivers/iommu/amd/iommu.c | 63 ++++++++++++++-- drivers/iommu/amd/nested.c | 107 ++++++++++++++++++++++++++++ 5 files changed, 175 insertions(+), 8 deletions(-) create mode 100644 drivers/iommu/amd/nested.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index f454fbb1569e..447cb6bb48eb 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_AMD_IOMMU) += iommu.o init.o quirks.o io_pgtable.o io_pgtable_v2.o +obj-$(CONFIG_AMD_IOMMU) += iommu.o init.o quirks.o io_pgtable.o io_pgtable_v2.o nested.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += debugfs.o diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 55479a6efaae..6ea146a964df 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -7,6 +7,7 @@ #ifndef AMD_IOMMU_H #define AMD_IOMMU_H +#include #include #include "amd_iommu_types.h" @@ -75,6 +76,8 @@ void amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data, ioasid_t pasid); void amd_iommu_build_efr(u64 *efr, u64 *efr2); +int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev); +void amd_iommu_domain_free(struct iommu_domain *dom); #ifdef CONFIG_IRQ_REMAP int amd_iommu_create_irq_domain(struct amd_iommu *iommu); @@ -190,4 +193,9 @@ int amd_iommu_vminfo_alloc(struct amd_iommu *iommu, struct amd_iommu_vminfo *vmi void amd_iommu_vminfo_free(struct amd_iommu *iommu, struct amd_iommu_vminfo *vminfo); struct amd_iommu_vminfo *amd_iommu_get_vminfo(int gid); +/* NESTED */ +struct protection_domain *to_pdomain(struct iommu_domain *dom); +struct iommu_domain *amd_iommu_nested_domain_alloc(struct device *dev, + struct iommu_hwpt_amd_v2 *hwpt); + #endif diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 1b150e0cb689..c2055b476a97 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -114,6 +114,8 @@ #define FEATURE_PASMAX_MASK (0x1FULL << FEATURE_PASMAX_SHIFT) /* Extended Feature 2 Bits */ +#define FEATURE_GCR3TRPMODE BIT_ULL(3) + #define FEATURE_SNPAVICSUP_SHIFT 5 #define FEATURE_SNPAVICSUP_MASK (0x07ULL << FEATURE_SNPAVICSUP_SHIFT) #define FEATURE_SNPAVICSUP_GAM(x) \ @@ -1058,6 +1060,7 @@ struct amd_irte_ops { struct amd_iommu_vminfo { u16 gid; struct hlist_node hnode; + u64 *devid_table; }; #ifdef CONFIG_IRQ_REMAP diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8bf12674dc84..2a7e29e8c112 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -260,7 +260,7 @@ static struct amd_iommu *rlookup_amd_iommu(struct device *dev) return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid)); } -static struct protection_domain *to_pdomain(struct iommu_domain *dom) +struct protection_domain *to_pdomain(struct iommu_domain *dom) { return container_of(dom, struct protection_domain, domain); } @@ -2526,21 +2526,70 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned int type) return domain; } +static int udata_to_iommu_hwpt_amd_v2(const struct iommu_user_data *user_data, + struct iommu_hwpt_amd_v2 *hwpt) +{ + if (!user_data) + return -EINVAL; + + if (user_data->type != IOMMU_HWPT_DATA_AMD_V2) + return -EOPNOTSUPP; + + return iommu_copy_struct_from_user(hwpt, user_data, + IOMMU_HWPT_DATA_AMD_V2, + guest_paging_mode); +} + +static bool check_nested_support(u32 flags) +{ + if (!(flags & IOMMU_HWPT_ALLOC_NEST_PARENT)) + return true; + + if (!check_feature(FEATURE_GT) || + !check_feature(FEATURE_GIOSUP) || + !check_feature2(FEATURE_GCR3TRPMODE)) + return false; + + return true; +} + static struct iommu_domain * amd_iommu_domain_alloc_user(struct device *dev, u32 flags, struct iommu_domain *parent, const struct iommu_user_data *user_data) - { - unsigned int type = IOMMU_DOMAIN_UNMANAGED; + struct iommu_domain *dom; + + if (parent) { + int ret; + struct iommu_hwpt_amd_v2 hwpt; + + if (parent->ops != amd_iommu_ops.default_domain_ops) + return ERR_PTR(-EINVAL); - if ((flags & ~IOMMU_HWPT_ALLOC_DIRTY_TRACKING) || parent || user_data) + ret = udata_to_iommu_hwpt_amd_v2(user_data, &hwpt); + if (ret) + return ERR_PTR(ret); + + return amd_iommu_nested_domain_alloc(dev, &hwpt); + } + + /* Check supported flags */ + if (flags & (~(IOMMU_HWPT_ALLOC_NEST_PARENT | + IOMMU_HWPT_ALLOC_DIRTY_TRACKING))) + return ERR_PTR(-EOPNOTSUPP); + + if (!check_nested_support(flags)) return ERR_PTR(-EOPNOTSUPP); - return do_iommu_domain_alloc(type, dev, flags); + dom = iommu_domain_alloc(dev->bus); + if (!dom) + return ERR_PTR(-ENOMEM); + + return dom; } -static void amd_iommu_domain_free(struct iommu_domain *dom) +void amd_iommu_domain_free(struct iommu_domain *dom) { struct protection_domain *domain; unsigned long flags; @@ -2559,7 +2608,7 @@ static void amd_iommu_domain_free(struct iommu_domain *dom) protection_domain_free(domain); } -static int amd_iommu_attach_device(struct iommu_domain *dom, +int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev) { struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); diff --git a/drivers/iommu/amd/nested.c b/drivers/iommu/amd/nested.c new file mode 100644 index 000000000000..332f7efcdc92 --- /dev/null +++ b/drivers/iommu/amd/nested.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * Author: Suravee Suthikulpanit + */ + +#define pr_fmt(fmt) "AMD-Vi: " fmt +#define dev_fmt(fmt) pr_fmt(fmt) + +#include +#include + +#include "amd_iommu.h" + +static struct amd_iommu *get_amd_iommu_from_devid(u16 devid) +{ + struct amd_iommu *iommu; + + for_each_iommu(iommu) + if (iommu->devid == devid) + return iommu; + return NULL; +} + +/* + * Note: + * Host-DevID is stored in the per-VM DevID mapping table, + * which is indexed by the Guest-DevID. + */ +static u16 get_hdev_id(struct amd_iommu *iommu, u16 guestId, u16 gdev_id) +{ + struct amd_iommu_vminfo *vminfo; + void *addr; + u64 offset; + + vminfo = amd_iommu_get_vminfo(guestId); + if (!vminfo) + return -1; + + addr = vminfo->devid_table; + offset = gdev_id << 4; + return (*((u64 *)(addr + offset)) >> 24) & 0xFFFF; +} + +static int nested_gcr3_update(struct iommu_hwpt_amd_v2 *hwpt, struct iommu_domain *udom) +{ + int ret; + u16 hdev_id; + struct pci_dev *pdev; + struct amd_iommu *iommu; + + iommu = get_amd_iommu_from_devid(hwpt->iommu_id); + hdev_id = get_hdev_id(iommu, hwpt->gid, hwpt->gdev_id); + + pr_debug("%s: gid=%u, hdev_id=%#x, gcr3=%#llx\n", + __func__, hwpt->gid, hdev_id, + (unsigned long long) hwpt->gcr3); + + pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(hdev_id), + hdev_id & 0xff); + if (!pdev) + return -EINVAL; + + /* Note: Currently only support GCR3TRPMode with nested translation */ + if (!check_feature2(FEATURE_GCR3TRPMODE)) + return -EOPNOTSUPP; + + ret = amd_iommu_set_gcr3tbl_trp(iommu, pdev, hwpt->gcr3, hwpt->glx, + hwpt->guest_paging_mode); + if (ret) { + pr_err("%s: Fail to enable gcr3 (devid=%#x)\n", __func__, + pci_dev_id(pdev)); + } + + return ret; +} + +static const struct iommu_domain_ops nested_domain_ops = { + .attach_dev = amd_iommu_attach_device, + .free = amd_iommu_domain_free, +}; + +struct iommu_domain *amd_iommu_nested_domain_alloc(struct device *dev, + struct iommu_hwpt_amd_v2 *hwpt) +{ + int ret; + struct iommu_domain *dom; + struct protection_domain *pdom; + + dom = iommu_domain_alloc(dev->bus); + if (!dom) + return ERR_PTR(-ENOMEM); + + pdom = to_pdomain(dom); + dom->type = IOMMU_DOMAIN_NESTED; + dom->ops = &nested_domain_ops; + + ret = nested_gcr3_update(hwpt, dom); + if (ret) + goto err_out; + + return dom; + +err_out: + iommu_domain_free(dom); + return ERR_PTR(-EINVAL); +}