From patchwork Tue Dec 12 12:19:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177306 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682335vqy; Tue, 12 Dec 2023 04:21:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFw+HmDUZX94cJp42hZK13fyRzzlo+S26HFqfgnKF6e+YW+CV4xFFey1v6hC6TeZx1SH7xy X-Received: by 2002:a05:6a20:bcaa:b0:191:60f4:1053 with SMTP id fx42-20020a056a20bcaa00b0019160f41053mr1421760pzb.79.1702383682785; Tue, 12 Dec 2023 04:21:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383682; cv=none; d=google.com; s=arc-20160816; b=vuEGvm51WvsJLtDwDsurp0bkzj1G5Xt50cOyISas6FWyYanOazBHTqvZJcKc5YPjZG pOy6UGP4qK2CeYX09AHSYu2akHCEagzvxTBzBnMjPp81LezmqzD/XyX9snh74Soub6Ct URvk3nlzTz9UpaxmoLIt6eyBF61/gRaCaPsZE3IHdFE1eSXCexhQf7hAPRwGFrzwBAEI mOwvfG3zLEP99nDHg1QQEumKWTXu3f0XgkM2EpwfQnevEMGdGCe06ylloQGCPz2Mgso/ YEjXRdsxxudlPo6elJTGVRlURRhBZynYaM4DwkrxKe/15kWhKpbyM6hQ6+2fPRm2gxaV 3c9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=pbIhtZN7tbeEZN7b/e6iHZByMWn+L/d3BOIBFhKze9A=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=Ac2xo0IUP8jBiNrGLK7BciU8xsJTUOFLUa5w7JZnpYbfJDOPxRau3oEF28hX320E6n JsA8siikeHxmsWqBM6iz0U10++kuuLUzpI6cFetsYud2LPcdrlcDRmPzw9lKOBdl6axi vzaQKEoo2zsg5PxOh9VgRIqg9UahhalJhatRwFx1GOm4MPFYhNv9jf/3lniV26qiTOhP NQ08LYa6MuetaPnGVw2KiJalyNuUTfop9wJwoGDXcSoyUYCCy5EnpCCtz+/c7pSE1bPy fomZwhGjVIFoAKzl8hixluaO2tx2TNd/qGiqmj2bu82gfqhGe0JlVMdGcJURGxT+SZBo UdyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=mBcUHx6Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id b22-20020a6567d6000000b005c603ab4578si7587726pgs.173.2023.12.12.04.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=mBcUHx6Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id B968B804B87A; Tue, 12 Dec 2023 04:21:21 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346541AbjLLMVB (ORCPT + 99 others); Tue, 12 Dec 2023 07:21:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346476AbjLLMUK (ORCPT ); Tue, 12 Dec 2023 07:20:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33EB3F3; Tue, 12 Dec 2023 04:20:10 -0800 (PST) X-UUID: c5ea7b4e98e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=pbIhtZN7tbeEZN7b/e6iHZByMWn+L/d3BOIBFhKze9A=; b=mBcUHx6ZZUu+ywqQriIr/AXnlCRo+afPBm6/YsnRme4V/accePrdqGWzLTkRYiaBPAMG4i6e+nGe7GuM6DLSukknFoFtsjqqVhrooYqZwsY3Ru+ugaD1vdxVLRvJt7P3jHTgZyUu4aSOtnPEguwCVk8hrL+N9agA8rWjSbMrr2I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:bc3a8859-4acb-4962-9f58-fb1a3b65b4b0,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5d391d7,CLOUDID:283b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c5ea7b4e98e811eeba30773df0976c77-20231212 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1777728567; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:00 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 01/17] soc: mediatek: Add register definitions for GCE Date: Tue, 12 Dec 2023 20:19:41 +0800 Message-ID: <20231212121957.19231-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.744200-8.000000 X-TMASE-MatchedRID: +aiIZkdJNeWLwgJA7qJvFMnUT+eskUQPUAjrAJWsTe//evmlVf9xZkN+ V6ZFLcNdK+GE57usLIi8xfjW6NxdqFfnsPC4h9MjSEQN/D/3cG4IYICTzfK2gccfB5qY+d3io8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtZHKDEaeJy4byKRh4CNRN852PVxVMV2ioN9hxljcgqvC+po L87PUishRY09hgyy5B79Evy1WLpYHKWZR2fV44oViLpGR6nqyUwZBgUyJVEbl6Fw8/PpTMRaVvm iAyeA2kc5MSfkiJFI5p3LlElBHTlw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.744200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2D86889AE4343A0DF89ACE741E79DE7F8215F39A453CACB35BE8DDAD111FC7682000:8 X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,RDNS_NONE,SPF_HELO_PASS, T_SCC_BODY_TEXT_LINE,T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:21:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078672748077436 X-GMAIL-MSGID: 1785078672748077436 Add register definitions for GCE so users can use them as a buffer to store data. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- include/linux/soc/mediatek/mtk-cmdq.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 649955d2cf5c..a253c001c861 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -14,6 +14,16 @@ #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) +/* + * Every cmdq thread has its own SPRs (Specific Purpose Registers), + * so there are 4 * 24 (threads) = 96 SPRs in GCE that shares the + * same indexes below + */ +#define CMDQ_THR_SPR_IDX0 (0) +#define CMDQ_THR_SPR_IDX1 (1) +#define CMDQ_THR_SPR_IDX2 (2) +#define CMDQ_THR_SPR_IDX3 (3) + struct cmdq_pkt; struct cmdq_client_reg { From patchwork Tue Dec 12 12:19:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177294 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682070vqy; Tue, 12 Dec 2023 04:20:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IG822nq5/k3LhiQ1XmIfZ828HmQ0tBxgczw/kvI5PtnshH7taVOhkUpunZfK+Tgv+t874pW X-Received: by 2002:a05:6602:459:b0:7b6:f2a7:1882 with SMTP id e25-20020a056602045900b007b6f2a71882mr5969794iov.28.1702383655521; Tue, 12 Dec 2023 04:20:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383655; cv=none; d=google.com; s=arc-20160816; b=j5qAC3bMgwdNRU2IP3xlQw5oSPXo8+OMa+KDoXMYEfQBFo/Xi8SAEcp6zy45IKn4FN 4afM+FHHwG5/ZAKARxOg7q5CE7ACmg2+Jjzi2UCDq+7SVPy03cFmdsxpEDG0Ga305DT2 ciDVL8iwclWdg81A+AysJmubeWKb4tLm1GHeqrSnVqHv34itxo6fuxr+IHXTprzhL3BS b88nChU0HokVqBza40TWrazzTkxpZ5d8GlJpKiopPonWIVKYumfwjAbfLpa4LPFCsOrJ XQcBIFgIKyjNowfBBRmR7KJbgIgMBZXUEqhPIlBvkD9ANEsCk1NLmOIOV+cqMsGtERnE Bspw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=t+paXc0G+J5PIa6eBd5aN09eNdWMzQ/VjFRYNpFI7RI=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=up06NArlDTH/Pu+/Ns6z+Ls37X9mjEIsTAPxI3+jKIBIeNOKQlUtsSfuFPoZmwQAKQ 7CclL41I/4oUvFz8qhV/zQoKhmwSzwIBBV9Aw6HwvHwZlin+wmVyu3Ij/U/rScbt86vo 76BATunZLz/xA7EUBhXoo0GJx+zV6aPx8QyfBvrvgjCrRLlJ/57LcAUVBZE0IXLmm9td NFVZjNxTya+Y+E4vCN9FH/r96M2DTz0w3Ngo7EEHuffhR/urDxsZjPnECbXsSAoU8Uhj 3Kb+Jh9w+kfvLQ4t+Eb570YzWPODh5oiMxONaCH5pvwhBH2YQKp8epkyFXjlczWsiHEV 4zPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=jpBBP4mj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id n10-20020a634d4a000000b005c1b2d279f3si7557539pgl.342.2023.12.12.04.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:20:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=jpBBP4mj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 1FE2980740D4; Tue, 12 Dec 2023 04:20:27 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235097AbjLLMUM (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232296AbjLLMUG (ORCPT ); Tue, 12 Dec 2023 07:20:06 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D620FE3; Tue, 12 Dec 2023 04:20:08 -0800 (PST) X-UUID: c674da0a98e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=t+paXc0G+J5PIa6eBd5aN09eNdWMzQ/VjFRYNpFI7RI=; b=jpBBP4mj43nOsX6+sr2Dv8HHZWVV9TJirtGg3kAo4XDp/LSJr1AHgkWxyNDsnZcF3F+7nlBzbKa07ro17KQ762g7Fj6jbq59GoqnW8i15fUg2C0NyyhodQeTfo38sm74oHdq658+/xi6Lbx+ZOcf/3PAAhKf2QJRc/4xW6DDDEc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:e30eb8ba-ddae-4303-af0d-fc6bea18d36b,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:363b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c674da0a98e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1877912619; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:00 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 02/17] soc: mediatek: Disable 9-bit alpha in ETHDR Date: Tue, 12 Dec 2023 20:19:42 +0800 Message-ID: <20231212121957.19231-3-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.084300-8.000000 X-TMASE-MatchedRID: Rj8ugvyJmEO+Yp4vsvc0tLMsPmSZxbpksvllF/5zpT3jsTquy0JRi0fp kQx2u0Ks+qmOSYkzMxl1VEmx7sTk/25/NyTKlG694bl1FkKDELcoteqd/zXaI/ufvd3T2+v3dHv iJhofy1Hi8zVgXoAltsIJ+4gwXrEtJ0RPnyOnrZJwhH7yAuWrPPJZnPx9vad3szm63XzKi/h9jP F3getekOuu3S58dvEzZv9PVtL7eD1CMnXXKxnDMlJXgzMBvyCJUbx233hKZ3OAhOcaQrQ0U1GyR coeF18qmKP0zzpTAeGwod8xOMKmvA1Aka/KIp/p X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.084300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E5D52D9BAA93CA09F0D377C642A81C5292335B927DF9DD87617EAC2C9A84A53C2000:8 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078644058533964 X-GMAIL-MSGID: 1785078644058533964 ETHDR 9-bit alpha should be disabled by default, otherwise alpha blending will not work. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a456c3e0aee7..e471be3bafc1 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -226,6 +226,7 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, alpha << 16 | alpha, cmdq_pkt); + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, From patchwork Tue Dec 12 12:19:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177298 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682215vqy; Tue, 12 Dec 2023 04:21:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IFLCoam0r5UjdUjVr5IGJZsCPl4q1GQRS9j+ZGyGLm9vF46GuszxxxIPGO6141ifobbtVwG X-Received: by 2002:a05:6870:4e01:b0:1fa:25de:2f6b with SMTP id pl1-20020a0568704e0100b001fa25de2f6bmr7695204oab.23.1702383670374; Tue, 12 Dec 2023 04:21:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383670; cv=none; d=google.com; s=arc-20160816; b=yMSAdE+zBGvX9Cb7NNB/kmlzlwXmBGr363QLma8xnB8NNmox93cRH9VlDBI6X344fn 7hGF9AStSJcXggbIqKEtqAT6Bg+LWp0z+DXgntkMUQBZZrBHSbn9LRDEZM3JTZM95HF+ MkYhgxZFvD8Iqg2M0MNhlWzfVGnS9Y9Uan4nP+cbvpFZXDlrnfuvn6vWzsvwL5Kc+8sG bc9r7L+x9yoUCweX7WsbtzG7qKdcOTizxn1Sy86heD0gmC7TTYI3QDjFrm3p6MXbCz/h YxdKUegplPuPwZ5KNqjZPRIO/tLxlO0W6t6ANTNTVq/1p6Ha7IJCpAxgl6uQgeHLvohu tokw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=V6TtNYHx8gD+ReEuu8s2b4PzcryQf7rZOYfLtaSOUVc=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=lq/idUBCT8gExqQrZitA/vKUh7L61zARTVejMWdv/g6ylFrqANJfhCfg96Low8RkIe UPDLHKCrAdL1dJDwVnRyLWr2FYTecaJCINDBQuCGzy6y2iesu4vxObZxNJM0j4n3BJKQ QWIeFaw5wpCu8yLIM6kZ7pDK5a8PQOPWLuYrcHgN02306SoIjC2SPpuRupMZsmdK8n7D 7vAolIdoUnx597RM7KjemQbOBAHJns5S4XZFFpspLBoVxUI+rw6oCvB0saOJtICe5ZaE nzhu7FO2lM7tqAulz3we28WkhbjrU5xoNOy2G1N9+BnSHxh8KQHiwXhUeeVXpYdmOtVt kWcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=fdyBh02c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id o2-20020a655202000000b005c65dc887dbsi7360317pgp.557.2023.12.12.04.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=fdyBh02c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 3648780A18D2; Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346571AbjLLMUh (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346475AbjLLMUK (ORCPT ); Tue, 12 Dec 2023 07:20:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33DFDF2; Tue, 12 Dec 2023 04:20:10 -0800 (PST) X-UUID: c60abc5698e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=V6TtNYHx8gD+ReEuu8s2b4PzcryQf7rZOYfLtaSOUVc=; b=fdyBh02cWf4kzkU9wPUdkb0z8zeKknt4uvF4Ma/vymubuMx1IZqJ95e50gUue8kRfSttnwzfYq3e13cgJdU3VEglEBP8Xj/VxedIjuO8Sdw3FjS130P9rBGpBNGRx3Fj5UgyefgGO8mziJVOeAJ9HikjMFf0wu2IGwvFGwgYXiE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:6d670ee4-9aa9-428a-acb5-eca9aee2d050,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:273b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c60abc5698e811eeba30773df0976c77-20231212 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1196575877; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:00 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 03/17] dt-bindings: display: mediatek: ovl: Modify rules for MT8195/MT8188 Date: Tue, 12 Dec 2023 20:19:43 +0800 Message-ID: <20231212121957.19231-4-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078659781918894 X-GMAIL-MSGID: 1785078659781918894 Modify rules for both MT8195 and MT8188. Hardware capabilities include color formats and AFBC are changed since MT8195, stop using the settings of MT8183. Acked-by: Rob Herring Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/display/mediatek/mediatek,ovl.yaml | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 92e320d54ba2..b37208a9e370 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -26,20 +26,18 @@ properties: - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl + - mediatek,mt8195-disp-ovl - items: - enum: - mediatek,mt7623-disp-ovl - mediatek,mt2712-disp-ovl - const: mediatek,mt2701-disp-ovl - items: - - enum: - - mediatek,mt8188-disp-ovl - - mediatek,mt8195-disp-ovl - - const: mediatek,mt8183-disp-ovl - - items: - - enum: - - mediatek,mt8186-disp-ovl + - const: mediatek,mt8186-disp-ovl - const: mediatek,mt8192-disp-ovl + - items: + - const: mediatek,mt8188-disp-ovl + - const: mediatek,mt8195-disp-ovl reg: maxItems: 1 From patchwork Tue Dec 12 12:19:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177302 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682254vqy; Tue, 12 Dec 2023 04:21:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IF47YywcXLJKfv0RVW0Bf9+AmzprVZCgs0KqIlRQOom5MADCdv7kBkpubBVmoCqxaTGXAbH X-Received: by 2002:a05:6a20:9492:b0:18f:b988:5aa1 with SMTP id hs18-20020a056a20949200b0018fb9885aa1mr2865679pzb.37.1702383673494; Tue, 12 Dec 2023 04:21:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383673; cv=none; d=google.com; s=arc-20160816; b=mhQyCw+fWLQrGYzkBg5aWUc8mq2jJKjOt4LwIVbwQrcW9K+VB4GgFYOPk80X407kKY M+gj9dYryhfbA1qWe9EnSQnRZamSQMuUYRXZa97MJ5j7lGZE3MI4/v6PdFZzS2OIKB6G aW+1okisR7LsIeDNJ4GOExrQ67lnwS2iDb7Um//4ef+QRT8fX/Z4WwukuTGzMNwHlOzH YWqZaT5hl0vsvR0RTyy1uPv2k6y6FeDtw9XVjgh3p/9g85pYOziwUZAGOmZ1RaS/Q1Kl 0SG28j3uYghY/VpMcQu7WCSIGaJXr3wsgKQMfoWbrbvdptEgaxmurlJhncW/0yLAG4oA 5l8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qLWx+HZRKPvH3+Dk9QJq2Dd9wV6RcWPjJPAYx49RqJs=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=bSxTRVGfS/TwMa8IqcBxHR9yTDacjQrjXB9dR3GJ+5ouHr9nr9sV5z82lISoC9WzvJ S+kSAy84hvWY/2to7TMpXIXTlMmlIfEn2mTqVIpTTZSa+Ousfc1wvReWjqj2EZC6HTpK bInt/9O1NHMFfDP7wiiceEL/yNYiqGzDNYP7aMSmKmyxIxP4LnIrPZYhwWYE2h2xeBaV WuBfru2FDPAWfmOPFCGl3MGdA8N9kSIyKSfM/bkOJWOhIeELvUKaIOaY7glYlcQWX9yf Xm5pvcaNhz8uOmcKdZA9h+ZxNxDd1TXCU2CjwbhBbg2CQ6HqR7nvOiixQRpKGMmDuJ5j IXWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=avnwPJz1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id u24-20020a631418000000b00584b6af3b9fsi7838971pgl.524.2023.12.12.04.21.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=avnwPJz1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id C0DCC80A18CE; Tue, 12 Dec 2023 04:21:03 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346490AbjLLMUy (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232079AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D71F5FD; Tue, 12 Dec 2023 04:20:12 -0800 (PST) X-UUID: c6707abe98e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qLWx+HZRKPvH3+Dk9QJq2Dd9wV6RcWPjJPAYx49RqJs=; b=avnwPJz1GnVsr+ASIO9IR1mFQIuA9HoeCABc7j2kXioWPy3kSlrVqpAjDlk3qkpDgisUuOsopz1BGUDu1NB6KEgOlT/Vnr1AsYR8t2fdIfLPwRMcZAzplyvqj1UoTG+0of6IMBayVmIQnmQ6JtIMbFqEzud3/iJglI8j+TyLd2A=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:afa2bb8c-3f41-4ee8-ba6c-3349d0955466,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5d391d7,CLOUDID:0e7d16bd-2ac7-4da2-9f94-677a477649d9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c6707abe98e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1101473199; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:00 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 04/17] drm/mediatek: Add OVL compatible name for MT8195 Date: Tue, 12 Dec 2023 20:19:44 +0800 Message-ID: <20231212121957.19231-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.158800-8.000000 X-TMASE-MatchedRID: GIpmbigRs3bREKzvS64+oRWCVBr+Ay986SXuwUgGH0jvnm3ZesFzgvKC 81FnsF5IThbvLLI8RvOlEtDJyVR88h8TzIzimOwP0C1sQRfQzEHEQdG7H66TyH4gKq42LRYk3IX 35wrrNuzRJKYA5zmYK99uNaKbMwndq/PWrh7GSAB+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.158800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 44375C04DBE7903F73D87F3E6318336E804BBBD17EA592E22860AF42C7C3B7A82000:8 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:21:04 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078662704325293 X-GMAIL-MSGID: 1785078662704325293 Add OVL compatible name for MT8195. Without this commit, DRM won't work after modifying the device tree. Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index eecfeb8fbde1..5d551bff6b3f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -767,6 +767,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8192-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8195-disp-ovl", + .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt8192-disp-ovl-2l", From patchwork Tue Dec 12 12:19:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177305 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682275vqy; Tue, 12 Dec 2023 04:21:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IHGjfxAr+BbBnugAhcLlfgDV6W+2AC3se2tCcnTU1DBdDpW5X+I89nzLxP3bpJOKI0c102S X-Received: by 2002:a17:902:ea06:b0:1d0:b42f:e40f with SMTP id s6-20020a170902ea0600b001d0b42fe40fmr6942492plg.30.1702383676109; Tue, 12 Dec 2023 04:21:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383676; cv=none; d=google.com; s=arc-20160816; b=BWZ78kx229nxIqS9AYJBYA8iYZNC/Qp29skGnRxzgFogz/Urb/i4ffrCu9/4dz6z9q PxDKEUs9SN2f/EKkjtz+PQHub47yxsTAdfFHe76kKkR/2wUrpYByt8bkIM48e0wNKWIZ eFHS3hRp4jK/m+W2lKoaFIGtXOVO8PvAmD3eGGZm0Q7SGCS7MgeQ5Bjt4VGUmGOMkcy9 AXZCNBtk1Z5idOVzW931eRSTN1fDWb16EUmQaHXHyW8rKBIPIugtkH5M15IH0/ZlLLWp OPI9XxwfqkI+RtMAq5p0pBIAlqHVOE0qCcqriliK2Md6dvPv9cqZ3mNJJSUymETNwS11 OzqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ka6DlWr8O5KPNFH1pdRfFP5nTUuhgOMLMTgYtTTQtV0=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=gFC0bU+grmPRvVAVF6UagYkQf9+KUcU1tKdrd+ZDdrfALIf6hoMVnTlj9TNiRn8HNV daFHMU6dA/qDTfmbq398LJ4YndDs1sTC/ciuNzSE5m6QRMVdmWiFtAb66qYBkNRBbeYI mU08gKaatIf9IT+mCiOuGAoneY+hLJgCK64k51Mb43LBwAIJ4AbW06W3I7Lr09PiJ70d eZDTfcxQzyzevGdNaEQDL6mbT/99xBgyEaVtp7MY7timbApdofYYe83TyG7c8u2OSbVD QcOoHrB2Nw+WrmfidpQbrEijWgkfu5qrGndp/yaBa2mKkbJ+snw8EdXGYFwEdXISqzKT bNag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=VyBYMoOC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id u9-20020a170902e80900b001d091c3ab04si7997790plg.355.2023.12.12.04.21.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=VyBYMoOC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 834468088694; Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346588AbjLLMUk (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346481AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33F37F4; Tue, 12 Dec 2023 04:20:10 -0800 (PST) X-UUID: c5ef250e98e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ka6DlWr8O5KPNFH1pdRfFP5nTUuhgOMLMTgYtTTQtV0=; b=VyBYMoOCJ7ACDsbZtMtc869NmcA0a/uX/fXR2ulxUaRKvU3WTsFl7wfLb8l1uqdH6t5gffFrY1B5AJ3TLYgxrHCqG27V5WcqM4PGO8RKkf7XHjbFlCn6IWAvByxFDIsQaO5Fa3yXCyaMhrLhHSaRzjSFQdxynyop4xaLvBhxAxU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:27f7bae1-a772-4223-89c8-73aeeab04431,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:7ea8b373-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c5ef250e98e811eeba30773df0976c77-20231212 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 990221556; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:00 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 05/17] drm/mediatek: Set DRM mode configs accordingly Date: Tue, 12 Dec 2023 20:19:45 +0800 Message-ID: <20231212121957.19231-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--11.930400-8.000000 X-TMASE-MatchedRID: x3Ubk3t+gcy00StIHoZF5pJAa1C/+FcunhD9A3Sa7pYs/uUAk6xP7PlY oV6p/cSxNFCzr/YjTjOc2wuft1o14LvaJG+XDhc2DB+ErBr0bANn+sA9+u1YLX5h6y4KCSJcShj sNhfAcgIZ/p8qQ24bJaaYJmaMPc4/jb9Ltm8ZneZu+yxbbkYIFifyNCEwujCFXhmWufKBF2SRXS 5OutA+GekoCEC/ht5M70Qm3YXk6SwfE8yM4pjsDwtuKBGekqUpI/NGWt0UYPDRKhK/CnIxuNRkc Elpi5gOLxOGdstXMZz9Oo/9meFJyeSPyTK27pvM X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--11.930400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: D0B24F9408CB0F914E97D4B49733F9498BF49BB0989FC96017ABFA7DF88B43D12000:8 X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,RDNS_NONE,SPF_HELO_PASS, T_SCC_BODY_TEXT_LINE,T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078665631252072 X-GMAIL-MSGID: 1785078665631252072 Set DRM mode configs limitation accroding to the hardware capabilities. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 ++++++++++++++++++-------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5d551bff6b3f..a4b740420ebb 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -304,6 +304,7 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .conn_routes = mt8188_mtk_ddp_main_routes, .conn_routes_num = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num = 2, + .max_pitch = GENMASK(15, 0), }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -318,6 +319,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .main_path = mt8195_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num = 2, + .max_pitch = GENMASK(15, 0), }; static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { @@ -325,6 +327,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), .mmsys_id = 1, .mmsys_dev_num = 2, + .max_pitch = GENMASK(15, 0), }; static const struct of_device_id mtk_drm_of_ids[] = { @@ -463,16 +466,16 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (ret) goto put_mutex_dev; - drm->mode_config.min_width = 64; - drm->mode_config.min_height = 64; - /* - * set max width and height as default value(4096x4096). - * this value would be used to check framebuffer size limitation - * at drm_mode_addfb(). + * Set default values for drm mode config + * these values will be referenced by drm_mode_addfb() as + * frame buffer size limitation. */ - drm->mode_config.max_width = 4096; - drm->mode_config.max_height = 4096; + drm->mode_config.min_width = 1; + drm->mode_config.min_height = 1; + drm->mode_config.cursor_width = 512; + drm->mode_config.cursor_height = 512; + drm->mode_config.funcs = &mtk_drm_mode_config_funcs; drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; @@ -502,6 +505,15 @@ static int mtk_drm_kms_init(struct drm_device *drm) for (j = 0; j < private->data->mmsys_dev_num; j++) { priv_n = private->all_drm_private[j]; + if (priv_n->data->max_pitch) { + /* Save 4 bytes for the color depth (pitch = width x bpp) */ + drm->mode_config.max_width = priv_n->data->max_pitch >> 2; + drm->mode_config.max_height = priv_n->data->max_pitch >> 2; + } else { + drm->mode_config.max_width = 4096; + drm->mode_config.max_height = 4096; + } + if (i == 0 && priv_n->data->main_len) { ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, priv_n->data->main_len, j, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index d2efd715699f..3d6c1f58a7ec 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -41,6 +41,7 @@ struct mtk_mmsys_driver_data { bool shadow_register; unsigned int mmsys_id; unsigned int mmsys_dev_num; + u32 max_pitch; }; struct mtk_drm_private { From patchwork Tue Dec 12 12:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177307 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682423vqy; Tue, 12 Dec 2023 04:21:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtZDBN6yePzUKYtNfnyFZj6tB6hOiTn6tcLDn55RBy7rQXfcOaKwKHDMh0NmkDwM/Vi6pR X-Received: by 2002:a05:6a00:10c1:b0:6cb:a1fe:5217 with SMTP id d1-20020a056a0010c100b006cba1fe5217mr6204811pfu.16.1702383692260; Tue, 12 Dec 2023 04:21:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383692; cv=none; d=google.com; s=arc-20160816; b=mScWpJQmRCix0ziEUI9wyPVpo+Z0ZpwDx2x3sOiBha6FAEGuH1H+44fRsxmO4jiJ/t nA8jka7RpT9zq8N9eZbuaBA+VrE6G6A0d6uWgDt4JuqC+FfWUIFpPVpx/KLOfmK0fg8H A0BzvOVT8D+YjU//o/Fzo2OFWKMmNrbHza10lAV4etEkjxFQXc3VCs14i4ouSZlkOq3P iecYgBNwZRiwftaKb7t10Ccv9IGkTPLBmB08nxlMlay6JzAiCZ6ypyM8v1QySiZuzlFO kygS/RqUq0rekIyIdAuY3eDScZnJq8si0Nl5x+jlBCHbNEbPUonkAvgDEL4WSAh2L++a +eew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=K4w5up8ZLqgyPQD8H2AboWYB5hZ/MbRF9/Caa0P/nFY=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=N9SlYnbEZfX7LQ9FnmYS3JVMLU0YmXegh2837ab3ZyEokZPZyPXBmcpg1Pz6GAgiLd R6t+S7g3cD8Oq9r34HjCSJxr+lwG1oVXKS1vunB5FZ7CAYik/n/vdHsfvkllSDd4zRBU AalawOsJNntYh2Dh2CLSXm5LKoiTD8/ocVHBVgx2Cb6iaGC5/8mUIdUM2hkq82GVXWR0 cJQrgzEKiiqci6VPEylQGJzqpjMaaGO0WXAt53sBTRnsLab0gW8g5WZ/p8nXUKNHn3rR iBFcCMtoXnFrLNRaC9StDVipFmaIO1rN99Z7sQb9nT6fIvIJdjLbnKppXLLgIg17lcP7 fU9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=HhuCOvW4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id t42-20020a056a0013aa00b006ce6ad886c8si7829630pfg.177.2023.12.12.04.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=HhuCOvW4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 03EDD806D7E8; Tue, 12 Dec 2023 04:21:27 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346511AbjLLMU5 (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232539AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6076F5; Tue, 12 Dec 2023 04:20:11 -0800 (PST) X-UUID: c66879d698e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=K4w5up8ZLqgyPQD8H2AboWYB5hZ/MbRF9/Caa0P/nFY=; b=HhuCOvW4IhLy5vj+kqHvm32ou+xjclkW82NhRao1Nuj8UBZyP/CKXGr+xru2a7713lAACW3AzQ4KPDRcuKus9FSjLDq5fKBWxU6Vi/x9WCUOuDnVNd1EpxuIteQ6aerOwNSDdOHiyPs/i2FIYkR834XhLc5wMs/Cli80cYxX72s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:2491e0dc-58ac-4849-9ac7-9c3af3b7cdde,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:383b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c66879d698e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1401706049; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 06/17] drm/mediatek: Support alpha blending in OVL Date: Tue, 12 Dec 2023 20:19:46 +0800 Message-ID: <20231212121957.19231-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:21:28 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078682132307659 X-GMAIL-MSGID: 1785078682132307659 Support premultiply and coverage alpha blending in Overlay. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 73 +++++++++++++++++-------- 1 file changed, 51 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 5aaf4342cdbd..66074c2d917c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -39,6 +39,7 @@ #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) +#define OVL_CONST_BLEND BIT(28) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -52,13 +53,16 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) -#define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) -#define OVL_CON_CLRFMT_RGB (1 << 12) -#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) -#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) -#define OVL_CON_CLRFMT_UYVY (4 << 12) -#define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_CLRFMT_MAN BIT(23) +#define OVL_CON_BYTE_SWAP BIT(24) +#define OVL_CON_RGB_SWAP BIT(25) +#define OVL_CON_CLRFMT_RGB (1 << 12) +#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) +#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_CLRFMT_MAN) +#define OVL_CON_CLRFMT_UYVY (4 << 12) +#define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -208,14 +212,12 @@ void mtk_ovl_clk_disable(struct device *dev) void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); - if (ovl->data->smi_id_en) { - unsigned int reg; + if (ovl->data->smi_id_en) + reg |= OVL_LAYER_SMI_ID_EN; - reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); - reg = reg | OVL_LAYER_SMI_ID_EN; - writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); - } + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } @@ -274,7 +276,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w, if (w != 0 && h != 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR); + + /* + * The background color should be opaque black (ARGB), + * otherwise there will be no effect with alpha blend + */ + mtk_ddp_write_relaxed(cmdq_pkt, 0xff000000, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_ROI_BGCLR); mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); @@ -357,7 +365,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx, DISP_REG_OVL_RDMA_CTRL(idx)); } -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -376,18 +385,30 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: - return OVL_CON_CLRFMT_ARGB8888; + return blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + return OVL_CON_BYTE_SWAP | + (blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888); case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + return blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: - return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_RGB_SWAP | + (blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888); case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: @@ -408,6 +429,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, unsigned int fmt = pending->format; unsigned int offset = (pending->y << 16) | pending->x; unsigned int src_size = (pending->height << 16) | pending->width; + unsigned int blend_mode = state->base.pixel_blend_mode; + unsigned int ignore_pixel_alpha = 0; unsigned int con; bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; union overlay_pitch { @@ -425,9 +448,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, return; } - con = ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |= OVL_CON_AEN | OVL_CON_ALPHA; + con = ovl_fmt_convert(ovl, fmt, blend_mode); + if (state->base.fb) { + con |= OVL_CON_AEN; + con |= state->base.alpha & OVL_CON_ALPHA; + } + + if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) + ignore_pixel_alpha = OVL_CONST_BLEND; if (pending->rotation & DRM_MODE_REFLECT_Y) { con |= OVL_CON_VIRT_FLIP; @@ -444,8 +473,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs, - DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, From patchwork Tue Dec 12 12:19:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177295 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682153vqy; Tue, 12 Dec 2023 04:21:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IFvNzl18NZLQEaRuR/FzKZqvhdw8mSwxk/aCkbDJLrfB4FO3BcSfMj3HWGUFrtn7ZMNr6bX X-Received: by 2002:a17:90a:1349:b0:28a:d20c:de4d with SMTP id y9-20020a17090a134900b0028ad20cde4dmr82403pjf.78.1702383665579; Tue, 12 Dec 2023 04:21:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383665; cv=none; d=google.com; s=arc-20160816; b=waCMhk4JOG2prKsYB0NtmaXJ5jAT6oBg5cEDPM7hRCGzofjlyXZ7UQZylS0+b3Xz+v vMu0oCbBYa2Tojh3crw6BNfq6ct+A8smB49jz3YoI0u9BJYTrLpa/LLwJhWUzPsNC0c3 jVe+S1NCywM1fLJjIfn674NsRg3HjqHrMbtLWehKqv3O7Yxy6PSFdLX+sFQ+CHueaJ3k 5MwspD9+MLfQH52uzSC8F273+e9rIJSMURqoK1ybd9RH61YmEbXaB0eF5dv5FLSJ3JA0 gYFdrQ3h7FL2a6I/mqdSarMDZwb2ioRxC4lFbcKIm/5RzJQRrICeKAgdEysY+TcnwFsU Nmxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RWVos3ttma+ouGUpqkowB6aiHNm3iis8v3nPP5nxLek=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=ATJ5RX6Dq1cxSKanU6qG0pyOiGV1Zz/9ub7+/ta3qQEkx8SRqRLn2Eh7Ef45r1x1n9 tDtwvyVqkvr2qnEyCmj/NPswV2wUhMV+/ANz8MZ7RXTQM8E83ZFRfOuXed31CnUz9bY4 yGrlU4tqhzyfRx9psqBWf9tAZQz52l91DoKeyQQYyYQeo7lYMCgj9SKDoMm187MMZ/Zw ANT4DTeUH1Kes3hDNYgJgFYyDnVI6geyMkAry+JObp5ymeyd5Ss+HtvDrnlKDk27frxi 3ik/s7Ao5W1mjyHN5rNZC4SRp8TZQ+yBPGG8dI/dDxXDDvShF1NhzdMiIZkI7pHVm1cQ BO0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=sNHKt1qE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id m5-20020a170902768500b001d0af284622si7642624pll.427.2023.12.12.04.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=sNHKt1qE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 3CBC180A366D; Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346565AbjLLMUe (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346474AbjLLMUK (ORCPT ); Tue, 12 Dec 2023 07:20:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3312AED; Tue, 12 Dec 2023 04:20:10 -0800 (PST) X-UUID: c60dd12098e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RWVos3ttma+ouGUpqkowB6aiHNm3iis8v3nPP5nxLek=; b=sNHKt1qEZDijnm5ZKrZMBmqosskfDxLvBgwJoYtaUXtKJ5TTHqjaw2tmGaX343+V0Xruar65JvahX59G8PDcRrttDEKdES3jVU8EODllnz9eGETBvUM7P+V6ASoiGRTD+4z/3XBY8srlNEDwL8RLKz+aQXj/ZTrvSulh+rZ4o3Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:41375495-af01-497d-9d39-cd7791029042,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:00fd94fd-4a48-46e2-b946-12f04f20af8c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c60dd12098e811eeba30773df0976c77-20231212 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 511087762; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 07/17] drm/mediatek: Support alpha blending in Mixer Date: Tue, 12 Dec 2023 20:19:47 +0800 Message-ID: <20231212121957.19231-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078654360735869 X-GMAIL-MSGID: 1785078654360735869 Support premultiply and coverage alpha blending in Mixer. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 73dc4da3ba3b..73c9e3da56a7 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -35,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -153,7 +155,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_pending_state *pending = &state->pending; unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x; unsigned int align_width = ALIGN_DOWN(pending->width, 2); - unsigned int alpha_con = 0; + unsigned int mix_con = NON_PREMULTI_SOURCE; + bool replace_src_a = false; dev_dbg(dev, "%s+ idx:%d", __func__, idx); @@ -165,19 +168,28 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, return; } - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; + mix_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA); - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true, - DEFAULT_9BIT_ALPHA, + if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE) + mix_con |= PREMULTI_SOURCE; + + if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a = true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), - 0x1ff); + mtk_ddp_write(cmdq_pkt, mix_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, BIT(idx)); } From patchwork Tue Dec 12 12:19:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177296 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682162vqy; Tue, 12 Dec 2023 04:21:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4Klj3FfnfTExzj9gasvpwoka9Pag4wNSWz6Bo7dXvVU5GnX7c+394Qaa4fQeGmNlPc8+u X-Received: by 2002:a05:6358:7e83:b0:16e:33e:3a9c with SMTP id o3-20020a0563587e8300b0016e033e3a9cmr4830070rwn.6.1702383666440; Tue, 12 Dec 2023 04:21:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383666; cv=none; d=google.com; s=arc-20160816; b=R8iLVnDXw896eI1R3fGUDt7vd1F7RLe4rB+Pcq/Xe6DAeTQC1uLmYNKG9N2TkzJVeR NEDwEZfXCdNFfNKfGGt9MmrHNxoFVrxchlh0dElQrlvOoPt7SR71+u26/Ef6ARahBOYv Oqa8ZWIx6UtaKSOtSv7qJ71NpYKoGXo14Mm3mpYQtGYe7ua9OILiTkbA6ZQXpd421aLE i9yBz1D/b6iuirj7Xh3Uo/+ogkpiv9BQ5box4v4vVvMSTsBRFjD20txfE3KRHk759Cwl BrysdBbM228ktylPasQyi52KtzBOOa73shhplDUmrk9sGBkScTGACHqRblMX6oE1+7Lq wL6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=6ySY1u/YNaA7jfhX55xp0CtWVrzD0erxT1NWG3Ec/Vo=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=N0JBGWr6EJpgdeGhsvDqNx2xUOiroLWcX4bdqjGJXhlv8VUhyfLbmR8T4ADcxP5qkI 3c6AMXjbh7XORCvzxUCFV+pO7Ce1L9A1Jz5YCY9gk6HwjNpZJuxaYBCYORmFjWXLP04x yZ2FsnrSWJxZ8gpWugro3kv5XDXoTbpK3V2zbaHD3XxDbFs4di2U9z60TOZCxRLTnoUS BeiWRsB1f8FSdbStlnudP14Rwsjt7Iuy7iQADkVgcrsj2Nh2X3gZkwH+ercuWu0OCR/e v7SWKdaLQw2lpq2NFvv+k9tkS0/CoNCzaMluXsZaMGjlP3wd/Cln7WUeePZ5fAeUCv4d z/rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=OIEbJsAG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id z2-20020a63e102000000b005aa83686f32si7872578pgh.42.2023.12.12.04.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=OIEbJsAG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 3A8A18096462; Tue, 12 Dec 2023 04:20:32 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235108AbjLLMUP (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232461AbjLLMUG (ORCPT ); Tue, 12 Dec 2023 07:20:06 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5AEEC3; Tue, 12 Dec 2023 04:20:09 -0800 (PST) X-UUID: c6ccf47498e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6ySY1u/YNaA7jfhX55xp0CtWVrzD0erxT1NWG3Ec/Vo=; b=OIEbJsAG8If+T82xYPUBlgMMcstui73Dbqn9SEvN+8rRZU2HYibvLcB9rpFBInAlveVG1WxEJpeIZnfkUukI8pPT193NurNO4/lgd9Z2HKZuF7gO1V3cOkBmQlu49oQ/0H6jKcWBiqCJEatLbKxWiqaEg9qJOlyay3u7YAsu9bQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:b8749653-df68-4fb8-9bbc-43700a6fcc63,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:373b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c6ccf47498e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 594440457; Tue, 12 Dec 2023 20:20:03 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 08/17] drm/mediatek: Support alpha blending in display driver Date: Tue, 12 Dec 2023 20:19:48 +0800 Message-ID: <20231212121957.19231-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.676900-8.000000 X-TMASE-MatchedRID: uP1aVdOuidn2fv0LTPfvM6MVgdN9w+TCG9Itfzsy8/Xvnm3ZesFzgvKC 81FnsF5IrUhQzMxACbp+6n5OByhL/9S/P7msP4phXP5rFAucBUF9LQinZ4QefPcjNeVeWlqY+gt Hj7OwNO31Kzk40dEY9ZuHU9bZjqh9ETalZivxO7S1Qc3P+ghxGHPWA7TjQr4H X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.676900-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 430A300697861B49F3FF941E41A8CF8D528CC0377473359CF40861FC00E808A82000:8 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078655323125441 X-GMAIL-MSGID: 1785078655323125441 Support alpha blending by adding correct blend mode and alpha property in plane initialization. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index 9208f03b3f8c..dfd81172a940 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -349,6 +349,17 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, DRM_INFO("Create rotation property failed\n"); } + err = drm_plane_create_alpha_property(plane); + if (err) + DRM_ERROR("failed to create property: alpha\n"); + + err = drm_plane_create_blend_mode_property(plane, + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE)); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + drm_plane_helper_add(plane, &mtk_plane_helper_funcs); return 0; From patchwork Tue Dec 12 12:19:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177299 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682223vqy; Tue, 12 Dec 2023 04:21:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IFN4V2bzIl7tXIX1nNrklGWKM7OPD6amdcvDMa653EolYnMeZBtjGkvr+6+9k8QYvj/2uZV X-Received: by 2002:a92:cd8e:0:b0:35d:a1b9:9c16 with SMTP id r14-20020a92cd8e000000b0035da1b99c16mr6858160ilb.19.1702383670961; Tue, 12 Dec 2023 04:21:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383670; cv=none; d=google.com; s=arc-20160816; b=ABnFLW7I8nVtqcpZQIFkJYPrZeDR+2ENo8zsRjdQEvYkIAFR2DXqRztDEQ1nTLTh5p V95r4C1zonR3VAtaKAKdD4EE7ElJpsQVdvDdPOsBGxVkdRhncRj9dn27/oz7s6n5X1IM cWpjsA2Cq02EqqIU7L+OX3oYOBumHZgne4Hp0DXTxx2hrIdBo+g+bVxFMsCRcHBSnr0p y/gOmmH/2X+bnF0Jp4oznpyrmGg2uVBleE4vQlSaqkXodOGZQreXm3sZoYtK9lhCbnOt dLMJZ8RwnItw7hqOjEmkd2GTHWhRkdI6whefhjoJQM5yQZTLPN6j0ZoMewN8DgS+FrJJ VsHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ieYGvdKX/O8oWqSbJuyH2sRjtlQXogz01qgELDwpc6A=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=y+AgpiC3xNnJdWXJKYjOo4HeACRrHZaw2XNJVzJK8+2EXz1ml+9Pb5LqJPabIf8EPJ kaZJmY/Ij4YuJMYDXNyMih0xPT96cyq2bzgScdoaY+ADVkhw7nlhpgJTQzRRD79Ueyig 2yVlCWGX7XKDHZm/3bPqUO1rLtmcIcWuEgGZs/lVa9IXnhlTRHCs0X0VohEfmxwgNiic ct8O/AqDhZ4lznyPbOIKGZRquDXfSsYpKISzktivL7+kRrU/NtUMof0FPMqqy16TQShN wVG7ZKRxK4iN+oRhy43rGyJgE42ovO/N+Gioe6QsokQbkzAr5k/HyOhPcuSOak6rACvK lH/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Pwk4570k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id f6-20020a631f06000000b005c66bb23ba2si7763186pgf.563.2023.12.12.04.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Pwk4570k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 68A8480A18D5; Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346692AbjLLMUs (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230234AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EA6FFE; Tue, 12 Dec 2023 04:20:12 -0800 (PST) X-UUID: c6b7078698e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ieYGvdKX/O8oWqSbJuyH2sRjtlQXogz01qgELDwpc6A=; b=Pwk4570kvF2ndYzjojfqUVXjBqsGYeBBsAOFqbMTUIlO8QQJOMAgE+vlqoqew7NSEmbpIAur7X8FvJy5VHXr3+YrLWvrZNPTj5Obaj0CrcguqffUypyUxmaBfV8kt0bzruAQl0/aLjjLNYqXtLYun2v7dtRdwTkpAC1kZLy0V5g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:c78da633-ee65-4734-b21a-87ad4ca76620,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:4f3b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c6b7078698e811eeba30773df0976c77-20231212 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 794778524; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 09/17] drm/mediatek: Support CSC in OVL Date: Tue, 12 Dec 2023 20:19:49 +0800 Message-ID: <20231212121957.19231-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078660143124994 X-GMAIL-MSGID: 1785078660143124994 Support Color Transform Control (CSC) in Overlay to do Y2R or R2R conversion. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 121 +++++++++++++++++++++++- 1 file changed, 118 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 66074c2d917c..7e217142d0c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -31,6 +31,7 @@ #define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define OVL_LAYER_AFBC_EN(n) BIT(4+n) +#define OVL_OUTPUT_CLAMP BIT(26) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) @@ -44,6 +45,23 @@ #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 #define DISP_REG_OVL_CLRFMT_EXT 0x02D0 +#define DISP_REG_OVL_CLRFMT_EXT1 0x02D8 +#define OVL_CLRFMT_EXT1_CSC_EN(n) (1 << (((n) * 4) + 1)) +#define DISP_REG_OVL_Y2R_PARA_R0(n) (0x0134 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_RMY (GENMASK(14, 0)) +#define DISP_REG_OVL_Y2R_PARA_G0(n) (0x013c + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_GMU (GENMASK(30, 16)) +#define DISP_REG_OVL_Y2R_PARA_B1(n) (0x0148 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_BMV (GENMASK(14, 0)) +#define DISP_REG_OVL_Y2R_PARA_YUV_A_0(n) (0x014c + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_YA (GENMASK(10, 0)) +#define OVL_Y2R_PARA_C_CF_UA (GENMASK(26, 16)) +#define DISP_REG_OVL_Y2R_PARA_YUV_A_1(n) (0x0150 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_VA (GENMASK(10, 0)) +#define DISP_REG_OVL_Y2R_PRE_ADD2(n) (0x0154 + 0x28 * (n)) +#define DISP_REG_OVL_R2R_R0(n) (0x0500 + 0x40 * (n)) +#define DISP_REG_OVL_R2R_G1(n) (0x0510 + 0x40 * (n)) +#define DISP_REG_OVL_R2R_B2(n) (0x0520 + 0x40 * (n)) #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -56,6 +74,8 @@ #define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) #define OVL_CON_RGB_SWAP BIT(25) +#define OVL_CON_MTX_AUTO_DIS BIT(26) +#define OVL_CON_MTX_EN BIT(27) #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) @@ -63,6 +83,7 @@ #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_MTX_PROGRAMMABLE (8 << 16) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -76,6 +97,22 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) +static inline bool is_10bit_rgb(u32 fmt) +{ + switch (fmt) { + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return true; + } + return false; +} + static const u32 mt8173_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -217,6 +254,14 @@ void mtk_ovl_start(struct device *dev) if (ovl->data->smi_id_en) reg |= OVL_LAYER_SMI_ID_EN; + /* + * When doing Y2R conversion, it's common to get an output + * that is larger than 10 bits (negative numbers). + * Enable this bit to clamp the output to 10 bits per channel + * (should always be enabled) + */ + reg |= OVL_OUTPUT_CLAMP; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } @@ -256,9 +301,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); - if (format == DRM_FORMAT_RGBA1010102 || - format == DRM_FORMAT_BGRA1010102 || - format == DRM_FORMAT_ARGB2101010) + if (is_10bit_rgb(format)) bit_depth = OVL_CON_CLRFMT_10_BIT; reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); @@ -458,6 +501,78 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, (state->base.fb && !state->base.fb->format->has_alpha)) ignore_pixel_alpha = OVL_CONST_BLEND; + /* need to do Y2R and R2R to reduce 10bit data to 8bit for CRC calculation */ + if (ovl->data->supports_clrfmt_ext) { + u32 y2r_coef = 0, y2r_offset = 0, r2r_coef = 0, csc_en = 0; + + if (is_10bit_rgb(fmt)) { + con |= OVL_CON_MTX_AUTO_DIS | OVL_CON_MTX_EN | OVL_CON_MTX_PROGRAMMABLE; + + /* + * Y2R coef setting + * bit 13 is 2^1, bit 12 is 2^0, bit 11 is 2^-1, + * bit 10 is 2^-2 = 0.25 + */ + y2r_coef = BIT(10); + + /* -1 in 10bit */ + y2r_offset = GENMASK(10, 0) - 1; + + /* + * R2R coef setting + * bit 19 is 2^1, bit 18 is 2^0, bit 17 is 2^-1, + * bit 20 is 2^2 = 4 + */ + r2r_coef = BIT(20); + + /* CSC_EN is for R2R */ + csc_en = OVL_CLRFMT_EXT1_CSC_EN(idx); + + /* + * 1. YUV input data - 1 and shift right for 2 bits to remove it + * [R'] [0.25 0 0] [Y in - 1] + * [G'] = [ 0 0.25 0] * [U in - 1] + * [B'] [ 0 0 0.25] [V in - 1] + * + * 2. shift left for 2 bit letting the last 2 bits become 0 + * [R out] [ 4 0 0] [R'] + * [G out] = [ 0 4 0] * [G'] + * [B out] [ 0 0 4] [B'] + */ + } + + mtk_ddp_write_mask(cmdq_pkt, y2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_R0(idx), + OVL_Y2R_PARA_C_CF_RMY); + mtk_ddp_write_mask(cmdq_pkt, (y2r_coef << 16), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_G0(idx), + OVL_Y2R_PARA_C_CF_GMU); + mtk_ddp_write_mask(cmdq_pkt, y2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_B1(idx), + OVL_Y2R_PARA_C_CF_BMV); + + mtk_ddp_write_mask(cmdq_pkt, y2r_offset, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx), + OVL_Y2R_PARA_C_CF_YA); + mtk_ddp_write_mask(cmdq_pkt, (y2r_offset << 16), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx), + OVL_Y2R_PARA_C_CF_UA); + mtk_ddp_write_mask(cmdq_pkt, y2r_offset, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_1(idx), + OVL_Y2R_PARA_C_CF_VA); + + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_R0(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_G1(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_B2(idx)); + + mtk_ddp_write_mask(cmdq_pkt, csc_en, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT1, + OVL_CLRFMT_EXT1_CSC_EN(idx)); + } + if (pending->rotation & DRM_MODE_REFLECT_Y) { con |= OVL_CON_VIRT_FLIP; addr += (pending->height - 1) * pending->pitch; From patchwork Tue Dec 12 12:19:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177297 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682182vqy; Tue, 12 Dec 2023 04:21:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVmh28HGOCYgFcKdL5ANwCBPTnvCUFp9PUUZUc4VEj71BMlN+Z/S4Ewj/W/lWdWkb9u8HZ X-Received: by 2002:aa7:8896:0:b0:6ce:6484:c661 with SMTP id z22-20020aa78896000000b006ce6484c661mr3389110pfe.67.1702383668275; Tue, 12 Dec 2023 04:21:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383668; cv=none; d=google.com; s=arc-20160816; b=bPfiegCKFd5z/cIFFpq1U31y3/bRekwJgP0icUnPX6MaMQhLlP3LGUTT0O1kfIGOcD BB04SLtot73T03I1paRfSXSlTvnddC1bofI4/LZ91hyiZUknbfmLVEk9IOIc4LN2wsln IWneN+kIFQ/8zO6fIlXMtXigAQ8m5M4qm/8eOliXjhNxKQlJFmEwmCWpZkgAT2qjNa8H MxTBafgjxen2ga8tpNAIeGyHPx6Y2PJxwGiF9Rb1mogho3Woud6wZpa2vbV7wSg6TIzF Mq+89WoVgrG/b+aPkJvR8xH8yg4rZrVjXyO+jeCgty5lY+SzYuJYf03UDPDWXKMwAKYZ xxFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=MPb3UfJ/F4HQXrrSrfK/t28qw8wKavrHrRjno5lOOAY=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=tdpjnI5TmHOm5axxQaVhx0HyaUhDssv0BeMWFq9+uH+b4p3ZQWa0Ccgi6A5S/CSVpJ 3ctyW5N+6AJU3bkaUeN+0dOLPebnbXskesaDdClRGR3UI55up4OzyKt8J7i4Kbn8xDlD tXOt5Y5AbdmyVt25Y7WYlTs/VhgCYE5J+cNIYMFp5DNs9rQYdQujG42nT5riQpmFoX+L SNaGRnt/qm1BX1qnLytqisRYH9AoIqLX7tQti+nY2+fUeBUlE93cNa23ht0hx8Psgc1f wulafUhAgPx0338jhl5mv0nOyKqy3q6iDtmFW8PEUrLOVmtY9bR8lYmyoAKdbiPr18Vx OeCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=fukKPYDX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id c32-20020a630d20000000b0059b79bf220csi7657224pgl.662.2023.12.12.04.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=fukKPYDX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 13723802139D; Tue, 12 Dec 2023 04:21:05 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232296AbjLLMUu (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232372AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D647DD0; Tue, 12 Dec 2023 04:20:10 -0800 (PST) X-UUID: c677506498e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MPb3UfJ/F4HQXrrSrfK/t28qw8wKavrHrRjno5lOOAY=; b=fukKPYDXe4S3GCZqZAdH/qp4nuM/KzbHZOl+1oyVzqHAM64RWTD2k5BuozY6Yrkl1Js+vzOWivqspwtRdvO2O34TqAFSAYhWRgTMT8owxcwV5YaNe/eTsqKKrpgeSX6dh9Z+arOMPw/dUfYz7pWIVRdlW0W6RPBfOECBmbO+PAo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:d4e42f79-d320-42a9-83f3-eb095eddaa87,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:8ca8b373-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c677506498e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1914280450; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 10/17] drm/mediatek: Support more color formats in OVL Date: Tue, 12 Dec 2023 20:19:50 +0800 Message-ID: <20231212121957.19231-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.858200-8.000000 X-TMASE-MatchedRID: N6Ek0bBNb/E5GkwO9XZv45JAa1C/+FcuEbxKVXd70tXfUZT83lbkEEtH ojrK13E4YW+LSuE6vND+UA6OdqfdiY9oUcx9VMLgFEUknJ/kEl7dB/CxWTRRu+rAZ8KTspSz62l iZc9EiWzgbP91+i7CtRVExQW3pejuw9QMYAEj5Zv1L4LYH+jdFH8WNOUAlF9V1usLfFvCBSaq/z HufHxGjVoL4DB5xh01F0aD5ljt43pMcHZD6gqu7wxMjfifIXfowkvVoA11Twp+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.858200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7E0BD30B751507242B0EAC6B2A6D9844A95C039D2C0DE733BA5CF34BD308532E2000:8 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:21:05 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078657544650655 X-GMAIL-MSGID: 1785078657544650655 Support more color formats in Overlay. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 7e217142d0c4..a3f1630af5df 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -130,12 +130,20 @@ static const u32 mt8173_formats[] = { static const u32 mt8195_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX1010102, DRM_FORMAT_BGRA1010102, DRM_FORMAT_ABGR8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_RGBX1010102, + DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_RGB565, @@ -431,12 +439,16 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, return blend_mode == DRM_MODE_BLEND_COVERAGE ? OVL_CON_CLRFMT_ARGB8888 : OVL_CON_CLRFMT_PARGB8888; + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: return OVL_CON_BYTE_SWAP | (blend_mode == DRM_MODE_BLEND_COVERAGE ? OVL_CON_CLRFMT_ARGB8888 : OVL_CON_CLRFMT_PARGB8888); + case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: @@ -444,6 +456,7 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, return blend_mode == DRM_MODE_BLEND_COVERAGE ? OVL_CON_CLRFMT_RGBA8888 : OVL_CON_CLRFMT_PARGB8888; + case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: @@ -452,6 +465,9 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, (blend_mode == DRM_MODE_BLEND_COVERAGE ? OVL_CON_CLRFMT_RGBA8888 : OVL_CON_CLRFMT_PARGB8888); + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: From patchwork Tue Dec 12 12:19:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7681897vqy; Tue, 12 Dec 2023 04:20:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IH18K1oPjVJJ9zp55ZQKWKyL7iZelMw+4zu9uPzt8tQvK3YXx/qbdFZxC93vdp42+hSdDrO X-Received: by 2002:a05:6359:a19:b0:170:4168:8ba4 with SMTP id el25-20020a0563590a1900b0017041688ba4mr6954789rwb.34.1702383631906; Tue, 12 Dec 2023 04:20:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383631; cv=none; d=google.com; s=arc-20160816; b=Va+nGOLbF26QfbrGV4AlQJNpvSDDKpq+S/u1kbhueN44/drlIN1WExsrVcHuaWpuCO Nlxw34UhWpacpDhukrgZaLh4be/Bf4qE5nfx2MoypCYehT5Ht9LaM6Ld6zBw5DBCpXHb OytwfXQ4FU6HBsGuhTCHQAvMEdkqxaLs2AbEGQd3+mxVKYkJyq9BP+Xn4eoISJ5qsOV7 g7vvSVm99syNpUo+kVKU6oFtuVfMmRkYMfca/8C/URoOdQRTF4TI5n295ZQPnmDWHFVU SmjK+WnIAgpj67VELoK0ACwnb4ibMa+a3JZJG9eWx+/lBOcCMhn2rc1dP03oQzrEf8sx LkIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=4lXtxRLW2YUA4Wg50wpANF7MKGwStkbHF3oDgsbY6kQ=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=l8Wk68GT0OF3BHPTxbJ23S6rDTl9AhULCBE+8lbZHWrXoifPlXZuEcT5qChh6EPa6e GnOCJeFxk6MEx+z1FS+BbpQNwnt02HqPFfByVpjL89CgyCOKRRYRm+rkpElyMbvBdLCG ERy8vDQ0l528unQwgw15HOOoYmUBpLDSzV2I+zJ3fdmT/SVIvPg66rdfF77kses7ku2I C4Sxey4YTf0P1Inn/8ZYFqoHICj8A5R8aDFMQvfypwWUt/BY86O9aB+B1SmIW6RoWxdD tZVn4DMh6apAIT+IKRIZT++P1Vsq3VyLJc1M+imtBCpoIOiFaZ7ApvaznBkUL9NsD3Xg JSiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=eIsTuf9D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id j21-20020a635955000000b005c603f06562si7652594pgm.333.2023.12.12.04.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:20:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=eIsTuf9D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 357E1802139C; Tue, 12 Dec 2023 04:20:28 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346413AbjLLMUI (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232372AbjLLMUG (ORCPT ); Tue, 12 Dec 2023 07:20:06 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3AA3D5; Tue, 12 Dec 2023 04:20:07 -0800 (PST) X-UUID: c66cc80698e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=4lXtxRLW2YUA4Wg50wpANF7MKGwStkbHF3oDgsbY6kQ=; b=eIsTuf9DRXBPrpwn+rN+YYCcQ5KFwuT/XDGvaYAX2E+nWYYTHVq/5ZtfTB6KMGa78/yvBCbFC9gt+19S4NZ3DfJJN65SBDaJhccORouBws5L3ldMEDVMY8lS7DR/0wVgZgcpc15LC9lWgLfXbtK7cRYI1p2P0IKuxtuSGf1FFVw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:c23d5db9-7d0d-42f6-8d8b-5969664cc573,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:0a7d16bd-2ac7-4da2-9f94-677a477649d9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c66cc80698e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2088098696; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:01 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 11/17] drm/mediatek: Turn off the layers with zero width or height Date: Tue, 12 Dec 2023 20:19:51 +0800 Message-ID: <20231212121957.19231-12-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:28 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078618648028679 X-GMAIL-MSGID: 1785078618648028679 We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such situations. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 10d23e76acaa..8789442c039f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -156,7 +156,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 73c9e3da56a7..e95331c06815 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -163,7 +163,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, if (idx >= 4) return; - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); return; } From patchwork Tue Dec 12 12:19:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177301 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682212vqy; Tue, 12 Dec 2023 04:21:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IFuMf0/64OIPw2X3UrAu0IEuUHDd6MX9wg2578wUfEyy0sF4uCPNkchS50G1XbQ83qvMpWO X-Received: by 2002:a05:6a20:2583:b0:190:3fd8:45c1 with SMTP id k3-20020a056a20258300b001903fd845c1mr8461617pzd.0.1702383670203; Tue, 12 Dec 2023 04:21:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383670; cv=none; d=google.com; s=arc-20160816; b=vVROo7b02NkrRBkozLwbW+biw6QDe9ar2jotRIcsZ9X2e4hZWcUTaBgWl+VHG6/Iy9 aiBprTPgwA112w3ICxZWuFimyFOZ8d9lltPgd+0mjAzAsa87n5llGffAJX6MxxRqC3fo 9KFNULPe8o/GXm2qG80eR7tU4rbUni9dslg1jRC/9FfP3yKFtz7JNLZ7imuTNx3VyOvT qZCG28ppWAG9TU9f051XcacMW1nbNzMWoCJ2093Kzs0vFKnRSEA6ffQA2tvHYx7UYdRj 3jUnQfngcZSJPH53TOEAjxOFUoIHIZari97JOcjG4sEsuqNWPPy4Sx6OziLGJ5lkJis1 b+jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jUEzKmTbOzfZxokr6l1oDWohCMnMpyeGAEntpOnJMtE=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=G9UCJtPvvwGB6oGGDWvVDFpXxForEuz8ioCaVIW+yz8a2CxK2Br5ka1pDKzYiG2eiB b9vJsmIk52gv7Sw0rNAegiuQ5ri1bzVp+nkj4GLjUyrZEsAssc9CpDi+2WoyzKYaygiD fylSvywtvQi7+ISDc9Yf2r/uG1Hpa4E/0AgPBsVE7GrmrXbzbPv1zaFtnf1J/3RB5aXy sQpP3sE+HzMVluYXg2iQCxAuwVM8tJ6llEytP1tBsqocPLO7de7RyTxA8HI68bZ4TqUc B5e2Xe7sql7V2zHYf1AUtBUiG4kOpTD/HoWPWVBxVtSH5BWOQ6oVnZcjxqs7V7VhW0Rh SscQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=tpZA42L6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id bq5-20020a056a02044500b005c5e2331ba9si8116395pgb.324.2023.12.12.04.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=tpZA42L6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 0B8AC80A14BE; Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346496AbjLLMU0 (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346470AbjLLMUJ (ORCPT ); Tue, 12 Dec 2023 07:20:09 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D73E7106; Tue, 12 Dec 2023 04:20:14 -0800 (PST) X-UUID: c6cfe9ea98e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jUEzKmTbOzfZxokr6l1oDWohCMnMpyeGAEntpOnJMtE=; b=tpZA42L6JQH2IXx8FNCcy5EtYR/83aqizgOi+ySDGj2yKK+svHhYbv/+EHYGNuINaWaFEL7s5Gh2kc3uACtfMuIWQpDErnofkDcyFvCDEWYtHcRUUY5vRwls6dJafRuK3O83zHn3j8eirse6k7DcOu60aUtu3em7EPJUi5H1QxE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:136af1e5-17ca-4134-9c9f-e0dbb577d74e,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:117d16bd-2ac7-4da2-9f94-677a477649d9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c6cfe9ea98e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 985053357; Tue, 12 Dec 2023 20:20:03 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:02 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 12/17] drm/mediatek: Support CRC in display driver Date: Tue, 12 Dec 2023 20:19:52 +0800 Message-ID: <20231212121957.19231-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.939000-8.000000 X-TMASE-MatchedRID: 0rWiJU0QJZCiwkztVCsqb5JAa1C/+FcunhD9A3Sa7pYs/uUAk6xP7COq qvcT7F2IBEwG50CDfQMYMPaM+DRRbK0ZS7JYIH8qA5rdNgLWPkLoatYL/ATKmPzaSz3Z/4aa5q3 YkgneJmRc9hYWdFWKJD2+qVno7r3yO+xLATovPvoQ9/tMNQ4aipaFO9XLY12U1DNIFLaNMLh1gn ekL1c23iJrUDQ2MZ9qDjZ1VoeiMBNwL3Zf4FPpFiNHByyOpYYCF46YuX32Nn9PThEiFkm5eJOuv 4LVY2bF30ZuzE6YjcTLQze2Z7hVw7bfdDP+zORmR/j040fRFpIUkWvaqUqLH4eUNQK7Qj5cS8FR hpoGD37s1fZuShlORjvuPM/g30AtSMQH4Jcpfxh3sO3zr/a7+CGlZBSK0BYbCyKtPCTkUEI5tOk lY41M4eLzNWBegCW2wgn7iDBesS0nRE+fI6etkmfcfA7Mq1QjkmLjIQEsCtJSl90o6O24vwmP49 dmkWzgd11JCSiws13xF0JitsT3889dWPZBEhtorGasNh2RT5paW0lvuTB0cYCE5xpCtDRTUbJFy h4XXyqYo/TPOlMB4bCh3zE4wqa8DUCRr8oin+k= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.939000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A3F22DF9538766EE6B79EB66650647947E3D3E009921CE7141E2BD41829F1D552000:8 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078659318272467 X-GMAIL-MSGID: 1785078659318272467 Register CRC related function pointers to support CRC retrieval. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 239 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 39 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 + 3 files changed, 281 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index bc4cc75cca18..fad728690db7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -71,6 +71,9 @@ struct mtk_drm_crtc { /* lock for display hardware access */ struct mutex hw_lock; bool config_updating; + + struct mtk_ddp_comp *crc_provider; + unsigned int frames; }; struct mtk_crtc_state { @@ -625,6 +628,14 @@ static void mtk_crtc_ddp_irq(void *data) struct drm_crtc *crtc = data; struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_drm_private *priv = crtc->dev->dev_private; + struct mtk_ddp_comp *comp = mtk_crtc->crc_provider; + + /* + * crc providers should make sure the crc is always correct + * by resetting it in .crc_read() + */ + if (crtc->crc.opened) + comp->funcs->crc_read(comp->dev); #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) @@ -636,6 +647,24 @@ static void mtk_crtc_ddp_irq(void *data) if (!priv->data->shadow_register) mtk_crtc_ddp_config(crtc, NULL); #endif + + /* + * drm_crtc_add_crc_entry() could take more than 50ms to finish + * put it at the end of the isr + */ + if (crtc->crc.opened) { + /* + * skip the first crc because the first frame is configured by + * mtk_crtc_ddp_hw_init() when atomic enable + */ + if (++mtk_crtc->frames > 1) { + drm_crtc_add_crc_entry(crtc, true, + drm_crtc_vblank_count(crtc), + comp->funcs->crc_entry(comp->dev)); + } + } else { + mtk_crtc->frames = 0; + } mtk_drm_finish_page_flip(mtk_crtc); } @@ -736,6 +765,40 @@ static int mtk_drm_crtc_update_output(struct drm_crtc *crtc, return 0; } +static int mtk_drm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src) +{ + if (src && strcmp(src, "auto") != 0) { + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", + __func__, drm_crtc_index(crtc), src); + return -EINVAL; + } + return 0; +} + +static int mtk_drm_crtc_verify_crc_source(struct drm_crtc *crtc, + const char *src, + size_t *cnt) +{ + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); + struct mtk_ddp_comp *comp = mtk_crtc->crc_provider; + + if (!comp) { + DRM_ERROR("%s(crtc-%d): no crc provider\n", + __func__, drm_crtc_index(crtc)); + return -ENOENT; + } + + if (src && strcmp(src, "auto") != 0) { + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", + __func__, drm_crtc_index(crtc), src); + return -EINVAL; + } + + *cnt = comp->funcs->crc_cnt(comp->dev); + + return 0; +} + int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state) { @@ -872,6 +935,8 @@ static const struct drm_crtc_funcs mtk_crtc_funcs = { .atomic_destroy_state = mtk_drm_crtc_destroy_state, .enable_vblank = mtk_drm_crtc_enable_vblank, .disable_vblank = mtk_drm_crtc_disable_vblank, + .set_crc_source = mtk_drm_crtc_set_crc_source, + .verify_crc_source = mtk_drm_crtc_verify_crc_source, }; static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { @@ -1073,6 +1138,11 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, if (comp->funcs->ctm_set) has_ctm = true; + + if (comp->funcs->crc_cnt && + comp->funcs->crc_entry && + comp->funcs->crc_read) + mtk_crtc->crc_provider = comp; } mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, @@ -1152,3 +1222,172 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, #endif return 0; } + +void mtk_drm_crc_init(struct mtk_drm_crc *crc, + const u32 *crc_offset_table, size_t crc_count, + u32 reset_offset, u32 reset_mask) +{ + crc->ofs = crc_offset_table; + crc->cnt = crc_count; + crc->rst_ofs = reset_offset; + crc->rst_msk = reset_mask; + crc->va = kcalloc(crc->cnt, sizeof(*crc->va), GFP_KERNEL); + if (!crc->va) { + DRM_ERROR("failed to allocate memory for crc\n"); + crc->cnt = 0; + } +} + +void mtk_drm_crc_read(struct mtk_drm_crc *crc, void __iomem *reg) +{ + if (!crc->cnt || !crc->ofs || !crc->va) + return; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + /* sync to see the most up-to-date copy of the DMA buffer */ + dma_sync_single_for_cpu(crc->cmdq_client.chan->mbox->dev, + crc->pa, crc->cnt * sizeof(*crc->va), + DMA_FROM_DEVICE); +#else + /* read crc with cpu for the platforms without cmdq */ + { + u32 n; + + for (n = 0; n < crc->cnt; n++) + crc->va[n] = readl(reg + crc->ofs[n]); + + n = readl(reg + crc->rst_ofs); + + /* pull reset bit */ + n |= crc->rst_msk; + writel(n, reg + crc->rst_ofs); + + /* release reset bit */ + n &= ~crc->rst_msk; + writel(n, reg + crc->rst_ofs); + } +#endif +} + +void mtk_drm_crc_destroy(struct mtk_drm_crc *crc) +{ + if (!crc->cnt) + return; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (crc->pa) { + dma_unmap_single(crc->cmdq_client.chan->mbox->dev, + crc->pa, crc->cnt * sizeof(*crc->va), + DMA_TO_DEVICE); + crc->pa = 0; + } + if (crc->cmdq_client.chan) { + mtk_drm_cmdq_pkt_destroy(&crc->cmdq_handle); + mbox_free_channel(crc->cmdq_client.chan); + crc->cmdq_client.chan = NULL; + } +#endif + kfree(crc->va); + crc->va = NULL; + crc->cnt = 0; +} + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +void mtk_drm_crc_cmdq_create(struct device *dev, struct mtk_drm_crc *crc) +{ + int i; + + if (!crc->cnt) { + dev_warn(dev, "%s: not support\n", __func__); + goto cleanup; + } + + if (!crc->ofs) { + dev_warn(dev, "%s: not defined\n", __func__); + goto cleanup; + } + + crc->cmdq_client.client.dev = dev; + crc->cmdq_client.client.tx_block = false; + crc->cmdq_client.client.knows_txdone = true; + crc->cmdq_client.client.rx_callback = NULL; + crc->cmdq_client.chan = mbox_request_channel(&crc->cmdq_client.client, 0); + if (IS_ERR(crc->cmdq_client.chan)) { + dev_warn(dev, "%s: failed to create mailbox client\n", __func__); + crc->cmdq_client.chan = NULL; + goto cleanup; + } + + if (mtk_drm_cmdq_pkt_create(&crc->cmdq_client, &crc->cmdq_handle, PAGE_SIZE)) { + dev_warn(dev, "%s: failed to create cmdq packet\n", __func__); + goto cleanup; + } + + if (!crc->va) { + dev_warn(dev, "%s: no memory\n", __func__); + goto cleanup; + } + + /* map the entry to get a dma address for cmdq to store the crc */ + crc->pa = dma_map_single(crc->cmdq_client.chan->mbox->dev, + crc->va, crc->cnt * sizeof(*crc->va), + DMA_FROM_DEVICE); + + if (dma_mapping_error(crc->cmdq_client.chan->mbox->dev, crc->pa)) { + dev_err(dev, "%s: failed to map dma\n", __func__); + goto cleanup; + } + + if (crc->cmdq_event) + cmdq_pkt_wfe(&crc->cmdq_handle, crc->cmdq_event, true); + + for (i = 0; i < crc->cnt; i++) { + /* put crc to spr1 register */ + cmdq_pkt_read_s(&crc->cmdq_handle, crc->cmdq_reg->subsys, + crc->cmdq_reg->offset + crc->ofs[i], + CMDQ_THR_SPR_IDX1); + + /* copy spr1 register to physical address of the crc */ + cmdq_pkt_assign(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_HIGH(crc->pa + i * sizeof(*crc->va))); + cmdq_pkt_write_s(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(crc->pa + i * sizeof(*crc->va)), + CMDQ_THR_SPR_IDX1); + } + /* reset crc */ + mtk_ddp_write_mask(&crc->cmdq_handle, ~0, crc->cmdq_reg, 0, + crc->rst_ofs, crc->rst_msk); + + /* clear reset bit */ + mtk_ddp_write_mask(&crc->cmdq_handle, 0, crc->cmdq_reg, 0, + crc->rst_ofs, crc->rst_msk); + + /* jump to head of the cmdq packet */ + cmdq_pkt_jump(&crc->cmdq_handle, crc->cmdq_handle.pa_base); + + return; +cleanup: + mtk_drm_crc_destroy(crc); +} + +void mtk_drm_crc_cmdq_start(struct mtk_drm_crc *crc) +{ + if (!crc->cmdq_client.chan) + return; + + dma_sync_single_for_device(crc->cmdq_client.chan->mbox->dev, + crc->cmdq_handle.pa_base, + crc->cmdq_handle.cmd_buf_size, + DMA_TO_DEVICE); + mbox_send_message(crc->cmdq_client.chan, &crc->cmdq_handle); + mbox_client_txdone(crc->cmdq_client.chan, 0); +} + +void mtk_drm_crc_cmdq_stop(struct mtk_drm_crc *crc) +{ + if (!crc->cmdq_client.chan) + return; + + mbox_flush(crc->cmdq_client.chan, 2000); +} +#endif diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index 96790f8f7a94..3440c154ad1e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -15,6 +15,45 @@ #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 +/** + * struct mtk_drm_crc - crc related information + * @ofs: register offset of crc + * @rst_ofs: register offset of crc reset + * @rst_msk: register mask of crc reset + * @cnt: count of crc + * @va: pointer to the start of crc array + * @pa: physical address of the crc for gce to access + * @cmdq_event: the event to trigger the cmdq + * @cmdq_reg: address of the register that cmdq is going to access + * @cmdq_client: handler to control cmdq (mbox channel, thread ...etc.) + * @cmdq_handle: cmdq packet to store the commands + */ +struct mtk_drm_crc { + const u32 *ofs; + u32 rst_ofs; + u32 rst_msk; + size_t cnt; + u32 *va; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + dma_addr_t pa; + u32 cmdq_event; + struct cmdq_client_reg *cmdq_reg; + struct cmdq_client cmdq_client; + struct cmdq_pkt cmdq_handle; +#endif +}; + +void mtk_drm_crc_init(struct mtk_drm_crc *crc, + const u32 *crc_offset_table, size_t crc_count, + u32 reset_offset, u32 reset_mask); +void mtk_drm_crc_read(struct mtk_drm_crc *crc, void __iomem *reg); +void mtk_drm_crc_destroy(struct mtk_drm_crc *crc); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +void mtk_drm_crc_cmdq_create(struct device *dev, struct mtk_drm_crc *crc); +void mtk_drm_crc_cmdq_start(struct mtk_drm_crc *crc); +void mtk_drm_crc_cmdq_stop(struct mtk_drm_crc *crc); +#endif + void mtk_drm_crtc_commit(struct drm_crtc *crtc); int mtk_drm_crtc_create(struct drm_device *drm_dev, const unsigned int *path, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2597dd7ac0d2..38d08796fae4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -84,6 +84,9 @@ struct mtk_ddp_comp_funcs { void (*add)(struct device *dev, struct mtk_mutex *mutex); void (*remove)(struct device *dev, struct mtk_mutex *mutex); int (*encoder_index)(struct device *dev); + size_t (*crc_cnt)(struct device *dev); + u32 *(*crc_entry)(struct device *dev); + void (*crc_read)(struct device *dev); }; struct mtk_ddp_comp { From patchwork Tue Dec 12 12:19:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177304 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682272vqy; Tue, 12 Dec 2023 04:21:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IG9lJ9moPQas29Rz0qu6Fg/+r28MwT2y/dGYXcd0heKJhQ97gyFwj9oI5ODuvau9erqkQWN X-Received: by 2002:a05:6a00:b4d:b0:6cb:b7b7:c04c with SMTP id p13-20020a056a000b4d00b006cbb7b7c04cmr3146558pfo.12.1702383675631; Tue, 12 Dec 2023 04:21:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383675; cv=none; d=google.com; s=arc-20160816; b=GExRmwfwOz+N0AtpSSAdZKss7ECpNipabje5uU5/V3Lsfeg0/FwgQH96DfI7tkK/4S 4u0BsIXTUtJ9d/8xY+6lvmo5Q+jy9If3gk3mDjtntDw7amswmxe6azhqY28dfrdo/nwr K2oI4R0MpqIj9WRONJUXOw+Ji7fINiTWdcX5H4j5qd+a6Py0cNLH5M+RpHVV+p7hTquz FsyWxabHfUrnNVtTW2A2lAiPgcodmTXo9uhBm9uRJfCQCrA803pT43HqH1PTRvvxsF1r Ip+jT0VHcOewUvAkrTuV/NlcH8yadjgbaSZwDwdmzsPf71CIB4YuLlokb8231cEHn6s7 opBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=wACZeC0fJfmXvigLU68UKadLKrfAY6i7TfCwkPACsEQ=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=FPlo3UZPjt85myYRXP17aq2qFkf/i6Zf4JWy/euyOxPS3WhlxvtENhzAPOK8KxACyH 5EIY6BagCHZCPeeqrJD6tySwZ6SLYmHozFPOAnPK4fJ6QrX752lBxi+9tRQSF42c1hdL SoJ3tAj4FfR4gRVmgPrp6NZ1S6CiNZL/nkipm81AowCo0JRXdEal4B7w4FaKl5u5GLee f7DA49Bm37IJpcrel9iTnrD7u3GPBKQl6WI114nMHVLGyVnUrkyv6rPuECWpy+4NYNjR khGj7COJEbyZMZGeZj68ENK5JjN+yo1u8XYwUzuDg0qOBlT6piS2LUWHH7a6uTT+Oq8T qCww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=W0hhkrU0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id j12-20020a056a00234c00b006cec9b3fd91si7831047pfj.98.2023.12.12.04.21.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=W0hhkrU0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 4A71A80B1E4B; Tue, 12 Dec 2023 04:20:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346413AbjLLMUb (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346471AbjLLMUK (ORCPT ); Tue, 12 Dec 2023 07:20:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F87D109; Tue, 12 Dec 2023 04:20:14 -0800 (PST) X-UUID: c6c2e13298e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wACZeC0fJfmXvigLU68UKadLKrfAY6i7TfCwkPACsEQ=; b=W0hhkrU0N8e8L5hXB8ujEpY4WO+YeScEy79OprHKq8Z5n5tP/cs+rCt1P8Rimv0zuizk/b+oRPZCwpRR1pevasb/kent50fB8CPYnNPsAELKtTergmJcifFy3mmonMByzBdTPtB32Ydt4kOmk0QqW4Do830pKAgrLjy/xqcAckU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:92925212-fdd2-4992-8e2d-062e6d48af72,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:a7a8b373-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: c6c2e13298e811eeba30773df0976c77-20231212 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 858016398; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:02 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 13/17] drm/mediatek: Support CRC in OVL Date: Tue, 12 Dec 2023 20:19:53 +0800 Message-ID: <20231212121957.19231-14-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078665304089681 X-GMAIL-MSGID: 1785078665304089681 We choose OVL as the CRC generator from other hardware components that are also capable of calculating CRCs, since its frame done event triggers vblanks, it can be used as a signal to know when is safe to retrieve CRC of the frame. Please note that position of the hardware component that is chosen as CRC generator in the display path is significant. For example, while OVL is the first module in VDOSYS0, its CRC won't be affected by the modules after it, which means effects applied by PQ, Gamma, Dither or any other components after OVL won't be calculated in CRC generation. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 85 +++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 + 3 files changed, 85 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index c44f5b31bab5..08cc2d2fef9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -102,6 +102,9 @@ void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); +size_t mtk_ovl_crc_cnt(struct device *dev); +u32 *mtk_ovl_crc_entry(struct device *dev); +void mtk_ovl_crc_read(struct device *dev); void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex); void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index a3f1630af5df..78749dabeb43 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -25,6 +25,13 @@ #define OVL_FME_CPL_INT BIT(1) #define DISP_REG_OVL_INTSTA 0x0008 #define DISP_REG_OVL_EN 0x000c +#define OVL_EN BIT(0) +#define OVL_OP_8BIT_MODE BIT(4) +#define OVL_HG_FOVL_CK_ON BIT(8) +#define OVL_HF_FOVL_CK_ON BIT(10) +#define DISP_REG_OVL_TRIG 0x0010 +#define OVL_CRC_EN BIT(8) +#define OVL_CRC_CLR BIT(9) #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 @@ -44,6 +51,8 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CRC 0x0270 +#define OVL_CRC_OUT_MASK GENMASK(30, 0) #define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_CLRFMT_EXT1 0x02D8 #define OVL_CLRFMT_EXT1_CSC_EN(n) (1 << (((n) * 4) + 1)) @@ -151,6 +160,10 @@ static const u32 mt8195_formats[] = { DRM_FORMAT_YUYV, }; +static const u32 mt8195_ovl_crc_ofs[] = { + DISP_REG_OVL_CRC, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -161,12 +174,15 @@ struct mtk_disp_ovl_data { const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; + const u32 *crc_ofs; + size_t crc_cnt; }; /* * struct mtk_disp_ovl - DISP_OVL driver structure * @crtc: associated crtc to report vblank events to * @data: platform data + * @crc: crc related information */ struct mtk_disp_ovl { struct drm_crtc *crtc; @@ -176,8 +192,30 @@ struct mtk_disp_ovl { const struct mtk_disp_ovl_data *data; void (*vblank_cb)(void *data); void *vblank_cb_data; + struct mtk_drm_crc crc; }; +size_t mtk_ovl_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->crc.cnt; +} + +u32 *mtk_ovl_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->crc.va; +} + +void mtk_ovl_crc_read(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + mtk_drm_crc_read(&ovl->crc, ovl->regs); +} + static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv = dev_id; @@ -269,15 +307,28 @@ void mtk_ovl_start(struct device *dev) * (should always be enabled) */ reg |= OVL_OUTPUT_CLAMP; - writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); - writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); + + reg = OVL_EN; + if (ovl->data->crc_cnt) { + /* enable crc and its related clocks */ + writel_relaxed(OVL_CRC_EN, ovl->regs + DISP_REG_OVL_TRIG); + reg |= OVL_OP_8BIT_MODE | OVL_HG_FOVL_CK_ON | OVL_HF_FOVL_CK_ON; + } + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_EN); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_start(&ovl->crc); +#endif } void mtk_ovl_stop(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_stop(&ovl->crc); +#endif writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); if (ovl->data->smi_id_en) { unsigned int reg; @@ -695,15 +746,31 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) dev_err(dev, "failed to ioremap ovl\n"); return PTR_ERR(priv->regs); } + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + if (priv->data->crc_cnt) { + mtk_drm_crc_init(&priv->crc, + priv->data->crc_ofs, priv->data->crc_cnt, + DISP_REG_OVL_TRIG, OVL_CRC_CLR); + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); -#endif - - priv->data = of_device_get_match_data(dev); - platform_set_drvdata(pdev, priv); + if (priv->data->crc_cnt) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", 0, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg = &priv->cmdq_reg; + mtk_drm_crc_cmdq_create(dev, &priv->crc); + } +#endif ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, IRQF_TRIGGER_NONE, dev_name(dev), priv); if (ret < 0) { @@ -724,6 +791,10 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) static void mtk_disp_ovl_remove(struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + mtk_drm_crc_destroy(&ovl->crc); component_del(&pdev->dev, &mtk_disp_ovl_component_ops); pm_runtime_disable(&pdev->dev); } @@ -794,6 +865,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .formats = mt8195_formats, .num_formats = ARRAY_SIZE(mt8195_formats), .supports_clrfmt_ext = true, + .crc_ofs = mt8195_ovl_crc_ofs, + .crc_cnt = ARRAY_SIZE(mt8195_ovl_crc_ofs), }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 9940909c7435..1118efcde98a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -349,6 +349,9 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .clk_enable = mtk_ovl_clk_enable, .clk_disable = mtk_ovl_clk_disable, .config = mtk_ovl_config, + .crc_cnt = mtk_ovl_crc_cnt, + .crc_entry = mtk_ovl_crc_entry, + .crc_read = mtk_ovl_crc_read, .start = mtk_ovl_start, .stop = mtk_ovl_stop, .register_vblank_cb = mtk_ovl_register_vblank_cb, From patchwork Tue Dec 12 12:19:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177293 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7681984vqy; Tue, 12 Dec 2023 04:20:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IFWteIhsURJ5c1sLih2Gr8YVfg8X7WJp7V0Qv6fMNXiop/KBhuRuxiBx9AiRh36BgT6XkqM X-Received: by 2002:a92:cd8d:0:b0:35d:6281:517 with SMTP id r13-20020a92cd8d000000b0035d62810517mr8916347ilb.11.1702383644237; Tue, 12 Dec 2023 04:20:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383644; cv=none; d=google.com; s=arc-20160816; b=UiZLJ1RUvsUVX79HZA5F54DdEKS4kh8gqy9ynU6+hOBkWG2Ba7PKbXildFUIPaWbDz 8mvKVoxtfYkUX+ZSiU4FnF+cPHMGEYlwQnEfBkYpVrN7mfQoX64W5hiwLeKtkEaCvbF3 ZgGxD2uZG9rBInCjj3JDkfJUhgzAXb4JMHw4R4r/loIgKnwBLLnUP6XDBuR04gZ0PIvi KQ1OgV/QIFZo2+3dOUmsmmmSx7jnOmty/Gh5lIkc6B7CFwzl+i9DACzM3DhMirHOc1J8 knzAWZYrCBuvD+KMxnRoQR6uQrst6k8SWYHBt8SMyEC+dyWNCo7hP7qhF2tTc7AlTQgz aWag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=KIx5/HI4HAsZhhvbPfbiM+jroIK7c4B0KZSaWT0axyw=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=gT5vIyTd+dJjkhfw2d+OQiCTY8VVMzm91NZrVCMlt+HC5QRlgQGyKfhFeyBaaKQGiV Zexxw9O47J5NU8JqUCEjAPMOtSptLQS9iFOPE6UbqcZyWgX8wl51Rcaz4Z7iAtWucSLy +YXxaF7sMIz4P9+wV1hBPf9PP+hsTKZ39n8TND0vJEfgwwSN6Lpw6vxDHZjbUmbzsBJV kfj3x39qeNUDdRNGwJEB9fClFTl/Bg586kapJo2YByyd4xM+inYpPE5sJrfRor9Xn8j/ efRTJxv+9YxcQT0af12HNpFXizo8aJNWBlQuDQf+PRWtNjL2eSFCS2kzNT6VDgBYrIjn Maug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=q5lLvcQj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id i3-20020a635403000000b005c1b5a2be77si7346094pgb.702.2023.12.12.04.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:20:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=q5lLvcQj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 8E15F8021398; Tue, 12 Dec 2023 04:20:39 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346502AbjLLMUR (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346425AbjLLMUI (ORCPT ); Tue, 12 Dec 2023 07:20:08 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5DBAFF; Tue, 12 Dec 2023 04:20:13 -0800 (PST) X-UUID: c735aa1498e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KIx5/HI4HAsZhhvbPfbiM+jroIK7c4B0KZSaWT0axyw=; b=q5lLvcQj5Gh7gcLeGON+THEQyHQXSRoVEeH/EcXp2w5BPVDDI4SzsMZ8vbSrIuy2kDRehZ1o3Xb2pHxtKhpyfuxs+Bx5+a82UxIW0S9WDsuEmT/NU1VeuJ6wsYvXMgEa0ePV1uWfJHCJiYYwuhLKtO8cfJ/fi+KpDOdNHZhSeQc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:ad5c7b7a-a89b-4749-9144-6e08d0b0246d,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:8da8b373-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: c735aa1498e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 349522150; Tue, 12 Dec 2023 20:20:03 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:02 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 14/17] drm/mediatek: Support CRC in OVL adaptor Date: Tue, 12 Dec 2023 20:19:54 +0800 Message-ID: <20231212121957.19231-15-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:39 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078632549823104 X-GMAIL-MSGID: 1785078632549823104 We choose Mixer as CRC generator in OVL adaptor since its frame done event will trigger vblanks, we can know when is safe to retrieve CRC of the frame. In OVL adaptor, there's no image procession after Mixer, unlike the OVL in VDOSYS0, Mixer's CRC will include all the effects that are applied to the frame. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 21 +++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 + drivers/gpu/drm/mediatek/mtk_ethdr.c | 62 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 5 ++ 5 files changed, 94 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 08cc2d2fef9f..4d6e8b667bc3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -133,6 +133,9 @@ unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev); const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev); +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev); +void mtk_ovl_adaptor_crc_read(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 8789442c039f..4398db9a6276 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -205,6 +205,27 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); } +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + return mtk_ethdr_crc_cnt(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + return mtk_ethdr_crc_entry(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +void mtk_ovl_adaptor_crc_read(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + mtk_ethdr_crc_read(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 1118efcde98a..ffa4868b1222 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -404,6 +404,9 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = { .clk_enable = mtk_ovl_adaptor_clk_enable, .clk_disable = mtk_ovl_adaptor_clk_disable, .config = mtk_ovl_adaptor_config, + .crc_cnt = mtk_ovl_adaptor_crc_cnt, + .crc_entry = mtk_ovl_adaptor_crc_entry, + .crc_read = mtk_ovl_adaptor_crc_read, .start = mtk_ovl_adaptor_start, .stop = mtk_ovl_adaptor_stop, .layer_nr = mtk_ovl_adaptor_layer_nr, diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index e95331c06815..30eb2c3d95c0 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -24,6 +24,9 @@ #define MIX_FME_CPL_INTEN BIT(1) #define MIX_INTSTA 0x8 #define MIX_EN 0xc +#define MIX_TRIG 0x10 +#define MIX_TRIG_CRC_EN BIT(8) +#define MIX_TRIG_CRC_RST BIT(9) #define MIX_RST 0x14 #define MIX_ROI_SIZE 0x18 #define MIX_DATAPATH_CON 0x1c @@ -39,6 +42,11 @@ #define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) + +/* CRC register offsets for odd and even lines */ +#define MIX_CRC_ODD 0x110 +#define MIX_CRC_EVEN 0x114 + #define MIX_FUNC_DCM0 0x120 #define MIX_FUNC_DCM1 0x124 #define MIX_FUNC_DCM_ENABLE 0xffffffff @@ -82,6 +90,7 @@ struct mtk_ethdr { void *vblank_cb_data; int irq; struct reset_control *reset_ctl; + struct mtk_drm_crc crc; }; static const char * const ethdr_clk_str[] = { @@ -100,6 +109,32 @@ static const char * const ethdr_clk_str[] = { "vdo_be_async", }; +static const u32 ethdr_crc_ofs[] = { + MIX_CRC_ODD, + MIX_CRC_EVEN, +}; + +size_t mtk_ethdr_crc_cnt(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + return priv->crc.cnt; +} + +u32 *mtk_ethdr_crc_entry(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + return priv->crc.va; +} + +void mtk_ethdr_crc_read(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + mtk_drm_crc_read(&priv->crc, priv->ethdr_comp[ETHDR_MIXER].regs); +} + void mtk_ethdr_register_vblank_cb(struct device *dev, void (*vblank_cb)(void *), void *vblank_cb_data) @@ -256,6 +291,13 @@ void mtk_ethdr_start(struct device *dev) struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; writel(1, mixer->regs + MIX_EN); + + if (priv->crc.cnt) { + writel(MIX_TRIG_CRC_EN, mixer->regs + MIX_TRIG); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_start(&priv->crc); +#endif + } } void mtk_ethdr_stop(struct device *dev) @@ -263,6 +305,9 @@ void mtk_ethdr_stop(struct device *dev) struct mtk_ethdr *priv = dev_get_drvdata(dev); struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_drm_crc_cmdq_stop(&priv->crc); +#endif writel(0, mixer->regs + MIX_EN); writel(1, mixer->regs + MIX_RST); reset_control_reset(priv->reset_ctl); @@ -317,6 +362,10 @@ static int mtk_ethdr_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + mtk_drm_crc_init(&priv->crc, + ethdr_crc_ofs, ARRAY_SIZE(ethdr_crc_ofs), + MIX_TRIG, MIX_TRIG_CRC_RST); + for (i = 0; i < ETHDR_ID_MAX; i++) { priv->ethdr_comp[i].dev = dev; priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i); @@ -325,6 +374,16 @@ static int mtk_ethdr_probe(struct platform_device *pdev) &priv->ethdr_comp[i].cmdq_base, i); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); + + if (i == ETHDR_MIXER) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", i, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg = &priv->ethdr_comp[i].cmdq_base; + mtk_drm_crc_cmdq_create(dev, &priv->crc); + } #endif dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i); } @@ -365,6 +424,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev) static int mtk_ethdr_remove(struct platform_device *pdev) { + struct mtk_ethdr *priv = dev_get_drvdata(&pdev->dev); + + mtk_drm_crc_destroy(&priv->crc); component_del(&pdev->dev, &mtk_ethdr_component_ops); return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h index 81af9edea3f7..d17d7256bd12 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.h +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -22,4 +22,9 @@ void mtk_ethdr_register_vblank_cb(struct device *dev, void mtk_ethdr_unregister_vblank_cb(struct device *dev); void mtk_ethdr_enable_vblank(struct device *dev); void mtk_ethdr_disable_vblank(struct device *dev); + +size_t mtk_ethdr_crc_cnt(struct device *dev); +u32 *mtk_ethdr_crc_entry(struct device *dev); +void mtk_ethdr_crc_read(struct device *dev); + #endif From patchwork Tue Dec 12 12:19:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177300 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682229vqy; Tue, 12 Dec 2023 04:21:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IHTbmY00LeCXn7frZLgqNnpHfMVZq/a6DbYO/CCiXLMPyKI95WivdLjiV2uzmExAkQHZTC7 X-Received: by 2002:a6b:6517:0:b0:7b4:2d71:fe41 with SMTP id z23-20020a6b6517000000b007b42d71fe41mr7621369iob.27.1702383671460; Tue, 12 Dec 2023 04:21:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383671; cv=none; d=google.com; s=arc-20160816; b=No501t60KS6S8rEp4kttj6V/3lJVDRzE0d7eFPkK/el1D+jq7u+eEd5CQqENwmQ7vx kZoLijQtdyYewMKhldV4zTpHmfqKmHHpA/e/NwvaEsP3aBTvOqW/bgL+EPhm2E9Egf5u 2tT5/eIEVKoDDqKwHsJAMotE7bgTvJ4+TL9yf7JFvn0PkencGwfjWPINGYnsNUI+bNaN /NzIsmE9SsZccanZDKUwnACVDyAiRdWkSupE/u1YuvLy2TJ6Bn5odSA7bQlaShr68UQ3 bAwqjSd5e2wtQBO/JK0o/CTbCZKX+PwGfdvbC2CsKVLhFedaOViLVQVt+jMoHfj06QMq iJeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=JBMkZAIFf288hoKMwUlhm1D9YhcT5t9X6lxWz2ykYQo=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=VkqazpDDoz5WLc8qxGKJWAQ85hijHSOiUHdfIZggtapC3RW0me53NxEJTYpohG6vCM FwGXrVn2wPPpZXfkrVZOEztGYBd3reVTmjeIiw7QNzmBYP8G7dGRAwg2O5G3X7ryVU1g bmjoDQw81oVgNR4jCPYgWBdFq1/HWkFTDxcgGMGX9DMRL69w9nrpvP41jfjDmR88unBk fGS/MH7eTh8kgiJ7QKOW0sk5NVZvJrIHQLlFjNB5iOKemSSfPaHC0jB1VpKZ3wjtM2UK d8iGv9r/0WnxEkT6/MmWlC6372Dai2h3SC4V0gwa0mSeNaMqZhtlKOAv2J8KK8kRWDf6 /PoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=UzUl9hR0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id ks1-20020a056a004b8100b006cef628dd82si5305205pfb.289.2023.12.12.04.21.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=UzUl9hR0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 6E335807930B; Tue, 12 Dec 2023 04:21:00 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346633AbjLLMUo (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346482AbjLLMUL (ORCPT ); Tue, 12 Dec 2023 07:20:11 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73A97F7; Tue, 12 Dec 2023 04:20:12 -0800 (PST) X-UUID: c744a5fa98e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JBMkZAIFf288hoKMwUlhm1D9YhcT5t9X6lxWz2ykYQo=; b=UzUl9hR0Gk5JVblb2NWQBhlv0OBaa/bMr0xd/4u3RxGuV+llzWpfH4J1A6Z4hHX4nNN5TjjqCWHymQiBZu4DpCCdWREtSMLWYYBtDw3D+9ZQq+56rWr2wAZW3SxyjZr+mHwAyKPPZ7aWl59hO8Zp1uFoYB7sjvKPLmDeC/W2u2Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:528ed13f-757d-4db0-acbd-7fe6e1402a38,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:4d3b1c61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: c744a5fa98e811eeba30773df0976c77-20231212 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 422742863; Tue, 12 Dec 2023 20:20:03 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:02 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 15/17] drm/mediatek: Add missing plane settings when async update Date: Tue, 12 Dec 2023 20:19:55 +0800 Message-ID: <20231212121957.19231-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:21:00 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078660561255151 X-GMAIL-MSGID: 1785078660561255151 Fix an issue that plane coordinate was not saved when calling async update. Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic update") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index dfd81172a940..ff300426b590 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -232,6 +232,8 @@ static void mtk_plane_atomic_async_update(struct drm_plane *plane, plane->state->src_y = new_state->src_y; plane->state->src_h = new_state->src_h; plane->state->src_w = new_state->src_w; + plane->state->dst.x1 = new_state->dst.x1; + plane->state->dst.y1 = new_state->dst.y1; mtk_plane_update_new_state(new_state, new_plane_state); swap(plane->state->fb, new_state->fb); From patchwork Tue Dec 12 12:19:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177308 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682510vqy; Tue, 12 Dec 2023 04:21:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IG5Ibz9xNKA3BJzLDkjsl63Dxr2zGKzJ2zKq9UBfASKd2e6AaJDUoEeK56AnjKU99u8yC3E X-Received: by 2002:a05:6e02:1a2d:b0:35d:579e:dbf0 with SMTP id g13-20020a056e021a2d00b0035d579edbf0mr6507696ile.15.1702383704849; Tue, 12 Dec 2023 04:21:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383704; cv=none; d=google.com; s=arc-20160816; b=dAH8brwXtPlU547Yknx2phdfkrMfFQLMtL6Vtrh1pIfnqqoEDqrVIS5FULlrfSYqjB a4nJDvs9BoBNeZ0ywZP/Q6zFnJXdWFfK7G8az/wFyVaSvl+72Bx6LooFaXmJpYeqTEGT ESxuAqNYEpIZpDhtD9nK5zHTEP37JwYQDrZz6oCwTuz9QIY6tBVfwwQxfMyo/JLqBmIo c+yfPTa8yRoCm/ufJUizhwT02s9Q1yzoQbdUvFumkgC3twJfJAlWoONo9yrfneZNm9yr GVtyVCixeUwPUJtkXAcJIaaMhWRjbBPiOsRinPWtfC1Bdm2+hRwUBDZNRT6Dbz726p4w 6hAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=IAFUH+3gSqbAwKcAHXzJYY6xSL7PZ4g2dbK5i8/Gisk=; fh=9gBY3LVbdxTioLa7O2pOsMOkTMxlNAxxvKin9b2wF1U=; b=hHSJuJuCRZfhGXU2t1cQl6mXo2igQR1uTtWvK8iKw+OwCmnXhev/69kj0+CdhPglRf VzS/nm7ADVqdFdstpuqm9+HEjI715cTyRvB3n7KBU9QVYuRD5dGM1Ht5jFTTDKdeyIA6 QKgoAq38cT01Qclw+xu26rhPf0Gk8y9fPbVsxO3ryUD57EKdmfkmqN7LsIUpXyVjX5IX wgWcFQtccP6xzdn0GpOZ0ZPI3ZRalbOtC/eLGj1ypnJR0yNueVjuja/MS1bNg/PLZ5wN TsyywBoX4U6ixOeS/lRph09nbxIb8XDltpSIordOni4YEIbDY3lTwOWTbwZqJqc28LOh 7zZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=egry8NBq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id i7-20020a63e907000000b005897813624fsi7497680pgh.476.2023.12.12.04.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=egry8NBq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 2EFD6808E676; Tue, 12 Dec 2023 04:21:09 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346523AbjLLMUV (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346433AbjLLMUI (ORCPT ); Tue, 12 Dec 2023 07:20:08 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2EAA100; Tue, 12 Dec 2023 04:20:13 -0800 (PST) X-UUID: c769729098e811eea5db2bebc7c28f94-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IAFUH+3gSqbAwKcAHXzJYY6xSL7PZ4g2dbK5i8/Gisk=; b=egry8NBqoq/JdsPporF0mSAiIRklAfLVWEuNlUVZf8Y7+LOBzksKkdoW7IejUIJITvOedY7/U60S0wmAoFwNgCw3mqnU8iWsWZmOuSsiF0+PQFjRPGbmtb/FkXJRTt6E1EFqub6eEMEp7b9jv6SK2OaQ7JXSPHs3VO/PZFxilpE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:c5c9e319-8802-46be-9fcc-f5f9f09ed292,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5d391d7,CLOUDID:26fd94fd-4a48-46e2-b946-12f04f20af8c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c769729098e811eea5db2bebc7c28f94-20231212 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 408150858; Tue, 12 Dec 2023 20:20:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:02 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , Hsiao Chien Sung Subject: [PATCH v4 16/17] drm/mediatek: Fix errors when reporting rotation capability Date: Tue, 12 Dec 2023 20:19:56 +0800 Message-ID: <20231212121957.19231-17-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:21:09 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078695739138510 X-GMAIL-MSGID: 1785078695739138510 Create rotation property according to the hardware capability. Since currently OVL of all chips support same rotation, no need to define it in the driver data. Fixes: 84d805753983 ("drm/mediatek: Support reflect-y plane rotation") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++------------ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 9 +++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 +- 5 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 4d6e8b667bc3..c5afeb7c5527 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -127,6 +127,7 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device *dev, void (*vblank_cb)(vo void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev); void mtk_ovl_adaptor_enable_vblank(struct device *dev); void mtk_ovl_adaptor_disable_vblank(struct device *dev); +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev); void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 78749dabeb43..f019737078f6 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -399,6 +399,10 @@ unsigned int mtk_ovl_layer_nr(struct device *dev) unsigned int mtk_ovl_supported_rotations(struct device *dev) { + /* + * although currently OVL can only do reflection, + * reflect x + reflect y = rotate 180 + */ return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } @@ -407,27 +411,17 @@ int mtk_ovl_layer_check(struct device *dev, unsigned int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state = &mtk_state->base; - unsigned int rotation = 0; - rotation = drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &= ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) != 0) + if (state->rotation & ~mtk_ovl_supported_rotations(dev)) return -EINVAL; /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. */ - if (state->fb->format->is_yuv && rotation != 0) + if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; - state->rotation = rotation; - return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 4398db9a6276..273c79d37bef 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -383,6 +383,15 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device *dev, void (*vblank_cb)(vo vblank_cb, vblank_cb_data); } +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev) +{ + /* + * should still return DRM_MODE_ROTATE_0 if rotation is not supported, + * or IGT will fail. + */ + return DRM_MODE_ROTATE_0; +} + void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ffa4868b1222..206dd6f6f99e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -422,6 +422,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = { .remove = mtk_ovl_adaptor_remove_comp, .get_formats = mtk_ovl_adaptor_get_formats, .get_num_formats = mtk_ovl_adaptor_get_num_formats, + .supported_rotations = mtk_ovl_adaptor_supported_rotations, }; static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index ff300426b590..e73b9793dee2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -343,7 +343,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, return err; } - if (supported_rotations & ~DRM_MODE_ROTATE_0) { + if (supported_rotations) { err = drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, supported_rotations); From patchwork Tue Dec 12 12:19:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 177303 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7682260vqy; Tue, 12 Dec 2023 04:21:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IFs7xCwYI4jWFH3Lkzm2MKm0nWy3UJlDgK4gkxeopNoDRvg3+kelcpW775aHSTiq4dyIBDJ X-Received: by 2002:a17:902:ab84:b0:1d0:c445:801b with SMTP id f4-20020a170902ab8400b001d0c445801bmr2588434plr.71.1702383674031; Tue, 12 Dec 2023 04:21:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702383674; cv=none; d=google.com; s=arc-20160816; b=MqM82e3qmDk1ZVVYXmQGgl0b7TG0r2QRSbv7W3gQO1ptTifNeFB6SAeJybVYbMHw3x KKCR7AFRmsrWYB5W/DHAfStWuMpFB5tkQ39hVutaHalVEVWHDaxvkNuscm6ya0R9zmFN uUj1JtDo5oMR43Byo/fgCF0JipS5I5dUJ8fd/ZaWG4pD9b9Ah99Ese23qMr7m+/OfqJn MM5m+QI3IZcrFo4Sz1VB/awvHTYMNqNN3mo7ch2+x3dgrtyd9FH7uNUaNpXAZCIcC5Pk IoiLQ3gbVVQ9NjaO4v5LP4dGVryFN5xqMnnqhIUh9APEbQWQg8up6rqLqOtpbbFrQD9e SRQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=dbD8O1No6ELbDIE/2OQGZ6qruLLxbx5BCWm7Ga8QiXo=; fh=QYlm5YDIRnf0TNvgVsTQgUkIX+nQmf4Pag0ob76cGl4=; b=GZBLRAS6oacsF+Ntjx15vVumNeNbsNabubLLXJDM8Ghi0QIQctrX0snI+uIcJYwQDw r+FEKatURrQjkuMb8tqlKZWvi+O2tKR1YQ95koU0EE1pD7HyNt8AilGdEV6nq/vCsYHd zQSc3al+utx0k0UDp0xr0d5vsIQuc5vnJEw8WVb6tQr1TKvb7gl7v7VzhlcL0NF2ITTP Gz6k+9gwqvrIZ2hM02NRrFgytU+JcwdFxnhKVmsrcQDwLGzpqOh583xX7fBlfgXRqSwx HMfrr1kw7bPhrp9CQeiSfD8BVwc+Rf9MAd273styhAjr4XgtOeAbx+P+ASbxVMi/jz4W t9Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=bBOkYn4Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id p19-20020a170902b09300b001c36018fdaasi7674769plr.219.2023.12.12.04.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 04:21:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=bBOkYn4Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 38B8D809B9CD; Tue, 12 Dec 2023 04:20:47 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346488AbjLLMUX (ORCPT + 99 others); Tue, 12 Dec 2023 07:20:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346466AbjLLMUJ (ORCPT ); Tue, 12 Dec 2023 07:20:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D48F101; Tue, 12 Dec 2023 04:20:14 -0800 (PST) X-UUID: c7163c0698e811eeba30773df0976c77-20231212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dbD8O1No6ELbDIE/2OQGZ6qruLLxbx5BCWm7Ga8QiXo=; b=bBOkYn4QiHIfjsqbWpIMSXHS0kmYIVFOE6oSp87MLPSwwidje6Mb+Jh9LlgZpfauHO1Oh9tZWiicpYV8DaynTCaJPlveqwPQA3LH9tD+ThIR+1/Ia0FR28iEYYCkuuh4s2dZSTBRNA5A6Jx/BT/i7z83M00ssOrCqyh1zFx6zqs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:5d01109f-7de4-40d2-a89f-5bff6fd6c9c0,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:a8a8b373-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c7163c0698e811eeba30773df0976c77-20231212 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 509732317; Tue, 12 Dec 2023 20:20:03 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Dec 2023 20:20:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Dec 2023 20:20:02 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , CK Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chen-Yu Tsai , Sean Paul , Fei Shao , Bibby Hsieh , , , , , , "Hsiao Chien Sung" Subject: [PATCH v4 17/17] drm/mediatek: Add comments for the structures Date: Tue, 12 Dec 2023 20:19:57 +0800 Message-ID: <20231212121957.19231-18-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231212121957.19231-1-shawn.sung@mediatek.com> References: <20231212121957.19231-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--14.416000-8.000000 X-TMASE-MatchedRID: DmIE4Tvg5l+4pD9RIlWSGkOLK43kW8U2SjyMfjCRfaPfUZT83lbkEJJo t8xOxyL5vhH72H3yPfSvM8tTrzz8JopsQeZV7e/ekDpLRKO9xhSl9VzHf0qr7qvM+zzl/BSTnws uROZLCaS5j7tLcdeHTevPanPbI41jL47TD00zmvIyDra4i6b7VFg3VqSTJ7SoBlt4RZwvTdU4bl 3o5NgJi1hchnpql2OeYVpVTb4KUCIRXrSqR8jJuUhEDfw/93BuYQXxsZnRwoLDTXM3VzSaIpG/q oYvgCpndHIwi5HBo1kEGuB4DQT9H3Mp9PZvqqsOMSjlkes0Ka9/r8x3wtvaX1fXgfL55inv9sUL EBDqysJYA0BuCSp3oHN0bGsqI3dfRcriDaoCTGJIcJTn2HkqsXcF/0kiqyh4937Ck3f1gVGn/hn 1bFHD3d5yDFr9us0hTVsTalxdyw21DfGM6db7Xxes/RxhysDbTxfDNc/bKf56bqISdYJSGr1g9p Qs6Oo9R4+ZNLoF3plfpDE3h+Imb5cFdomgH0lnFEUknJ/kEl7dB/CxWTRRu25FeHtsUoHug45pb 8X/zrO6YE652/HW6BgXfxN81f2+1dAzLJAY5Lu+68HqACCvKA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--14.416000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B0E336AC218068CC60C43F713E6D55F12403E587E79AC0CF073E5DF3B5911E802000:8 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 12 Dec 2023 04:20:47 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785078663330507810 X-GMAIL-MSGID: 1785078663330507810 Add comments for the structures to improve readability. Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 22 ++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 32 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 15 ++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 +++++++ 5 files changed, 97 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index f019737078f6..78e5327ceda7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -164,6 +164,20 @@ static const u32 mt8195_ovl_crc_ofs[] = { DISP_REG_OVL_CRC, }; +/** + * struct mtk_disp_ovl_data - ovl driver data + * @addr: offset of the first layer (layer-0) + * @gmc_bits: gmc (gating memory clock) bit masks for adjusting positivity for ovl + * @layer_nr: layer numbers that ovl supports + * @fmt_rgb565_is_0: whether or not rgb565 is represented as 0 + * @smi_id_en: determine if smi needs to be enabled + * @supports_afbc: determine if ovl supports afbc + * @formats: format table that ovl supports + * @num_formats: number of formats that ovl supports + * @supports_clrfmt_ext: whether the ovl supports clear format (for alpha blend) + * @crc_ofs: crc offset table + * @crc_cnt: count of crc registers (could be more than one bank) + */ struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -178,10 +192,15 @@ struct mtk_disp_ovl_data { size_t crc_cnt; }; -/* +/** * struct mtk_disp_ovl - DISP_OVL driver structure * @crtc: associated crtc to report vblank events to + * @clk: clock of the ovl + * @regs: base address of the ovl register that can be accessed by cpu + * @cmdq_reg: register related info for cmdq (subsys, offset ...etc.) * @data: platform data + * @vblank_cb: callback function when vblank irq happened + * @vblank_cb_data: data to the callback function * @crc: crc related information */ struct mtk_disp_ovl { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index fad728690db7..beefa5804911 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -28,14 +28,30 @@ * struct mtk_drm_crtc - MediaTek specific crtc structure. * @base: crtc object. * @enabled: records whether crtc_enable succeeded + * @pending_needs_vblank: determine if we need to handle vblank event + * @event: the vblank event to handle * @planes: array of 4 drm_plane structures, one for each overlay plane + * @layer_nr: layer numbers that the crtc supports * @pending_planes: whether any plane has pending changes to be applied + * @pending_async_planes: if there is any pending async update + * @cmdq_client: a handler to control cmdq (mbox channel, thread ...etc.) + * @cmdq_handle: cmdq packet to store the commands + * @cmdq_event: cmdq event that the thread is waiting for + * @cmdq_vblank_cnt: vblank count that is dedicated for the cmdq thread + * @cb_blocking_queue: wait queue to determine if cmdq is blocked * @mmsys_dev: pointer to the mmsys device for configuration registers + * @dma_dev: pointer to the dma device (usually rdma) * @mutex: handle to one of the ten disp_mutex streams - * @ddp_comp_nr: number of components in ddp_comp + * @ddp_comp_nr_ori: number of the components excludes the route (origin) + * @max_ddp_comp_nr: maximum number of the components in routes + * @ddp_comp_nr: number of the components in the current path * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc - * - * TODO: Needs update: this header is missing a bunch of member descriptions. + * @conn_route_nr: number of the components in route + * @conn_routes: route to the connector + * @hw_lock: mutex lock to avoid race condition when layer config + * @config_updating: determine if the layer configuration is done + * @crc_provider: get crc provider of the crtc + * @frames: count the frames that are added to crc entry */ struct mtk_drm_crtc { struct drm_crtc base; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 38d08796fae4..af80c9e50d36 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -46,6 +46,38 @@ enum mtk_ddp_comp_type { struct mtk_ddp_comp; struct cmdq_pkt; + +/* struct mtk_ddp_comp_funcs - function pointers of the ddp components + * @clk_enable: enable the clocks of the component + * @clk_disable: disable the clocks of the component + * @config: configure the component + * @start: start (enable) the component + * @stop: stop (disable) the component + * @register_vblank_cb: to register a callback function when vblank irq occurs + * @unregister_vblank_cb: to unregister the callback function from the vblank irq + * @enable_vblank: enable vblank irq + * @disable_vblank: disable vblank irq + * @supported_rotations: return rotation capability of the component + * @layer_nr: how many layers the component supports + * @layer_check: to check if the state of the layer is valid for the component + * @layer_config: to configure the component according to the state of the layer + * @gamma_set: to set gamma for the component + * @bgclr_in_on: turn on background color + * @bgclr_in_off: turn off background color + * @ctm_set: set color transformation matrix + * @dma_dev_get: return the device that uses direct memory access + * @get_formats: get the format that is currently in use by the component + * @get_num_formats: get number of the formats that the component supports + * @connect: connect the sub modules of the component + * @disconnect: disconnect the sub modules of the component + * @add: add the device to the component (mount them in the mutex) + * @remove: remove the device from the component (unmount them from the mutex) + * @encoder_index: get the encoder index of the component + * @crc: return the start of crc array + * @crc_cnt: how many CRCs the component supports + * @crc_entry: get the pointer to the crc entry + * @crc_read: call this function to read crc from the hardware component + */ struct mtk_ddp_comp_funcs { int (*power_on)(struct device *dev); void (*power_off)(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 3d6c1f58a7ec..6430433fd20d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -28,6 +28,21 @@ struct mtk_drm_route { const unsigned int *route_ddp; }; +/** + * struct mtk_mmsys_driver_data - capabilities for the mmsys + * @main_path: path of the main display + * @main_len: length of the main display path + * @ext_path: path of the external display + * @ext_len: length of the external display path + * @third_path: path of the third display + * @third_len: length of the third display path + * @conn_routes: routing table of all the possible connectors + * @conn_routes_num: number of the routing table for the connectors + * @shadow_register: whether or not shadow register is enabled + * @mmsys_id: multi-media system ID + * @mmsys_dev_num: number of devices for in the mmsys as a whole + * @max_pitch: maximum pitch in bytes that the mmsys supports + */ struct mtk_mmsys_driver_data { const unsigned int *main_path; unsigned int main_len; diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 30eb2c3d95c0..eae72deacfd2 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -82,6 +82,17 @@ struct mtk_ethdr_comp { struct cmdq_client_reg cmdq_base; }; +/** + * struct mtk_ethdr - ethdr driver data + * @ethdr_comp: components of ethdr(mixer) + * @ethdr_clk: clocks of ethdr components + * @mmsys_dev: mmsys device that ethdr binds to + * @vblank_cb: callback function when vblank irq occurs + * @vblank_cb_data: data fo vblank callback + * @irq: irq that triggers irq handler + * @reset_ctl: reset control of ethdr + * @crc: crc information + */ struct mtk_ethdr { struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX]; struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];